arch/arm/mach-socfpga/reset_manager_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/reset_manager.h>
  10 #include <asm/arch/system_manager.h>
  11 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  12 #include <linux/iopoll.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 /* Assert or de-assert SoCFPGA reset manager reset. */
  17 void socfpga_per_reset(u32 reset, int set)
  18 {
  19         unsigned long reg;
  20
  21         if (RSTMGR_BANK(reset) == 0)
  22                 reg = RSTMGR_SOC64_MPUMODRST;
  23         else if (RSTMGR_BANK(reset) == 1)
  24                 reg = RSTMGR_SOC64_PER0MODRST;
  25         else if (RSTMGR_BANK(reset) == 2)
  26                 reg = RSTMGR_SOC64_PER1MODRST;
  27         else if (RSTMGR_BANK(reset) == 3)
  28                 reg = RSTMGR_SOC64_BRGMODRST;
  29         else    /* Invalid reset register, do nothing */
  30                 return;
  31
  32         if (set)
  33                 setbits_le32(socfpga_get_rstmgr_addr() + reg,
  34                              1 << RSTMGR_RESET(reset));
  35         else
  36                 clrbits_le32(socfpga_get_rstmgr_addr() + reg,
  37                              1 << RSTMGR_RESET(reset));
  38 }
  39
  40 /*
  41  * Assert reset on every peripheral but L4WD0.
  42  * Watchdog must be kept intact to prevent glitches
  43  * and/or hangs.
  44  */
  45 void socfpga_per_reset_all(void)
  46 {
  47         const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
  48
  49         /* disable all except OCP and l4wd0. OCP disable later */
  50         writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
  51                       socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
  52         writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
  53         writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
  54 }
  55
  56 void socfpga_bridges_reset(int enable)
  57 {
  58         u32 reg;
  59
  60         if (enable) {
  61                 /* clear idle request to all bridges */
  62                 setbits_le32(socfpga_get_sysmgr_addr() +
  63                              SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
  64
  65                 /* Release all bridges from reset state */
  66                 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
  67                              ~0);
  68
  69                 /* Poll until all idleack to 0 */
  70                 read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
  71                                   SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
  72                                   300000);
  73         } else {
  74                 /* set idle request to all bridges */
  75                 writel(~0,
  76                        socfpga_get_sysmgr_addr() +
  77                        SYSMGR_SOC64_NOC_IDLEREQ_SET);
  78
  79                 /* Enable the NOC timeout */
  80                 writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
  81
  82                 /* Poll until all idleack to 1 */
  83                 read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
  84                                   SYSMGR_SOC64_NOC_IDLEACK, reg,
  85                                   reg == (SYSMGR_NOC_H2F_MSK |
  86                                           SYSMGR_NOC_LWH2F_MSK),
  87                                   1000, 300000);
  88
  89                 /* Poll until all idlestatus to 1 */
  90                 read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
  91                                   SYSMGR_SOC64_NOC_IDLESTATUS, reg,
  92                                   reg == (SYSMGR_NOC_H2F_MSK |
  93                                           SYSMGR_NOC_LWH2F_MSK),
  94                                   1000, 300000);
  95
  96                 /* Reset all bridges (except NOR DDR scheduler & F2S) */
  97                 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
  98                              ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
  99                                RSTMGR_BRGMODRST_FPGA2SOC_MASK));
 100
 101                 /* Disable NOC timeout */
 102                 writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
 103         }
 104 }
 105
 106 /*
 107  * Return non-zero if the CPU has been warm reset
 108  */
 109 int cpu_has_been_warmreset(void)
 110 {
 111         return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
 112                         RSTMGR_L4WD_MPU_WARMRESET_MASK;
 113 }
 114
 115 void print_reset_info(void)
 116 {
 117         bool iswd;
 118         int n;
 119         u32 stat = cpu_has_been_warmreset();
 120
 121         printf("Reset state: %s%s", stat ? "Warm " : "Cold",
 122                (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : "");
 123
 124         stat &= ~RSTMGR_STAT_SDMWARMRST;
 125         if (!stat) {
 126                 puts("\n");
 127                 return;
 128         }
 129
 130         n = generic_ffs(stat) - 1;
 131         iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);
 132         printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU",
 133                iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :
 134                (n - RSTMGR_STAT_MPU0RST_BITPOS));
 135 }