1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __IMX8M_PICOPI_H
7 #define __IMX8M_PICOPI_H
9 #include <linux/sizes.h>
10 #include <asm/arch/imx-regs.h>
12 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
14 #ifdef CONFIG_SPL_BUILD
15 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
16 #define CONFIG_SPL_STACK 0x187FF0
17 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
18 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
19 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
20 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
22 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
23 #define CONFIG_MALLOC_F_ADDR 0x182000
24 /* For RAW image gives a error info not panic */
25 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
30 #if defined(CONFIG_CMD_NET)
31 #define CONFIG_FEC_MXC_PHYADDR 1
34 /* Initial environment variables */
35 #define CONFIG_EXTRA_ENV_SETTINGS \
38 "console=ttymxc0,115200\0" \
39 "fdt_addr=0x43000000\0" \
40 "fdt_high=0xffffffffffffffff\0" \
41 "fdt_file=imx8mq-pico-pi.dtb\0" \
42 "initrd_addr=0x43800000\0" \
43 "initrd_high=0xffffffffffffffff\0" \
44 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
46 "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
47 "mmcautodetect=yes\0" \
48 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
50 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
51 "bootscript=echo Running bootscript from mmc ...; source\0" \
52 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
53 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
54 "mmcboot=echo Booting from mmc ...; " \
56 "echo wait for boot; " \
58 "netargs=setenv bootargs console=${console} " \
60 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
61 "netboot=echo Booting from net ...; " \
63 "if test ${ip_dyn} = yes; then " \
64 "setenv get_cmd dhcp; " \
66 "setenv get_cmd tftp; " \
68 "${get_cmd} ${loadaddr} ${image}; " \
71 /* Link Definitions */
73 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
74 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
75 #define CONFIG_SYS_INIT_SP_OFFSET \
76 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
77 #define CONFIG_SYS_INIT_SP_ADDR \
78 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
81 #define CONFIG_SYS_SDRAM_BASE 0x40000000
82 #define PHYS_SDRAM 0x40000000
83 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
85 #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
87 #define CONFIG_SYS_FSL_USDHC_NUM 2
88 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
90 #define CONFIG_SYS_BOOTM_LEN SZ_128M