6 * Copyright (C) 2012 Freescale Semiconductor, Inc.
10 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/errno.h>
19 #include <asm/imx-common/iomux-v3.h>
20 #include <asm/imx-common/boot_mode.h>
21 #include <asm/imx-common/mxc_i2c.h>
22 #include <asm/imx-common/video.h>
24 #include <fsl_esdhc.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/arch/crm_regs.h>
30 #include <ipu_pixfmt.h>
32 #include <asm/arch/sys_proto.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
51 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
53 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
55 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
57 #define DISP_PAD_CTRL (0x10)
59 #define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
61 struct i2c_pads_info i2c_pad_info1 = {
63 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
64 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
65 .gp = IMX_GPIO_NR(5, 27)
68 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
69 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
70 .gp = IMX_GPIO_NR(5, 26)
74 struct i2c_pads_info i2c_pad_info2 = {
76 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
77 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
78 .gp = IMX_GPIO_NR(4, 12)
81 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
82 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
83 .gp = IMX_GPIO_NR(4, 13)
87 struct i2c_pads_info i2c_pad_info3 = {
89 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
90 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
91 .gp = IMX_GPIO_NR(3, 17)
94 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
95 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
96 .gp = IMX_GPIO_NR(3, 18)
102 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
107 iomux_v3_cfg_t const uart1_pads[] = {
108 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
109 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
112 iomux_v3_cfg_t const uart5_pads[] = {
113 MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
114 MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
117 iomux_v3_cfg_t const gpio_pads[] = {
119 MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
120 /* spi flash WP protect */
121 MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
122 /* backlight enable */
123 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
125 MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
127 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
129 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
131 MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
133 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
135 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
137 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
140 static iomux_v3_cfg_t const misc_pads[] = {
141 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
142 /* OTG Power enable */
143 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
144 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
147 iomux_v3_cfg_t const enet_pads[] = {
148 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
149 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
150 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
151 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
152 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
153 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
154 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
155 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
156 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
157 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
160 static void setup_iomux_enet(void)
162 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
164 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
166 /* set GPIO_16 as ENET_REF_CLK_OUT */
167 setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
170 iomux_v3_cfg_t const usdhc1_pads[] = {
171 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
173 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
174 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
175 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
176 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179 iomux_v3_cfg_t const usdhc2_pads[] = {
180 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
181 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
182 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
183 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
184 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
185 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
188 iomux_v3_cfg_t const ecspi4_pads[] = {
189 MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
190 MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
191 MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
192 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
195 static iomux_v3_cfg_t const display_pads[] = {
196 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
197 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
198 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
199 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
200 MX6_PAD_DI0_PIN4__GPIO4_IO20,
201 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
202 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
203 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
204 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
205 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
206 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
207 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
208 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
209 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
210 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
211 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
212 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
213 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
214 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
215 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
216 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
217 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
218 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
219 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
220 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
221 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
222 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
223 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
224 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
227 static iomux_v3_cfg_t const backlight_pads[] = {
228 MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
229 MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
230 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
233 int board_spi_cs_gpio(unsigned bus, unsigned cs)
235 return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
236 ? (IMX_GPIO_NR(3, 20)) : -1;
239 static void setup_spi(void)
243 imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
244 for (i = 0; i < 3; i++)
245 enable_spi_clk(true, i);
247 /* set cs1 to high */
248 gpio_direction_output(ECSPI4_CS1, 1);
251 static void setup_iomux_gpio(void)
253 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
256 static void setup_iomux_uart(void)
258 imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
261 #ifdef CONFIG_FSL_ESDHC
262 struct fsl_esdhc_cfg usdhc_cfg[2] = {
267 int board_mmc_getcd(struct mmc *mmc)
272 int board_mmc_init(bd_t *bis)
274 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
275 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
277 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
278 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
280 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
281 fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
286 * Do not overwrite the console
287 * Use always serial for U-Boot console
289 int overwrite_console(void)
294 int board_eth_init(bd_t *bis)
296 struct iomuxc *iomuxc_regs =
297 (struct iomuxc *)IOMUXC_BASE_ADDR;
301 /* clear gpr1[14], gpr1[18:17] to select anatop clock */
302 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
304 ret = enable_fec_anatop_clock(ENET_50MHZ);
308 return cpu_eth_init(bis);
310 #if defined(CONFIG_VIDEO_IPUV3)
312 static void enable_lvds(struct display_info_t const *dev)
314 imx_iomux_v3_setup_multiple_pads(
316 ARRAY_SIZE(display_pads));
317 imx_iomux_v3_setup_multiple_pads(
319 ARRAY_SIZE(backlight_pads));
321 /* enable backlight PWM 3 */
322 if (pwm_init(2, 0, 0))
324 /* duty cycle 200ns, period: 3000ns */
325 if (pwm_config(2, 200, 3000))
332 puts("error init pwm for backlight\n");
336 struct display_info_t const displays[] = {
340 .pixfmt = IPU_PIX_FMT_RGB24,
342 .enable = enable_lvds,
356 .vmode = FB_VMODE_NONINTERLACED
360 size_t display_count = ARRAY_SIZE(displays);
362 static void setup_display(void)
364 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
369 reg = readl(&mxc_ccm->cs2cdr);
370 /* select pll 5 clock */
371 reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
372 reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
373 writel(reg, &mxc_ccm->cs2cdr);
375 imx_iomux_v3_setup_multiple_pads(backlight_pads,
376 ARRAY_SIZE(backlight_pads));
379 /* no console on this board */
380 int board_cfb_skip(void)
386 int board_early_init_f(void)
391 #if defined(CONFIG_VIDEO_IPUV3)
397 iomux_v3_cfg_t nfc_pads[] = {
398 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
399 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
400 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
401 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
402 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
403 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
404 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
405 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
406 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
407 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
408 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
409 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
410 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
411 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
412 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
413 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
414 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
415 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
416 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
419 static void setup_gpmi_nand(void)
421 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
423 /* config gpmi nand iomux */
424 imx_iomux_v3_setup_multiple_pads(nfc_pads,
425 ARRAY_SIZE(nfc_pads));
427 /* config gpmi and bch clock to 100 MHz */
428 clrsetbits_le32(&mxc_ccm->cs2cdr,
429 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
430 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
431 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
432 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
433 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
434 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
436 /* enable gpmi and bch clock gating */
437 setbits_le32(&mxc_ccm->CCGR4,
438 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
439 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
440 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
441 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
442 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
444 /* enable apbh clock gating */
445 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
450 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
452 /* address of boot parameters */
453 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
457 setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
459 setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
461 setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
464 /* i2c4 not used, set it to gpio input */
465 gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
466 gpio_direction_input(IMX_GPIO_NR(1, 7));
467 gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
468 gpio_direction_input(IMX_GPIO_NR(1, 8));
470 /* SPI NOR Flash read only */
471 gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
472 gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
473 gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
476 gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
477 gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
479 gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
480 gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
481 gpio_request(IMX_GPIO_NR(1, 4), "LED red");
482 gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
483 gpio_request(IMX_GPIO_NR(1, 5), "LED green");
484 gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
485 gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
486 gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
490 /* GPIO_1 for USB_OTG_ID */
491 setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK);
492 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
499 puts("Board: aristaitenos\n");
503 #ifdef CONFIG_USB_EHCI_MX6
504 int board_ehci_hcd_init(int port)
508 ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
510 gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
511 ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
513 gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
517 int board_ehci_power(int port, int on)
520 gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
522 gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);