arch/arm/dts/mt7981.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2022 MediaTek Inc.
   4  * Author: Sam Shih <[email protected]>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/mt7981-clk.h>
  10 #include <dt-bindings/reset/mt7629-reset.h>
  11 #include <dt-bindings/pinctrl/mt65xx.h>
  12
  13 / {
  14         compatible = "mediatek,mt7981";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a53";
  24                         reg = <0x0>;
  25                         mediatek,hwver = <&hwver>;
  26                 };
  27                 cpu1: cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a53";
  30                         reg = <0x1>;
  31                         mediatek,hwver = <&hwver>;
  32                 };
  33         };
  34
  35         gpt_clk: gpt_dummy20m {
  36                 compatible = "fixed-clock";
  37                 clock-frequency = <13000000>;
  38                 #clock-cells = <0>;
  39                 bootph-all;
  40         };
  41
  42         hwver: hwver {
  43                 compatible = "mediatek,hwver", "syscon";
  44                 reg = <0x8000000 0x1000>;
  45         };
  46
  47         timer {
  48                 compatible = "arm,armv8-timer";
  49                 interrupt-parent = <&gic>;
  50                 clock-frequency = <13000000>;
  51                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  52                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  53                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  54                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  55                 arm,cpu-registers-not-fw-configured;
  56         };
  57
  58         timer0: timer@10008000 {
  59                 compatible = "mediatek,mt7986-timer";
  60                 reg = <0x10008000 0x1000>;
  61                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  62                 clocks = <&gpt_clk>;
  63                 clock-names = "gpt-clk";
  64                 bootph-all;
  65         };
  66
  67         watchdog: watchdog@1001c000 {
  68                 compatible = "mediatek,mt7986-wdt";
  69                 reg = <0x1001c000 0x1000>;
  70                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  71                 #reset-cells = <1>;
  72                 status = "disabled";
  73         };
  74
  75         gic: interrupt-controller@c000000 {
  76                 compatible = "arm,gic-v3";
  77                 #interrupt-cells = <3>;
  78                 interrupt-parent = <&gic>;
  79                 interrupt-controller;
  80                 reg = <0x0c000000 0x40000>,  /* GICD */
  81                       <0x0c080000 0x200000>; /* GICR */
  82
  83                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  84         };
  85
  86         fixed_plls: apmixedsys@1001e000 {
  87                 compatible = "mediatek,mt7981-fixed-plls";
  88                 reg = <0x1001e000 0x1000>;
  89                 #clock-cells = <1>;
  90                 bootph-all;
  91         };
  92
  93         topckgen: topckgen@1001b000 {
  94                 compatible = "mediatek,mt7981-topckgen";
  95                 reg = <0x1001b000 0x1000>;
  96                 clock-parent = <&fixed_plls>;
  97                 #clock-cells = <1>;
  98                 bootph-all;
  99         };
 100
 101         infracfg: infracfg@10001000 {
 102                 compatible = "mediatek,mt7981-infracfg";
 103                 reg = <0x10001000 0x30>;
 104                 clock-parent = <&topckgen>;
 105                 #clock-cells = <1>;
 106                 bootph-all;
 107         };
 108
 109         pinctrl: pinctrl@11d00000 {
 110                 compatible = "mediatek,mt7981-pinctrl";
 111                 reg = <0x11d00000 0x1000>,
 112                       <0x11c00000 0x1000>,
 113                       <0x11c10000 0x1000>,
 114                       <0x11d20000 0x1000>,
 115                       <0x11e00000 0x1000>,
 116                       <0x11e20000 0x1000>,
 117                       <0x11f00000 0x1000>,
 118                       <0x11f10000 0x1000>,
 119                       <0x1000b000 0x1000>;
 120                 reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base",
 121                             "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base",
 122                             "iocfg_tm_base", "iocfg_tl_base", "eint";
 123                 gpio: gpio-controller {
 124                         gpio-controller;
 125                         #gpio-cells = <2>;
 126                 };
 127         };
 128
 129         pwm: pwm@10048000 {
 130                 compatible = "mediatek,mt7981-pwm";
 131                 reg = <0x10048000 0x1000>;
 132                 #clock-cells = <1>;
 133                 #pwm-cells = <2>;
 134                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 135                 clocks = <&topckgen CK_TOP_PWM_SEL>,
 136                          <&infracfg CK_INFRA_PWM_BSEL>,
 137                          <&infracfg CK_INFRA_PWM1_CK>,
 138                          <&infracfg CK_INFRA_PWM2_CK>,
 139                          <&infracfg CK_INFRA_PWM3_CK>;
 140                 assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
 141                 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
 142                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
 143                 status = "disabled";
 144         };
 145
 146         i2c0: i2c@11007000 {
 147                 compatible = "mediatek,mt7981-i2c";
 148                 reg = <0x11007000 0x1000>,
 149                       <0x10217080 0x80>;
 150                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 151                 clock-div = <1>;
 152                 clocks = <&infracfg CK_INFRA_I2C0_CK>,
 153                          <&infracfg CK_INFRA_AP_DMA_CK>;
 154                 clock-names = "main", "dma";
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157                 status = "disabled";
 158         };
 159
 160         uart0: serial@11002000 {
 161                 compatible = "mediatek,hsuart";
 162                 reg = <0x11002000 0x400>;
 163                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 164                 clocks = <&infracfg CK_INFRA_UART0_CK>;
 165                 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
 166                                   <&infracfg CK_INFRA_UART0_SEL>;
 167                 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
 168                                          <&topckgen CK_TOP_UART_SEL>;
 169                 mediatek,force-highspeed;
 170                 status = "disabled";
 171                 bootph-all;
 172         };
 173
 174         uart1: serial@11003000 {
 175                 compatible = "mediatek,hsuart";
 176                 reg = <0x11003000 0x400>;
 177                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 178                 clocks = <&infracfg CK_INFRA_UART1_CK>;
 179                 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
 180                                   <&infracfg CK_INFRA_UART1_SEL>;
 181                 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
 182                                          <&topckgen CK_TOP_UART_SEL>;
 183                 mediatek,force-highspeed;
 184                 status = "disabled";
 185         };
 186
 187         uart2: serial@11004000 {
 188                 compatible = "mediatek,hsuart";
 189                 reg = <0x11004000 0x400>;
 190                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 191                 clocks = <&infracfg CK_INFRA_UART2_CK>;
 192                 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
 193                                   <&infracfg CK_INFRA_UART2_SEL>;
 194                 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
 195                                          <&topckgen CK_TOP_UART_SEL>;
 196                 mediatek,force-highspeed;
 197                 status = "disabled";
 198         };
 199
 200         snand: snand@11005000 {
 201                 compatible = "mediatek,mt7986-snand";
 202                 reg = <0x11005000 0x1000>,
 203                       <0x11006000 0x1000>;
 204                 reg-names = "nfi", "ecc";
 205                 clocks = <&infracfg CK_INFRA_SPINFI1_CK>,
 206                          <&infracfg CK_INFRA_NFI1_CK>,
 207                          <&infracfg CK_INFRA_NFI_HCK_CK>;
 208                 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
 209                 assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
 210                                   <&topckgen CK_TOP_NFI1X_SEL>;
 211                 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
 212                                          <&topckgen CK_TOP_CB_M_D8>;
 213                 status = "disabled";
 214         };
 215
 216         ethsys: syscon@15000000 {
 217                 compatible = "mediatek,mt7981-ethsys", "syscon";
 218                 reg = <0x15000000 0x1000>;
 219                 clock-parent = <&topckgen>;
 220                 #clock-cells = <1>;
 221                 #reset-cells = <1>;
 222         };
 223
 224         eth: ethernet@15100000 {
 225                 compatible = "mediatek,mt7981-eth", "syscon";
 226                 reg = <0x15100000 0x20000>;
 227                 resets = <&ethsys ETHSYS_FE_RST>;
 228                 reset-names = "fe";
 229                 mediatek,ethsys = <&ethsys>;
 230                 mediatek,sgmiisys = <&sgmiisys0>;
 231                 mediatek,infracfg = <&topmisc>;
 232                 #address-cells = <1>;
 233                 #size-cells = <0>;
 234                 status = "disabled";
 235         };
 236
 237         sgmiisys0: syscon@10060000 {
 238                 compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
 239                 reg = <0x10060000 0x1000>;
 240                 pn_swap;
 241                 #clock-cells = <1>;
 242         };
 243
 244         sgmiisys1: syscon@10070000 {
 245                 compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
 246                 reg = <0x10070000 0x1000>;
 247                 #clock-cells = <1>;
 248         };
 249
 250         topmisc: topmisc@11d10000 {
 251                 compatible = "mediatek,mt7981-topmisc", "syscon";
 252                 reg = <0x11d10000 0x10000>;
 253                 #clock-cells = <1>;
 254         };
 255
 256         spi0: spi@1100a000 {
 257                 compatible = "mediatek,ipm-spi";
 258                 reg = <0x1100a000 0x100>;
 259                 clocks = <&infracfg CK_INFRA_SPI0_CK>,
 260                          <&topckgen CK_TOP_SPI_SEL>;
 261                 assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
 262                                   <&infracfg CK_INFRA_SPI0_SEL>;
 263                 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
 264                                          <&topckgen CK_TOP_SPI_SEL>;
 265                 clock-names = "spi-clk", "sel-clk";
 266                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 267                 status = "disabled";
 268         };
 269
 270         spi1: spi@1100b000 {
 271                 compatible = "mediatek,ipm-spi";
 272                 reg = <0x1100b000 0x100>;
 273                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 274                 clocks = <&infracfg CK_INFRA_SPI1_CK>,
 275                          <&topckgen CK_TOP_SPIM_MST_SEL>;
 276                 assigned-clocks = <&topckgen CK_TOP_SPIM_MST_SEL>,
 277                                   <&infracfg CK_INFRA_SPI1_SEL>;
 278                 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
 279                                          <&topckgen CK_TOP_SPIM_MST_SEL>;
 280                 clock-names = "spi-clk", "sel-clk";
 281                 status = "disabled";
 282         };
 283
 284         spi2: spi@11009000 {
 285                 compatible = "mediatek,ipm-spi";
 286                 reg = <0x11009000 0x100>;
 287                 clocks = <&infracfg CK_INFRA_SPI2_CK>,
 288                          <&topckgen CK_TOP_SPI_SEL>;
 289                 assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
 290                                   <&infracfg CK_INFRA_SPI2_SEL>;
 291                 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
 292                                          <&topckgen CK_TOP_SPI_SEL>;
 293                 clock-names = "spi-clk", "sel-clk";
 294                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 295                 status = "disabled";
 296         };
 297
 298         mmc0: mmc@11230000 {
 299                 compatible = "mediatek,mt7981-mmc";
 300                 reg = <0x11230000 0x1000>,
 301                       <0x11C20000 0x1000>;
 302                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&topckgen CK_TOP_EMMC_400M>,
 304                          <&topckgen CK_TOP_EMMC_208M>,
 305                          <&infracfg CK_INFRA_MSDC_CK>;
 306                 assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
 307                                   <&topckgen CK_TOP_EMMC_208M_SEL>;
 308                 assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,
 309                                          <&topckgen CK_TOP_CB_M_D2>;
 310                 clock-names = "source", "hclk", "source_cg";
 311                 status = "disabled";
 312         };
 313
 314 };