2 * DHCOM DH-iMX6 PDK board support
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/sata.h>
22 #include <environment.h>
24 #include <fsl_esdhc.h>
32 #include <usb/ehci-ci.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 #define I2C_PAD_CTRL \
37 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
40 #define EEPROM_I2C_ADDRESS 0x50
42 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
44 static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
46 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
47 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
48 .gp = IMX_GPIO_NR(3, 21)
51 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
52 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
53 .gp = IMX_GPIO_NR(3, 28)
57 static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
59 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
60 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
61 .gp = IMX_GPIO_NR(4, 12)
64 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
65 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
66 .gp = IMX_GPIO_NR(4, 13)
70 static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
72 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
73 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
74 .gp = IMX_GPIO_NR(1, 3)
77 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
78 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
79 .gp = IMX_GPIO_NR(1, 6)
83 static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
85 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
86 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
87 .gp = IMX_GPIO_NR(3, 21)
90 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
91 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
92 .gp = IMX_GPIO_NR(3, 28)
96 static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
98 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
99 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
100 .gp = IMX_GPIO_NR(4, 12)
103 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
104 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
105 .gp = IMX_GPIO_NR(4, 13)
109 static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
111 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
112 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
113 .gp = IMX_GPIO_NR(1, 3)
116 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
117 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
118 .gp = IMX_GPIO_NR(1, 6)
124 gd->ram_size = imx_ddr_size();
129 * Do not overwrite the console
130 * Use always serial for U-Boot console
132 int overwrite_console(void)
137 #ifdef CONFIG_FEC_MXC
138 static void eth_phy_reset(void)
141 gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
143 gpio_set_value(IMX_GPIO_NR(5, 0), 1);
146 gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
149 * KSZ9021 PHY needs at least 10 mSec after PHY reset
150 * is released to stabilize
155 static int setup_fec_clock(void)
157 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
159 /* set gpr1[21] to select anatop clock */
160 clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
162 return enable_fec_anatop_clock(0, ENET_50MHZ);
165 int board_eth_init(bd_t *bis)
167 uint32_t base = IMX_FEC_BASE;
168 struct mii_dev *bus = NULL;
169 struct phy_device *phydev = NULL;
175 bus = fec_get_miibus(base, -1);
180 phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
182 printf("Ethernet PHY not found!\n");
186 return fec_probe(bis, -1, base, bus, phydev);
190 #ifdef CONFIG_FSL_ESDHC
192 #define USDHC2_CD_GPIO IMX_GPIO_NR(6, 16)
193 #define USDHC3_CD_GPIO IMX_GPIO_NR(7, 8)
195 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
196 { USDHC2_BASE_ADDR },
197 { USDHC3_BASE_ADDR },
198 { USDHC4_BASE_ADDR },
201 int board_mmc_getcd(struct mmc *mmc)
203 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
205 switch (cfg->esdhc_base) {
206 case USDHC2_BASE_ADDR:
207 return gpio_get_value(USDHC2_CD_GPIO);
208 case USDHC3_BASE_ADDR:
209 return !gpio_get_value(USDHC3_CD_GPIO);
210 case USDHC4_BASE_ADDR:
211 return 1; /* eMMC/uSDHC4 is always present */
217 int board_mmc_init(bd_t *bis)
222 * According to the board_mmc_init() the following map is done:
223 * (U-Boot device node) (Physical Port)
228 gpio_direction_input(USDHC2_CD_GPIO);
229 gpio_direction_input(USDHC3_CD_GPIO);
231 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
232 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
233 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
235 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
236 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
245 #ifdef CONFIG_USB_EHCI_MX6
246 static void setup_usb(void)
249 * Set daisy chain for otg_pin_id on MX6Q.
250 * For MX6DL, this bit is reserved.
252 imx_iomux_set_gpr_register(1, 13, 1, 0);
255 int board_usb_phy_mode(int port)
258 return USB_INIT_HOST;
260 return USB_INIT_DEVICE;
263 int board_ehci_power(int port, int on)
269 gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
272 printf("MXC USB port %d not yet supported\n", port);
280 static int setup_dhcom_mac_from_fuse(void)
282 unsigned char enetaddr[6];
285 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
286 if (ret) /* ethaddr is already set */
289 imx_get_mac_from_fuse(0, enetaddr);
291 if (is_valid_ethaddr(enetaddr)) {
292 eth_env_set_enetaddr("ethaddr", enetaddr);
296 ret = i2c_set_bus_num(2);
298 printf("Error switching I2C bus!\n");
302 ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
304 printf("Error reading configuration EEPROM!\n");
308 if (is_valid_ethaddr(enetaddr))
309 eth_env_set_enetaddr("ethaddr", enetaddr);
314 int board_early_init_f(void)
316 #ifdef CONFIG_USB_EHCI_MX6
323 #ifdef CONFIG_MXC_SPI
324 int board_spi_cs_gpio(unsigned bus, unsigned cs)
326 if (bus == 0 && cs == 0)
327 return IMX_GPIO_NR(2, 30);
335 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
337 /* address of boot parameters */
338 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
340 /* Enable eim_slow clocks */
341 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
343 #ifdef CONFIG_SYS_I2C_MXC
345 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
346 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
347 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
349 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
350 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
351 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
359 setup_dhcom_mac_from_fuse();
364 #ifdef CONFIG_CMD_BMODE
365 static const struct boot_mode board_boot_modes[] = {
366 /* 4 bit bus width */
367 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
368 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
369 /* 8 bit bus width */
370 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
375 #define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
376 #define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
377 #define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
379 static int board_get_hwcode(void)
383 gpio_direction_input(HW_CODE_BIT_0);
384 gpio_direction_input(HW_CODE_BIT_1);
385 gpio_direction_input(HW_CODE_BIT_2);
387 /* HW 100 + HW 200 = 00b; HW 300 = 01b */
388 hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
389 (gpio_get_value(HW_CODE_BIT_1) << 1) |
390 gpio_get_value(HW_CODE_BIT_0)) + 2;
395 int board_late_init(void)
400 hw_code = board_get_hwcode();
402 switch (get_cpu_type()) {
403 case MXC_CPU_MX6SOLO:
404 snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
407 snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
410 snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
413 snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
416 snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
420 env_set("dhcom", buf);
422 #ifdef CONFIG_CMD_BMODE
423 add_board_boot_modes(board_boot_modes);
430 puts("Board: DHCOM i.MX6\n");