arch/powerpc/cpu/mpc85xx/Kconfig

   1 menu "mpc85xx CPU"
   2         depends on MPC85xx
   3
   4 config SYS_CPU
   5         default "mpc85xx"
   6
   7 choice
   8         prompt "Target select"
   9         optional
  10
  11 config TARGET_SBC8548
  12         bool "Support sbc8548"
  13         select ARCH_MPC8548
  14
  15 config TARGET_SOCRATES
  16         bool "Support socrates"
  17         select ARCH_MPC8544
  18
  19 config TARGET_B4420QDS
  20         bool "Support B4420QDS"
  21         select ARCH_B4420
  22         select SUPPORT_SPL
  23         select PHYS_64BIT
  24
  25 config TARGET_B4860QDS
  26         bool "Support B4860QDS"
  27         select ARCH_B4860
  28         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  29         select SUPPORT_SPL
  30         select PHYS_64BIT
  31
  32 config TARGET_BSC9131RDB
  33         bool "Support BSC9131RDB"
  34         select ARCH_BSC9131
  35         select SUPPORT_SPL
  36         select BOARD_EARLY_INIT_F
  37
  38 config TARGET_BSC9132QDS
  39         bool "Support BSC9132QDS"
  40         select ARCH_BSC9132
  41         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  42         select SUPPORT_SPL
  43         select BOARD_EARLY_INIT_F
  44
  45 config TARGET_C29XPCIE
  46         bool "Support C29XPCIE"
  47         select ARCH_C29X
  48         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  49         select SUPPORT_SPL
  50         select SUPPORT_TPL
  51         select PHYS_64BIT
  52
  53 config TARGET_P3041DS
  54         bool "Support P3041DS"
  55         select PHYS_64BIT
  56         select ARCH_P3041
  57         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  58
  59 config TARGET_P4080DS
  60         bool "Support P4080DS"
  61         select PHYS_64BIT
  62         select ARCH_P4080
  63         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  64
  65 config TARGET_P5020DS
  66         bool "Support P5020DS"
  67         select PHYS_64BIT
  68         select ARCH_P5020
  69         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  70
  71 config TARGET_P5040DS
  72         bool "Support P5040DS"
  73         select PHYS_64BIT
  74         select ARCH_P5040
  75         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  76
  77 config TARGET_MPC8536DS
  78         bool "Support MPC8536DS"
  79         select ARCH_MPC8536
  80 # Use DDR3 controller with DDR2 DIMMs on this board
  81         select SYS_FSL_DDRC_GEN3
  82
  83 config TARGET_MPC8540ADS
  84         bool "Support MPC8540ADS"
  85         select ARCH_MPC8540
  86
  87 config TARGET_MPC8541CDS
  88         bool "Support MPC8541CDS"
  89         select ARCH_MPC8541
  90
  91 config TARGET_MPC8544DS
  92         bool "Support MPC8544DS"
  93         select ARCH_MPC8544
  94
  95 config TARGET_MPC8548CDS
  96         bool "Support MPC8548CDS"
  97         select ARCH_MPC8548
  98
  99 config TARGET_MPC8555CDS
 100         bool "Support MPC8555CDS"
 101         select ARCH_MPC8555
 102
 103 config TARGET_MPC8560ADS
 104         bool "Support MPC8560ADS"
 105         select ARCH_MPC8560
 106
 107 config TARGET_MPC8568MDS
 108         bool "Support MPC8568MDS"
 109         select ARCH_MPC8568
 110
 111 config TARGET_MPC8569MDS
 112         bool "Support MPC8569MDS"
 113         select ARCH_MPC8569
 114
 115 config TARGET_MPC8572DS
 116         bool "Support MPC8572DS"
 117         select ARCH_MPC8572
 118 # Use DDR3 controller with DDR2 DIMMs on this board
 119         select SYS_FSL_DDRC_GEN3
 120
 121 config TARGET_P1010RDB_PA
 122         bool "Support P1010RDB_PA"
 123         select ARCH_P1010
 124         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 125         select SUPPORT_SPL
 126         select SUPPORT_TPL
 127
 128 config TARGET_P1010RDB_PB
 129         bool "Support P1010RDB_PB"
 130         select ARCH_P1010
 131         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 132         select SUPPORT_SPL
 133         select SUPPORT_TPL
 134
 135 config TARGET_P1022DS
 136         bool "Support P1022DS"
 137         select ARCH_P1022
 138         select SUPPORT_SPL
 139         select SUPPORT_TPL
 140
 141 config TARGET_P1023RDB
 142         bool "Support P1023RDB"
 143         select ARCH_P1023
 144
 145 config TARGET_P1020MBG
 146         bool "Support P1020MBG-PC"
 147         select SUPPORT_SPL
 148         select SUPPORT_TPL
 149         select ARCH_P1020
 150
 151 config TARGET_P1020RDB_PC
 152         bool "Support P1020RDB-PC"
 153         select SUPPORT_SPL
 154         select SUPPORT_TPL
 155         select ARCH_P1020
 156
 157 config TARGET_P1020RDB_PD
 158         bool "Support P1020RDB-PD"
 159         select SUPPORT_SPL
 160         select SUPPORT_TPL
 161         select ARCH_P1020
 162
 163 config TARGET_P1020UTM
 164         bool "Support P1020UTM"
 165         select SUPPORT_SPL
 166         select SUPPORT_TPL
 167         select ARCH_P1020
 168
 169 config TARGET_P1021RDB
 170         bool "Support P1021RDB"
 171         select SUPPORT_SPL
 172         select SUPPORT_TPL
 173         select ARCH_P1021
 174
 175 config TARGET_P1024RDB
 176         bool "Support P1024RDB"
 177         select SUPPORT_SPL
 178         select SUPPORT_TPL
 179         select ARCH_P1024
 180
 181 config TARGET_P1025RDB
 182         bool "Support P1025RDB"
 183         select SUPPORT_SPL
 184         select SUPPORT_TPL
 185         select ARCH_P1025
 186
 187 config TARGET_P2020RDB
 188         bool "Support P2020RDB-PC"
 189         select SUPPORT_SPL
 190         select SUPPORT_TPL
 191         select ARCH_P2020
 192
 193 config TARGET_P1_TWR
 194         bool "Support p1_twr"
 195         select ARCH_P1025
 196
 197 config TARGET_P2041RDB
 198         bool "Support P2041RDB"
 199         select ARCH_P2041
 200         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 201         select PHYS_64BIT
 202
 203 config TARGET_QEMU_PPCE500
 204         bool "Support qemu-ppce500"
 205         select ARCH_QEMU_E500
 206         select PHYS_64BIT
 207
 208 config TARGET_T1024QDS
 209         bool "Support T1024QDS"
 210         select ARCH_T1024
 211         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 212         select SUPPORT_SPL
 213         select PHYS_64BIT
 214
 215 config TARGET_T1023RDB
 216         bool "Support T1023RDB"
 217         select ARCH_T1023
 218         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 219         select SUPPORT_SPL
 220         select PHYS_64BIT
 221
 222 config TARGET_T1024RDB
 223         bool "Support T1024RDB"
 224         select ARCH_T1024
 225         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 226         select SUPPORT_SPL
 227         select PHYS_64BIT
 228
 229 config TARGET_T1040QDS
 230         bool "Support T1040QDS"
 231         select ARCH_T1040
 232         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 233         select PHYS_64BIT
 234
 235 config TARGET_T1040RDB
 236         bool "Support T1040RDB"
 237         select ARCH_T1040
 238         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 239         select SUPPORT_SPL
 240         select PHYS_64BIT
 241
 242 config TARGET_T1040D4RDB
 243         bool "Support T1040D4RDB"
 244         select ARCH_T1040
 245         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 246         select SUPPORT_SPL
 247         select PHYS_64BIT
 248
 249 config TARGET_T1042RDB
 250         bool "Support T1042RDB"
 251         select ARCH_T1042
 252         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 253         select SUPPORT_SPL
 254         select PHYS_64BIT
 255
 256 config TARGET_T1042D4RDB
 257         bool "Support T1042D4RDB"
 258         select ARCH_T1042
 259         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 260         select SUPPORT_SPL
 261         select PHYS_64BIT
 262
 263 config TARGET_T1042RDB_PI
 264         bool "Support T1042RDB_PI"
 265         select ARCH_T1042
 266         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 267         select SUPPORT_SPL
 268         select PHYS_64BIT
 269
 270 config TARGET_T2080QDS
 271         bool "Support T2080QDS"
 272         select ARCH_T2080
 273         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 274         select SUPPORT_SPL
 275         select PHYS_64BIT
 276
 277 config TARGET_T2080RDB
 278         bool "Support T2080RDB"
 279         select ARCH_T2080
 280         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 281         select SUPPORT_SPL
 282         select PHYS_64BIT
 283
 284 config TARGET_T2081QDS
 285         bool "Support T2081QDS"
 286         select ARCH_T2081
 287         select SUPPORT_SPL
 288         select PHYS_64BIT
 289
 290 config TARGET_T4160QDS
 291         bool "Support T4160QDS"
 292         select ARCH_T4160
 293         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 294         select SUPPORT_SPL
 295         select PHYS_64BIT
 296
 297 config TARGET_T4160RDB
 298         bool "Support T4160RDB"
 299         select ARCH_T4160
 300         select SUPPORT_SPL
 301         select PHYS_64BIT
 302
 303 config TARGET_T4240QDS
 304         bool "Support T4240QDS"
 305         select ARCH_T4240
 306         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 307         select SUPPORT_SPL
 308         select PHYS_64BIT
 309
 310 config TARGET_T4240RDB
 311         bool "Support T4240RDB"
 312         select ARCH_T4240
 313         select SUPPORT_SPL
 314         select PHYS_64BIT
 315
 316 config TARGET_CONTROLCENTERD
 317         bool "Support controlcenterd"
 318         select ARCH_P1022
 319
 320 config TARGET_KMP204X
 321         bool "Support kmp204x"
 322         select ARCH_P2041
 323         select PHYS_64BIT
 324         imply CMD_CRAMFS
 325
 326 config TARGET_XPEDITE520X
 327         bool "Support xpedite520x"
 328         select ARCH_MPC8548
 329
 330 config TARGET_XPEDITE537X
 331         bool "Support xpedite537x"
 332         select ARCH_MPC8572
 333 # Use DDR3 controller with DDR2 DIMMs on this board
 334         select SYS_FSL_DDRC_GEN3
 335
 336 config TARGET_XPEDITE550X
 337         bool "Support xpedite550x"
 338         select ARCH_P2020
 339
 340 config TARGET_UCP1020
 341         bool "Support uCP1020"
 342         select ARCH_P1020
 343
 344 config TARGET_CYRUS_P5020
 345         bool "Support Varisys Cyrus P5020"
 346         select ARCH_P5020
 347         select PHYS_64BIT
 348
 349 config TARGET_CYRUS_P5040
 350          bool "Support Varisys Cyrus P5040"
 351         select ARCH_P5040
 352         select PHYS_64BIT
 353
 354 endchoice
 355
 356 config ARCH_B4420
 357         bool
 358         select E500MC
 359         select E6500
 360         select FSL_LAW
 361         select SYS_FSL_DDR_VER_47
 362         select SYS_FSL_ERRATUM_A004477
 363         select SYS_FSL_ERRATUM_A005871
 364         select SYS_FSL_ERRATUM_A006379
 365         select SYS_FSL_ERRATUM_A006384
 366         select SYS_FSL_ERRATUM_A006475
 367         select SYS_FSL_ERRATUM_A006593
 368         select SYS_FSL_ERRATUM_A007075
 369         select SYS_FSL_ERRATUM_A007186
 370         select SYS_FSL_ERRATUM_A007212
 371         select SYS_FSL_ERRATUM_A009942
 372         select SYS_FSL_HAS_DDR3
 373         select SYS_FSL_HAS_SEC
 374         select SYS_FSL_QORIQ_CHASSIS2
 375         select SYS_FSL_SEC_BE
 376         select SYS_FSL_SEC_COMPAT_4
 377         select SYS_PPC64
 378         select FSL_IFC
 379
 380 config ARCH_B4860
 381         bool
 382         select E500MC
 383         select E6500
 384         select FSL_LAW
 385         select SYS_FSL_DDR_VER_47
 386         select SYS_FSL_ERRATUM_A004477
 387         select SYS_FSL_ERRATUM_A005871
 388         select SYS_FSL_ERRATUM_A006379
 389         select SYS_FSL_ERRATUM_A006384
 390         select SYS_FSL_ERRATUM_A006475
 391         select SYS_FSL_ERRATUM_A006593
 392         select SYS_FSL_ERRATUM_A007075
 393         select SYS_FSL_ERRATUM_A007186
 394         select SYS_FSL_ERRATUM_A007212
 395         select SYS_FSL_ERRATUM_A007907
 396         select SYS_FSL_ERRATUM_A009942
 397         select SYS_FSL_HAS_DDR3
 398         select SYS_FSL_HAS_SEC
 399         select SYS_FSL_QORIQ_CHASSIS2
 400         select SYS_FSL_SEC_BE
 401         select SYS_FSL_SEC_COMPAT_4
 402         select SYS_PPC64
 403         select FSL_IFC
 404
 405 config ARCH_BSC9131
 406         bool
 407         select FSL_LAW
 408         select SYS_FSL_DDR_VER_44
 409         select SYS_FSL_ERRATUM_A004477
 410         select SYS_FSL_ERRATUM_A005125
 411         select SYS_FSL_ERRATUM_ESDHC111
 412         select SYS_FSL_HAS_DDR3
 413         select SYS_FSL_HAS_SEC
 414         select SYS_FSL_SEC_BE
 415         select SYS_FSL_SEC_COMPAT_4
 416         select FSL_IFC
 417
 418 config ARCH_BSC9132
 419         bool
 420         select FSL_LAW
 421         select SYS_FSL_DDR_VER_46
 422         select SYS_FSL_ERRATUM_A004477
 423         select SYS_FSL_ERRATUM_A005125
 424         select SYS_FSL_ERRATUM_A005434
 425         select SYS_FSL_ERRATUM_ESDHC111
 426         select SYS_FSL_ERRATUM_I2C_A004447
 427         select SYS_FSL_ERRATUM_IFC_A002769
 428         select SYS_FSL_HAS_DDR3
 429         select SYS_FSL_HAS_SEC
 430         select SYS_FSL_SEC_BE
 431         select SYS_FSL_SEC_COMPAT_4
 432         select SYS_PPC_E500_USE_DEBUG_TLB
 433         select FSL_IFC
 434
 435 config ARCH_C29X
 436         bool
 437         select FSL_LAW
 438         select SYS_FSL_DDR_VER_46
 439         select SYS_FSL_ERRATUM_A005125
 440         select SYS_FSL_ERRATUM_ESDHC111
 441         select SYS_FSL_HAS_DDR3
 442         select SYS_FSL_HAS_SEC
 443         select SYS_FSL_SEC_BE
 444         select SYS_FSL_SEC_COMPAT_6
 445         select SYS_PPC_E500_USE_DEBUG_TLB
 446         select FSL_IFC
 447
 448 config ARCH_MPC8536
 449         bool
 450         select FSL_LAW
 451         select SYS_FSL_ERRATUM_A004508
 452         select SYS_FSL_ERRATUM_A005125
 453         select SYS_FSL_HAS_DDR2
 454         select SYS_FSL_HAS_DDR3
 455         select SYS_FSL_HAS_SEC
 456         select SYS_FSL_SEC_BE
 457         select SYS_FSL_SEC_COMPAT_2
 458         select SYS_PPC_E500_USE_DEBUG_TLB
 459         select FSL_ELBC
 460
 461 config ARCH_MPC8540
 462         bool
 463         select FSL_LAW
 464         select SYS_FSL_HAS_DDR1
 465
 466 config ARCH_MPC8541
 467         bool
 468         select FSL_LAW
 469         select SYS_FSL_HAS_DDR1
 470         select SYS_FSL_HAS_SEC
 471         select SYS_FSL_SEC_BE
 472         select SYS_FSL_SEC_COMPAT_2
 473
 474 config ARCH_MPC8544
 475         bool
 476         select FSL_LAW
 477         select SYS_FSL_ERRATUM_A005125
 478         select SYS_FSL_HAS_DDR2
 479         select SYS_FSL_HAS_SEC
 480         select SYS_FSL_SEC_BE
 481         select SYS_FSL_SEC_COMPAT_2
 482         select SYS_PPC_E500_USE_DEBUG_TLB
 483         select FSL_ELBC
 484
 485 config ARCH_MPC8548
 486         bool
 487         select FSL_LAW
 488         select SYS_FSL_ERRATUM_A005125
 489         select SYS_FSL_ERRATUM_NMG_DDR120
 490         select SYS_FSL_ERRATUM_NMG_LBC103
 491         select SYS_FSL_ERRATUM_NMG_ETSEC129
 492         select SYS_FSL_ERRATUM_I2C_A004447
 493         select SYS_FSL_HAS_DDR2
 494         select SYS_FSL_HAS_DDR1
 495         select SYS_FSL_HAS_SEC
 496         select SYS_FSL_SEC_BE
 497         select SYS_FSL_SEC_COMPAT_2
 498         select SYS_PPC_E500_USE_DEBUG_TLB
 499
 500 config ARCH_MPC8555
 501         bool
 502         select FSL_LAW
 503         select SYS_FSL_HAS_DDR1
 504         select SYS_FSL_HAS_SEC
 505         select SYS_FSL_SEC_BE
 506         select SYS_FSL_SEC_COMPAT_2
 507
 508 config ARCH_MPC8560
 509         bool
 510         select FSL_LAW
 511         select SYS_FSL_HAS_DDR1
 512
 513 config ARCH_MPC8568
 514         bool
 515         select FSL_LAW
 516         select SYS_FSL_HAS_DDR2
 517         select SYS_FSL_HAS_SEC
 518         select SYS_FSL_SEC_BE
 519         select SYS_FSL_SEC_COMPAT_2
 520
 521 config ARCH_MPC8569
 522         bool
 523         select FSL_LAW
 524         select SYS_FSL_ERRATUM_A004508
 525         select SYS_FSL_ERRATUM_A005125
 526         select SYS_FSL_HAS_DDR3
 527         select SYS_FSL_HAS_SEC
 528         select SYS_FSL_SEC_BE
 529         select SYS_FSL_SEC_COMPAT_2
 530         select FSL_ELBC
 531
 532 config ARCH_MPC8572
 533         bool
 534         select FSL_LAW
 535         select SYS_FSL_ERRATUM_A004508
 536         select SYS_FSL_ERRATUM_A005125
 537         select SYS_FSL_ERRATUM_DDR_115
 538         select SYS_FSL_ERRATUM_DDR111_DDR134
 539         select SYS_FSL_HAS_DDR2
 540         select SYS_FSL_HAS_DDR3
 541         select SYS_FSL_HAS_SEC
 542         select SYS_FSL_SEC_BE
 543         select SYS_FSL_SEC_COMPAT_2
 544         select SYS_PPC_E500_USE_DEBUG_TLB
 545         select FSL_ELBC
 546
 547 config ARCH_P1010
 548         bool
 549         select FSL_LAW
 550         select SYS_FSL_ERRATUM_A004477
 551         select SYS_FSL_ERRATUM_A004508
 552         select SYS_FSL_ERRATUM_A005125
 553         select SYS_FSL_ERRATUM_A006261
 554         select SYS_FSL_ERRATUM_A007075
 555         select SYS_FSL_ERRATUM_ESDHC111
 556         select SYS_FSL_ERRATUM_I2C_A004447
 557         select SYS_FSL_ERRATUM_IFC_A002769
 558         select SYS_FSL_ERRATUM_P1010_A003549
 559         select SYS_FSL_ERRATUM_SEC_A003571
 560         select SYS_FSL_ERRATUM_IFC_A003399
 561         select SYS_FSL_HAS_DDR3
 562         select SYS_FSL_HAS_SEC
 563         select SYS_FSL_SEC_BE
 564         select SYS_FSL_SEC_COMPAT_4
 565         select SYS_PPC_E500_USE_DEBUG_TLB
 566         select FSL_IFC
 567
 568 config ARCH_P1011
 569         bool
 570         select FSL_LAW
 571         select SYS_FSL_ERRATUM_A004508
 572         select SYS_FSL_ERRATUM_A005125
 573         select SYS_FSL_ERRATUM_ELBC_A001
 574         select SYS_FSL_ERRATUM_ESDHC111
 575         select SYS_FSL_HAS_DDR3
 576         select SYS_FSL_HAS_SEC
 577         select SYS_FSL_SEC_BE
 578         select SYS_FSL_SEC_COMPAT_2
 579         select SYS_PPC_E500_USE_DEBUG_TLB
 580         select FSL_ELBC
 581
 582 config ARCH_P1020
 583         bool
 584         select FSL_LAW
 585         select SYS_FSL_ERRATUM_A004508
 586         select SYS_FSL_ERRATUM_A005125
 587         select SYS_FSL_ERRATUM_ELBC_A001
 588         select SYS_FSL_ERRATUM_ESDHC111
 589         select SYS_FSL_HAS_DDR3
 590         select SYS_FSL_HAS_SEC
 591         select SYS_FSL_SEC_BE
 592         select SYS_FSL_SEC_COMPAT_2
 593         select SYS_PPC_E500_USE_DEBUG_TLB
 594         select FSL_ELBC
 595
 596 config ARCH_P1021
 597         bool
 598         select FSL_LAW
 599         select SYS_FSL_ERRATUM_A004508
 600         select SYS_FSL_ERRATUM_A005125
 601         select SYS_FSL_ERRATUM_ELBC_A001
 602         select SYS_FSL_ERRATUM_ESDHC111
 603         select SYS_FSL_HAS_DDR3
 604         select SYS_FSL_HAS_SEC
 605         select SYS_FSL_SEC_BE
 606         select SYS_FSL_SEC_COMPAT_2
 607         select SYS_PPC_E500_USE_DEBUG_TLB
 608         select FSL_ELBC
 609
 610 config ARCH_P1022
 611         bool
 612         select FSL_LAW
 613         select SYS_FSL_ERRATUM_A004477
 614         select SYS_FSL_ERRATUM_A004508
 615         select SYS_FSL_ERRATUM_A005125
 616         select SYS_FSL_ERRATUM_ELBC_A001
 617         select SYS_FSL_ERRATUM_ESDHC111
 618         select SYS_FSL_ERRATUM_SATA_A001
 619         select SYS_FSL_HAS_DDR3
 620         select SYS_FSL_HAS_SEC
 621         select SYS_FSL_SEC_BE
 622         select SYS_FSL_SEC_COMPAT_2
 623         select SYS_PPC_E500_USE_DEBUG_TLB
 624         select FSL_ELBC
 625
 626 config ARCH_P1023
 627         bool
 628         select FSL_LAW
 629         select SYS_FSL_ERRATUM_A004508
 630         select SYS_FSL_ERRATUM_A005125
 631         select SYS_FSL_ERRATUM_I2C_A004447
 632         select SYS_FSL_HAS_DDR3
 633         select SYS_FSL_HAS_SEC
 634         select SYS_FSL_SEC_BE
 635         select SYS_FSL_SEC_COMPAT_4
 636         select FSL_ELBC
 637
 638 config ARCH_P1024
 639         bool
 640         select FSL_LAW
 641         select SYS_FSL_ERRATUM_A004508
 642         select SYS_FSL_ERRATUM_A005125
 643         select SYS_FSL_ERRATUM_ELBC_A001
 644         select SYS_FSL_ERRATUM_ESDHC111
 645         select SYS_FSL_HAS_DDR3
 646         select SYS_FSL_HAS_SEC
 647         select SYS_FSL_SEC_BE
 648         select SYS_FSL_SEC_COMPAT_2
 649         select SYS_PPC_E500_USE_DEBUG_TLB
 650         select FSL_ELBC
 651
 652 config ARCH_P1025
 653         bool
 654         select FSL_LAW
 655         select SYS_FSL_ERRATUM_A004508
 656         select SYS_FSL_ERRATUM_A005125
 657         select SYS_FSL_ERRATUM_ELBC_A001
 658         select SYS_FSL_ERRATUM_ESDHC111
 659         select SYS_FSL_HAS_DDR3
 660         select SYS_FSL_HAS_SEC
 661         select SYS_FSL_SEC_BE
 662         select SYS_FSL_SEC_COMPAT_2
 663         select SYS_PPC_E500_USE_DEBUG_TLB
 664         select FSL_ELBC
 665
 666 config ARCH_P2020
 667         bool
 668         select FSL_LAW
 669         select SYS_FSL_ERRATUM_A004477
 670         select SYS_FSL_ERRATUM_A004508
 671         select SYS_FSL_ERRATUM_A005125
 672         select SYS_FSL_ERRATUM_ESDHC111
 673         select SYS_FSL_ERRATUM_ESDHC_A001
 674         select SYS_FSL_HAS_DDR3
 675         select SYS_FSL_HAS_SEC
 676         select SYS_FSL_SEC_BE
 677         select SYS_FSL_SEC_COMPAT_2
 678         select SYS_PPC_E500_USE_DEBUG_TLB
 679         select FSL_ELBC
 680
 681 config ARCH_P2041
 682         bool
 683         select E500MC
 684         select FSL_LAW
 685         select SYS_FSL_ERRATUM_A004510
 686         select SYS_FSL_ERRATUM_A004849
 687         select SYS_FSL_ERRATUM_A006261
 688         select SYS_FSL_ERRATUM_CPU_A003999
 689         select SYS_FSL_ERRATUM_DDR_A003
 690         select SYS_FSL_ERRATUM_DDR_A003474
 691         select SYS_FSL_ERRATUM_ESDHC111
 692         select SYS_FSL_ERRATUM_I2C_A004447
 693         select SYS_FSL_ERRATUM_NMG_CPU_A011
 694         select SYS_FSL_ERRATUM_SRIO_A004034
 695         select SYS_FSL_ERRATUM_USB14
 696         select SYS_FSL_HAS_DDR3
 697         select SYS_FSL_HAS_SEC
 698         select SYS_FSL_QORIQ_CHASSIS1
 699         select SYS_FSL_SEC_BE
 700         select SYS_FSL_SEC_COMPAT_4
 701         select FSL_ELBC
 702
 703 config ARCH_P3041
 704         bool
 705         select E500MC
 706         select FSL_LAW
 707         select SYS_FSL_DDR_VER_44
 708         select SYS_FSL_ERRATUM_A004510
 709         select SYS_FSL_ERRATUM_A004849
 710         select SYS_FSL_ERRATUM_A005812
 711         select SYS_FSL_ERRATUM_A006261
 712         select SYS_FSL_ERRATUM_CPU_A003999
 713         select SYS_FSL_ERRATUM_DDR_A003
 714         select SYS_FSL_ERRATUM_DDR_A003474
 715         select SYS_FSL_ERRATUM_ESDHC111
 716         select SYS_FSL_ERRATUM_I2C_A004447
 717         select SYS_FSL_ERRATUM_NMG_CPU_A011
 718         select SYS_FSL_ERRATUM_SRIO_A004034
 719         select SYS_FSL_ERRATUM_USB14
 720         select SYS_FSL_HAS_DDR3
 721         select SYS_FSL_HAS_SEC
 722         select SYS_FSL_QORIQ_CHASSIS1
 723         select SYS_FSL_SEC_BE
 724         select SYS_FSL_SEC_COMPAT_4
 725         select FSL_ELBC
 726
 727 config ARCH_P4080
 728         bool
 729         select E500MC
 730         select FSL_LAW
 731         select SYS_FSL_DDR_VER_44
 732         select SYS_FSL_ERRATUM_A004510
 733         select SYS_FSL_ERRATUM_A004580
 734         select SYS_FSL_ERRATUM_A004849
 735         select SYS_FSL_ERRATUM_A005812
 736         select SYS_FSL_ERRATUM_A007075
 737         select SYS_FSL_ERRATUM_CPC_A002
 738         select SYS_FSL_ERRATUM_CPC_A003
 739         select SYS_FSL_ERRATUM_CPU_A003999
 740         select SYS_FSL_ERRATUM_DDR_A003
 741         select SYS_FSL_ERRATUM_DDR_A003474
 742         select SYS_FSL_ERRATUM_ELBC_A001
 743         select SYS_FSL_ERRATUM_ESDHC111
 744         select SYS_FSL_ERRATUM_ESDHC13
 745         select SYS_FSL_ERRATUM_ESDHC135
 746         select SYS_FSL_ERRATUM_I2C_A004447
 747         select SYS_FSL_ERRATUM_NMG_CPU_A011
 748         select SYS_FSL_ERRATUM_SRIO_A004034
 749         select SYS_P4080_ERRATUM_CPU22
 750         select SYS_P4080_ERRATUM_PCIE_A003
 751         select SYS_P4080_ERRATUM_SERDES8
 752         select SYS_P4080_ERRATUM_SERDES9
 753         select SYS_P4080_ERRATUM_SERDES_A001
 754         select SYS_P4080_ERRATUM_SERDES_A005
 755         select SYS_FSL_HAS_DDR3
 756         select SYS_FSL_HAS_SEC
 757         select SYS_FSL_QORIQ_CHASSIS1
 758         select SYS_FSL_SEC_BE
 759         select SYS_FSL_SEC_COMPAT_4
 760         select FSL_ELBC
 761
 762 config ARCH_P5020
 763         bool
 764         select E500MC
 765         select FSL_LAW
 766         select SYS_FSL_DDR_VER_44
 767         select SYS_FSL_ERRATUM_A004510
 768         select SYS_FSL_ERRATUM_A006261
 769         select SYS_FSL_ERRATUM_DDR_A003
 770         select SYS_FSL_ERRATUM_DDR_A003474
 771         select SYS_FSL_ERRATUM_ESDHC111
 772         select SYS_FSL_ERRATUM_I2C_A004447
 773         select SYS_FSL_ERRATUM_SRIO_A004034
 774         select SYS_FSL_ERRATUM_USB14
 775         select SYS_FSL_HAS_DDR3
 776         select SYS_FSL_HAS_SEC
 777         select SYS_FSL_QORIQ_CHASSIS1
 778         select SYS_FSL_SEC_BE
 779         select SYS_FSL_SEC_COMPAT_4
 780         select SYS_PPC64
 781         select FSL_ELBC
 782
 783 config ARCH_P5040
 784         bool
 785         select E500MC
 786         select FSL_LAW
 787         select SYS_FSL_DDR_VER_44
 788         select SYS_FSL_ERRATUM_A004510
 789         select SYS_FSL_ERRATUM_A004699
 790         select SYS_FSL_ERRATUM_A005812
 791         select SYS_FSL_ERRATUM_A006261
 792         select SYS_FSL_ERRATUM_DDR_A003
 793         select SYS_FSL_ERRATUM_DDR_A003474
 794         select SYS_FSL_ERRATUM_ESDHC111
 795         select SYS_FSL_ERRATUM_USB14
 796         select SYS_FSL_HAS_DDR3
 797         select SYS_FSL_HAS_SEC
 798         select SYS_FSL_QORIQ_CHASSIS1
 799         select SYS_FSL_SEC_BE
 800         select SYS_FSL_SEC_COMPAT_4
 801         select SYS_PPC64
 802         select FSL_ELBC
 803
 804 config ARCH_QEMU_E500
 805         bool
 806
 807 config ARCH_T1023
 808         bool
 809         select E500MC
 810         select FSL_LAW
 811         select SYS_FSL_DDR_VER_50
 812         select SYS_FSL_ERRATUM_A008378
 813         select SYS_FSL_ERRATUM_A009663
 814         select SYS_FSL_ERRATUM_A009942
 815         select SYS_FSL_ERRATUM_ESDHC111
 816         select SYS_FSL_HAS_DDR3
 817         select SYS_FSL_HAS_DDR4
 818         select SYS_FSL_HAS_SEC
 819         select SYS_FSL_QORIQ_CHASSIS2
 820         select SYS_FSL_SEC_BE
 821         select SYS_FSL_SEC_COMPAT_5
 822         select FSL_IFC
 823
 824 config ARCH_T1024
 825         bool
 826         select E500MC
 827         select FSL_LAW
 828         select SYS_FSL_DDR_VER_50
 829         select SYS_FSL_ERRATUM_A008378
 830         select SYS_FSL_ERRATUM_A009663
 831         select SYS_FSL_ERRATUM_A009942
 832         select SYS_FSL_ERRATUM_ESDHC111
 833         select SYS_FSL_HAS_DDR3
 834         select SYS_FSL_HAS_DDR4
 835         select SYS_FSL_HAS_SEC
 836         select SYS_FSL_QORIQ_CHASSIS2
 837         select SYS_FSL_SEC_BE
 838         select SYS_FSL_SEC_COMPAT_5
 839         select FSL_IFC
 840
 841 config ARCH_T1040
 842         bool
 843         select E500MC
 844         select FSL_LAW
 845         select SYS_FSL_DDR_VER_50
 846         select SYS_FSL_ERRATUM_A008044
 847         select SYS_FSL_ERRATUM_A008378
 848         select SYS_FSL_ERRATUM_A009663
 849         select SYS_FSL_ERRATUM_A009942
 850         select SYS_FSL_ERRATUM_ESDHC111
 851         select SYS_FSL_HAS_DDR3
 852         select SYS_FSL_HAS_DDR4
 853         select SYS_FSL_HAS_SEC
 854         select SYS_FSL_QORIQ_CHASSIS2
 855         select SYS_FSL_SEC_BE
 856         select SYS_FSL_SEC_COMPAT_5
 857         select FSL_IFC
 858
 859 config ARCH_T1042
 860         bool
 861         select E500MC
 862         select FSL_LAW
 863         select SYS_FSL_DDR_VER_50
 864         select SYS_FSL_ERRATUM_A008044
 865         select SYS_FSL_ERRATUM_A008378
 866         select SYS_FSL_ERRATUM_A009663
 867         select SYS_FSL_ERRATUM_A009942
 868         select SYS_FSL_ERRATUM_ESDHC111
 869         select SYS_FSL_HAS_DDR3
 870         select SYS_FSL_HAS_DDR4
 871         select SYS_FSL_HAS_SEC
 872         select SYS_FSL_QORIQ_CHASSIS2
 873         select SYS_FSL_SEC_BE
 874         select SYS_FSL_SEC_COMPAT_5
 875         select FSL_IFC
 876
 877 config ARCH_T2080
 878         bool
 879         select E500MC
 880         select E6500
 881         select FSL_LAW
 882         select SYS_FSL_DDR_VER_47
 883         select SYS_FSL_ERRATUM_A006379
 884         select SYS_FSL_ERRATUM_A006593
 885         select SYS_FSL_ERRATUM_A007186
 886         select SYS_FSL_ERRATUM_A007212
 887         select SYS_FSL_ERRATUM_A007815
 888         select SYS_FSL_ERRATUM_A007907
 889         select SYS_FSL_ERRATUM_A009942
 890         select SYS_FSL_ERRATUM_ESDHC111
 891         select SYS_FSL_HAS_DDR3
 892         select SYS_FSL_HAS_SEC
 893         select SYS_FSL_QORIQ_CHASSIS2
 894         select SYS_FSL_SEC_BE
 895         select SYS_FSL_SEC_COMPAT_4
 896         select SYS_PPC64
 897         select FSL_IFC
 898
 899 config ARCH_T2081
 900         bool
 901         select E500MC
 902         select E6500
 903         select FSL_LAW
 904         select SYS_FSL_DDR_VER_47
 905         select SYS_FSL_ERRATUM_A006379
 906         select SYS_FSL_ERRATUM_A006593
 907         select SYS_FSL_ERRATUM_A007186
 908         select SYS_FSL_ERRATUM_A007212
 909         select SYS_FSL_ERRATUM_A009942
 910         select SYS_FSL_ERRATUM_ESDHC111
 911         select SYS_FSL_HAS_DDR3
 912         select SYS_FSL_HAS_SEC
 913         select SYS_FSL_QORIQ_CHASSIS2
 914         select SYS_FSL_SEC_BE
 915         select SYS_FSL_SEC_COMPAT_4
 916         select SYS_PPC64
 917         select FSL_IFC
 918
 919 config ARCH_T4160
 920         bool
 921         select E500MC
 922         select E6500
 923         select FSL_LAW
 924         select SYS_FSL_DDR_VER_47
 925         select SYS_FSL_ERRATUM_A004468
 926         select SYS_FSL_ERRATUM_A005871
 927         select SYS_FSL_ERRATUM_A006379
 928         select SYS_FSL_ERRATUM_A006593
 929         select SYS_FSL_ERRATUM_A007186
 930         select SYS_FSL_ERRATUM_A007798
 931         select SYS_FSL_ERRATUM_A009942
 932         select SYS_FSL_HAS_DDR3
 933         select SYS_FSL_HAS_SEC
 934         select SYS_FSL_QORIQ_CHASSIS2
 935         select SYS_FSL_SEC_BE
 936         select SYS_FSL_SEC_COMPAT_4
 937         select SYS_PPC64
 938         select FSL_IFC
 939
 940 config ARCH_T4240
 941         bool
 942         select E500MC
 943         select E6500
 944         select FSL_LAW
 945         select SYS_FSL_DDR_VER_47
 946         select SYS_FSL_ERRATUM_A004468
 947         select SYS_FSL_ERRATUM_A005871
 948         select SYS_FSL_ERRATUM_A006261
 949         select SYS_FSL_ERRATUM_A006379
 950         select SYS_FSL_ERRATUM_A006593
 951         select SYS_FSL_ERRATUM_A007186
 952         select SYS_FSL_ERRATUM_A007798
 953         select SYS_FSL_ERRATUM_A007815
 954         select SYS_FSL_ERRATUM_A007907
 955         select SYS_FSL_ERRATUM_A009942
 956         select SYS_FSL_HAS_DDR3
 957         select SYS_FSL_HAS_SEC
 958         select SYS_FSL_QORIQ_CHASSIS2
 959         select SYS_FSL_SEC_BE
 960         select SYS_FSL_SEC_COMPAT_4
 961         select SYS_PPC64
 962         select FSL_IFC
 963
 964 config BOOKE
 965         bool
 966         default y
 967
 968 config E500
 969         bool
 970         default y
 971         help
 972                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
 973
 974 config E500MC
 975         bool
 976         help
 977                 Enble PowerPC E500MC core
 978
 979 config E6500
 980         bool
 981         help
 982                 Enable PowerPC E6500 core
 983
 984 config FSL_LAW
 985         bool
 986         help
 987                 Use Freescale common code for Local Access Window
 988
 989 config SECURE_BOOT
 990         bool    "Secure Boot"
 991         help
 992                 Enable Freescale Secure Boot feature. Normally selected
 993                 by defconfig. If unsure, do not change.
 994
 995 config MAX_CPUS
 996         int "Maximum number of CPUs permitted for MPC85xx"
 997         default 12 if ARCH_T4240
 998         default 8 if ARCH_P4080 || \
 999                      ARCH_T4160
1000         default 4 if ARCH_B4860 || \
1001                      ARCH_P2041 || \
1002                      ARCH_P3041 || \
1003                      ARCH_P5040 || \
1004                      ARCH_T1040 || \
1005                      ARCH_T1042 || \
1006                      ARCH_T2080 || \
1007                      ARCH_T2081
1008         default 2 if ARCH_B4420 || \
1009                      ARCH_BSC9132 || \
1010                      ARCH_MPC8572 || \
1011                      ARCH_P1020 || \
1012                      ARCH_P1021 || \
1013                      ARCH_P1022 || \
1014                      ARCH_P1023 || \
1015                      ARCH_P1024 || \
1016                      ARCH_P1025 || \
1017                      ARCH_P2020 || \
1018                      ARCH_P5020 || \
1019                      ARCH_T1023 || \
1020                      ARCH_T1024
1021         default 1
1022         help
1023           Set this number to the maximum number of possible CPUs in the SoC.
1024           SoCs may have multiple clusters with each cluster may have multiple
1025           ports. If some ports are reserved but higher ports are used for
1026           cores, count the reserved ports. This will allocate enough memory
1027           in spin table to properly handle all cores.
1028
1029 config SYS_CCSRBAR_DEFAULT
1030         hex "Default CCSRBAR address"
1031         default 0xff700000 if   ARCH_BSC9131    || \
1032                                 ARCH_BSC9132    || \
1033                                 ARCH_C29X       || \
1034                                 ARCH_MPC8536    || \
1035                                 ARCH_MPC8540    || \
1036                                 ARCH_MPC8541    || \
1037                                 ARCH_MPC8544    || \
1038                                 ARCH_MPC8548    || \
1039                                 ARCH_MPC8555    || \
1040                                 ARCH_MPC8560    || \
1041                                 ARCH_MPC8568    || \
1042                                 ARCH_MPC8569    || \
1043                                 ARCH_MPC8572    || \
1044                                 ARCH_P1010      || \
1045                                 ARCH_P1011      || \
1046                                 ARCH_P1020      || \
1047                                 ARCH_P1021      || \
1048                                 ARCH_P1022      || \
1049                                 ARCH_P1024      || \
1050                                 ARCH_P1025      || \
1051                                 ARCH_P2020
1052         default 0xff600000 if   ARCH_P1023
1053         default 0xfe000000 if   ARCH_B4420      || \
1054                                 ARCH_B4860      || \
1055                                 ARCH_P2041      || \
1056                                 ARCH_P3041      || \
1057                                 ARCH_P4080      || \
1058                                 ARCH_P5020      || \
1059                                 ARCH_P5040      || \
1060                                 ARCH_T1023      || \
1061                                 ARCH_T1024      || \
1062                                 ARCH_T1040      || \
1063                                 ARCH_T1042      || \
1064                                 ARCH_T2080      || \
1065                                 ARCH_T2081      || \
1066                                 ARCH_T4160      || \
1067                                 ARCH_T4240
1068         default 0xe0000000 if ARCH_QEMU_E500
1069         help
1070                 Default value of CCSRBAR comes from power-on-reset. It
1071                 is fixed on each SoC. Some SoCs can have different value
1072                 if changed by pre-boot regime. The value here must match
1073                 the current value in SoC. If not sure, do not change.
1074
1075 config SYS_FSL_ERRATUM_A004468
1076         bool
1077
1078 config SYS_FSL_ERRATUM_A004477
1079         bool
1080
1081 config SYS_FSL_ERRATUM_A004508
1082         bool
1083
1084 config SYS_FSL_ERRATUM_A004580
1085         bool
1086
1087 config SYS_FSL_ERRATUM_A004699
1088         bool
1089
1090 config SYS_FSL_ERRATUM_A004849
1091         bool
1092
1093 config SYS_FSL_ERRATUM_A004510
1094         bool
1095
1096 config SYS_FSL_ERRATUM_A004510_SVR_REV
1097         hex
1098         depends on SYS_FSL_ERRATUM_A004510
1099         default 0x20 if ARCH_P4080
1100         default 0x10
1101
1102 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1103         hex
1104         depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1105         default 0x11
1106
1107 config SYS_FSL_ERRATUM_A005125
1108         bool
1109
1110 config SYS_FSL_ERRATUM_A005434
1111         bool
1112
1113 config SYS_FSL_ERRATUM_A005812
1114         bool
1115
1116 config SYS_FSL_ERRATUM_A005871
1117         bool
1118
1119 config SYS_FSL_ERRATUM_A006261
1120         bool
1121
1122 config SYS_FSL_ERRATUM_A006379
1123         bool
1124
1125 config SYS_FSL_ERRATUM_A006384
1126         bool
1127
1128 config SYS_FSL_ERRATUM_A006475
1129         bool
1130
1131 config SYS_FSL_ERRATUM_A006593
1132         bool
1133
1134 config SYS_FSL_ERRATUM_A007075
1135         bool
1136
1137 config SYS_FSL_ERRATUM_A007186
1138         bool
1139
1140 config SYS_FSL_ERRATUM_A007212
1141         bool
1142
1143 config SYS_FSL_ERRATUM_A007815
1144         bool
1145
1146 config SYS_FSL_ERRATUM_A007798
1147         bool
1148
1149 config SYS_FSL_ERRATUM_A007907
1150         bool
1151
1152 config SYS_FSL_ERRATUM_A008044
1153         bool
1154
1155 config SYS_FSL_ERRATUM_CPC_A002
1156         bool
1157
1158 config SYS_FSL_ERRATUM_CPC_A003
1159         bool
1160
1161 config SYS_FSL_ERRATUM_CPU_A003999
1162         bool
1163
1164 config SYS_FSL_ERRATUM_ELBC_A001
1165         bool
1166
1167 config SYS_FSL_ERRATUM_I2C_A004447
1168         bool
1169
1170 config SYS_FSL_A004447_SVR_REV
1171         hex
1172         depends on SYS_FSL_ERRATUM_I2C_A004447
1173         default 0x00 if ARCH_MPC8548
1174         default 0x10 if ARCH_P1010
1175         default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1176         default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1177
1178 config SYS_FSL_ERRATUM_IFC_A002769
1179         bool
1180
1181 config SYS_FSL_ERRATUM_IFC_A003399
1182         bool
1183
1184 config SYS_FSL_ERRATUM_NMG_CPU_A011
1185         bool
1186
1187 config SYS_FSL_ERRATUM_NMG_ETSEC129
1188         bool
1189
1190 config SYS_FSL_ERRATUM_NMG_LBC103
1191         bool
1192
1193 config SYS_FSL_ERRATUM_P1010_A003549
1194         bool
1195
1196 config SYS_FSL_ERRATUM_SATA_A001
1197         bool
1198
1199 config SYS_FSL_ERRATUM_SEC_A003571
1200         bool
1201
1202 config SYS_FSL_ERRATUM_SRIO_A004034
1203         bool
1204
1205 config SYS_FSL_ERRATUM_USB14
1206         bool
1207
1208 config SYS_P4080_ERRATUM_CPU22
1209         bool
1210
1211 config SYS_P4080_ERRATUM_PCIE_A003
1212         bool
1213
1214 config SYS_P4080_ERRATUM_SERDES8
1215         bool
1216
1217 config SYS_P4080_ERRATUM_SERDES9
1218         bool
1219
1220 config SYS_P4080_ERRATUM_SERDES_A001
1221         bool
1222
1223 config SYS_P4080_ERRATUM_SERDES_A005
1224         bool
1225
1226 config SYS_FSL_QORIQ_CHASSIS1
1227         bool
1228
1229 config SYS_FSL_QORIQ_CHASSIS2
1230         bool
1231
1232 config SYS_FSL_NUM_LAWS
1233         int "Number of local access windows"
1234         depends on FSL_LAW
1235         default 32 if   ARCH_B4420      || \
1236                         ARCH_B4860      || \
1237                         ARCH_P2041      || \
1238                         ARCH_P3041      || \
1239                         ARCH_P4080      || \
1240                         ARCH_P5020      || \
1241                         ARCH_P5040      || \
1242                         ARCH_T2080      || \
1243                         ARCH_T2081      || \
1244                         ARCH_T4160      || \
1245                         ARCH_T4240
1246         default 16 if   ARCH_T1023      || \
1247                         ARCH_T1024      || \
1248                         ARCH_T1040      || \
1249                         ARCH_T1042
1250         default 12 if   ARCH_BSC9131    || \
1251                         ARCH_BSC9132    || \
1252                         ARCH_C29X       || \
1253                         ARCH_MPC8536    || \
1254                         ARCH_MPC8572    || \
1255                         ARCH_P1010      || \
1256                         ARCH_P1011      || \
1257                         ARCH_P1020      || \
1258                         ARCH_P1021      || \
1259                         ARCH_P1022      || \
1260                         ARCH_P1023      || \
1261                         ARCH_P1024      || \
1262                         ARCH_P1025      || \
1263                         ARCH_P2020
1264         default 10 if   ARCH_MPC8544    || \
1265                         ARCH_MPC8548    || \
1266                         ARCH_MPC8568    || \
1267                         ARCH_MPC8569
1268         default 8 if    ARCH_MPC8540    || \
1269                         ARCH_MPC8541    || \
1270                         ARCH_MPC8555    || \
1271                         ARCH_MPC8560
1272         help
1273                 Number of local access windows. This is fixed per SoC.
1274                 If not sure, do not change.
1275
1276 config SYS_FSL_THREADS_PER_CORE
1277         int
1278         default 2 if E6500
1279         default 1
1280
1281 config SYS_NUM_TLBCAMS
1282         int "Number of TLB CAM entries"
1283         default 64 if E500MC
1284         default 16
1285         help
1286                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1287                 16 for other E500 SoCs.
1288
1289 config SYS_PPC64
1290         bool
1291
1292 config SYS_PPC_E500_USE_DEBUG_TLB
1293         bool
1294
1295 config FSL_IFC
1296         bool
1297
1298 config FSL_ELBC
1299         bool
1300
1301 config SYS_PPC_E500_DEBUG_TLB
1302         int "Temporary TLB entry for external debugger"
1303         depends on SYS_PPC_E500_USE_DEBUG_TLB
1304         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
1305         default 1 if    ARCH_MPC8536
1306         default 2 if    ARCH_MPC8572    || \
1307                         ARCH_P1011      || \
1308                         ARCH_P1020      || \
1309                         ARCH_P1021      || \
1310                         ARCH_P1022      || \
1311                         ARCH_P1024      || \
1312                         ARCH_P1025      || \
1313                         ARCH_P2020
1314         default 3 if    ARCH_P1010      || \
1315                         ARCH_BSC9132    || \
1316                         ARCH_C29X
1317         help
1318                 Select a temporary TLB entry to be used during boot to work
1319                 around limitations in e500v1 and e500v2 external debugger
1320                 support. This reduces the portions of the boot code where
1321                 breakpoints and single stepping do not work. The value of this
1322                 symbol should be set to the TLB1 entry to be used for this
1323                 purpose. If unsure, do not change.
1324
1325 config SYS_FSL_IFC_CLK_DIV
1326         int "Divider of platform clock"
1327         depends on FSL_IFC
1328         default 2 if    ARCH_B4420      || \
1329                         ARCH_B4860      || \
1330                         ARCH_T1024      || \
1331                         ARCH_T1023      || \
1332                         ARCH_T1040      || \
1333                         ARCH_T1042      || \
1334                         ARCH_T4160      || \
1335                         ARCH_T4240
1336         default 1
1337         help
1338                 Defines divider of platform clock(clock input to
1339                 IFC controller).
1340
1341 config SYS_FSL_LBC_CLK_DIV
1342         int "Divider of platform clock"
1343         depends on FSL_ELBC || ARCH_MPC8540 || \
1344                 ARCH_MPC8548 || ARCH_MPC8541 || \
1345                 ARCH_MPC8555 || ARCH_MPC8560 || \
1346                 ARCH_MPC8568
1347
1348         default 2 if    ARCH_P2041      || \
1349                         ARCH_P3041      || \
1350                         ARCH_P4080      || \
1351                         ARCH_P5020      || \
1352                         ARCH_P5040
1353         default 1
1354
1355         help
1356                 Defines divider of platform clock(clock input to
1357                 eLBC controller).
1358
1359 source "board/freescale/b4860qds/Kconfig"
1360 source "board/freescale/bsc9131rdb/Kconfig"
1361 source "board/freescale/bsc9132qds/Kconfig"
1362 source "board/freescale/c29xpcie/Kconfig"
1363 source "board/freescale/corenet_ds/Kconfig"
1364 source "board/freescale/mpc8536ds/Kconfig"
1365 source "board/freescale/mpc8540ads/Kconfig"
1366 source "board/freescale/mpc8541cds/Kconfig"
1367 source "board/freescale/mpc8544ds/Kconfig"
1368 source "board/freescale/mpc8548cds/Kconfig"
1369 source "board/freescale/mpc8555cds/Kconfig"
1370 source "board/freescale/mpc8560ads/Kconfig"
1371 source "board/freescale/mpc8568mds/Kconfig"
1372 source "board/freescale/mpc8569mds/Kconfig"
1373 source "board/freescale/mpc8572ds/Kconfig"
1374 source "board/freescale/p1010rdb/Kconfig"
1375 source "board/freescale/p1022ds/Kconfig"
1376 source "board/freescale/p1023rdb/Kconfig"
1377 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1378 source "board/freescale/p1_twr/Kconfig"
1379 source "board/freescale/p2041rdb/Kconfig"
1380 source "board/freescale/qemu-ppce500/Kconfig"
1381 source "board/freescale/t102xqds/Kconfig"
1382 source "board/freescale/t102xrdb/Kconfig"
1383 source "board/freescale/t1040qds/Kconfig"
1384 source "board/freescale/t104xrdb/Kconfig"
1385 source "board/freescale/t208xqds/Kconfig"
1386 source "board/freescale/t208xrdb/Kconfig"
1387 source "board/freescale/t4qds/Kconfig"
1388 source "board/freescale/t4rdb/Kconfig"
1389 source "board/gdsys/p1022/Kconfig"
1390 source "board/keymile/kmp204x/Kconfig"
1391 source "board/sbc8548/Kconfig"
1392 source "board/socrates/Kconfig"
1393 source "board/varisys/cyrus/Kconfig"
1394 source "board/xes/xpedite520x/Kconfig"
1395 source "board/xes/xpedite537x/Kconfig"
1396 source "board/xes/xpedite550x/Kconfig"
1397 source "board/Arcturus/ucp1020/Kconfig"
1398
1399 endmenu