drivers/memory/stm32-fmc2-ebi.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) STMicroelectronics 2020
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_NOP
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <reset.h>
  12 #include <dm/device_compat.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/err.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/ioport.h>
  17 #include <linux/time.h>
  18
  19 /* FMC2 Controller Registers */
  20 #define FMC2_BCR1                       0x0
  21 #define FMC2_BTR1                       0x4
  22 #define FMC2_BCR(x)                     ((x) * 0x8 + FMC2_BCR1)
  23 #define FMC2_BTR(x)                     ((x) * 0x8 + FMC2_BTR1)
  24 #define FMC2_PCSCNTR                    0x20
  25 #define FMC2_BWTR1                      0x104
  26 #define FMC2_BWTR(x)                    ((x) * 0x8 + FMC2_BWTR1)
  27
  28 /* Register: FMC2_BCR1 */
  29 #define FMC2_BCR1_CCLKEN                BIT(20)
  30 #define FMC2_BCR1_FMC2EN                BIT(31)
  31
  32 /* Register: FMC2_BCRx */
  33 #define FMC2_BCR_MBKEN                  BIT(0)
  34 #define FMC2_BCR_MUXEN                  BIT(1)
  35 #define FMC2_BCR_MTYP                   GENMASK(3, 2)
  36 #define FMC2_BCR_MWID                   GENMASK(5, 4)
  37 #define FMC2_BCR_FACCEN                 BIT(6)
  38 #define FMC2_BCR_BURSTEN                BIT(8)
  39 #define FMC2_BCR_WAITPOL                BIT(9)
  40 #define FMC2_BCR_WAITCFG                BIT(11)
  41 #define FMC2_BCR_WREN                   BIT(12)
  42 #define FMC2_BCR_WAITEN                 BIT(13)
  43 #define FMC2_BCR_EXTMOD                 BIT(14)
  44 #define FMC2_BCR_ASYNCWAIT              BIT(15)
  45 #define FMC2_BCR_CPSIZE                 GENMASK(18, 16)
  46 #define FMC2_BCR_CBURSTRW               BIT(19)
  47 #define FMC2_BCR_NBLSET                 GENMASK(23, 22)
  48
  49 /* Register: FMC2_BTRx/FMC2_BWTRx */
  50 #define FMC2_BXTR_ADDSET                GENMASK(3, 0)
  51 #define FMC2_BXTR_ADDHLD                GENMASK(7, 4)
  52 #define FMC2_BXTR_DATAST                GENMASK(15, 8)
  53 #define FMC2_BXTR_BUSTURN               GENMASK(19, 16)
  54 #define FMC2_BTR_CLKDIV                 GENMASK(23, 20)
  55 #define FMC2_BTR_DATLAT                 GENMASK(27, 24)
  56 #define FMC2_BXTR_ACCMOD                GENMASK(29, 28)
  57 #define FMC2_BXTR_DATAHLD               GENMASK(31, 30)
  58
  59 /* Register: FMC2_PCSCNTR */
  60 #define FMC2_PCSCNTR_CSCOUNT            GENMASK(15, 0)
  61 #define FMC2_PCSCNTR_CNTBEN(x)          BIT((x) + 16)
  62
  63 #define FMC2_MAX_EBI_CE                 4
  64 #define FMC2_MAX_BANKS                  5
  65
  66 #define FMC2_BCR_CPSIZE_0               0x0
  67 #define FMC2_BCR_CPSIZE_128             0x1
  68 #define FMC2_BCR_CPSIZE_256             0x2
  69 #define FMC2_BCR_CPSIZE_512             0x3
  70 #define FMC2_BCR_CPSIZE_1024            0x4
  71
  72 #define FMC2_BCR_MWID_8                 0x0
  73 #define FMC2_BCR_MWID_16                0x1
  74
  75 #define FMC2_BCR_MTYP_SRAM              0x0
  76 #define FMC2_BCR_MTYP_PSRAM             0x1
  77 #define FMC2_BCR_MTYP_NOR               0x2
  78
  79 #define FMC2_BXTR_EXTMOD_A              0x0
  80 #define FMC2_BXTR_EXTMOD_B              0x1
  81 #define FMC2_BXTR_EXTMOD_C              0x2
  82 #define FMC2_BXTR_EXTMOD_D              0x3
  83
  84 #define FMC2_BCR_NBLSET_MAX             0x3
  85 #define FMC2_BXTR_ADDSET_MAX            0xf
  86 #define FMC2_BXTR_ADDHLD_MAX            0xf
  87 #define FMC2_BXTR_DATAST_MAX            0xff
  88 #define FMC2_BXTR_BUSTURN_MAX           0xf
  89 #define FMC2_BXTR_DATAHLD_MAX           0x3
  90 #define FMC2_BTR_CLKDIV_MAX             0xf
  91 #define FMC2_BTR_DATLAT_MAX             0xf
  92 #define FMC2_PCSCNTR_CSCOUNT_MAX        0xff
  93
  94 enum stm32_fmc2_ebi_bank {
  95         FMC2_EBI1 = 0,
  96         FMC2_EBI2,
  97         FMC2_EBI3,
  98         FMC2_EBI4,
  99         FMC2_NAND
 100 };
 101
 102 enum stm32_fmc2_ebi_register_type {
 103         FMC2_REG_BCR = 1,
 104         FMC2_REG_BTR,
 105         FMC2_REG_BWTR,
 106         FMC2_REG_PCSCNTR
 107 };
 108
 109 enum stm32_fmc2_ebi_transaction_type {
 110         FMC2_ASYNC_MODE_1_SRAM = 0,
 111         FMC2_ASYNC_MODE_1_PSRAM,
 112         FMC2_ASYNC_MODE_A_SRAM,
 113         FMC2_ASYNC_MODE_A_PSRAM,
 114         FMC2_ASYNC_MODE_2_NOR,
 115         FMC2_ASYNC_MODE_B_NOR,
 116         FMC2_ASYNC_MODE_C_NOR,
 117         FMC2_ASYNC_MODE_D_NOR,
 118         FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
 119         FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
 120         FMC2_SYNC_READ_SYNC_WRITE_NOR,
 121         FMC2_SYNC_READ_ASYNC_WRITE_NOR
 122 };
 123
 124 enum stm32_fmc2_ebi_buswidth {
 125         FMC2_BUSWIDTH_8 = 8,
 126         FMC2_BUSWIDTH_16 = 16
 127 };
 128
 129 enum stm32_fmc2_ebi_cpsize {
 130         FMC2_CPSIZE_0 = 0,
 131         FMC2_CPSIZE_128 = 128,
 132         FMC2_CPSIZE_256 = 256,
 133         FMC2_CPSIZE_512 = 512,
 134         FMC2_CPSIZE_1024 = 1024
 135 };
 136
 137 struct stm32_fmc2_ebi {
 138         struct clk clk;
 139         fdt_addr_t io_base;
 140         u8 bank_assigned;
 141 };
 142
 143 /*
 144  * struct stm32_fmc2_prop - STM32 FMC2 EBI property
 145  * @name: the device tree binding name of the property
 146  * @bprop: indicate that it is a boolean property
 147  * @mprop: indicate that it is a mandatory property
 148  * @reg_type: the register that have to be modified
 149  * @reg_mask: the bit that have to be modified in the selected register
 150  *            in case of it is a boolean property
 151  * @reset_val: the default value that have to be set in case the property
 152  *             has not been defined in the device tree
 153  * @check: this callback ckecks that the property is compliant with the
 154  *         transaction type selected
 155  * @calculate: this callback is called to calculate for exemple a timing
 156  *             set in nanoseconds in the device tree in clock cycles or in
 157  *             clock period
 158  * @set: this callback applies the values in the registers
 159  */
 160 struct stm32_fmc2_prop {
 161         const char *name;
 162         bool bprop;
 163         bool mprop;
 164         int reg_type;
 165         u32 reg_mask;
 166         u32 reset_val;
 167         int (*check)(struct stm32_fmc2_ebi *ebi,
 168                      const struct stm32_fmc2_prop *prop, int cs);
 169         u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
 170         int (*set)(struct stm32_fmc2_ebi *ebi,
 171                    const struct stm32_fmc2_prop *prop,
 172                    int cs, u32 setup);
 173 };
 174
 175 static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
 176                                     const struct stm32_fmc2_prop *prop,
 177                                     int cs)
 178 {
 179         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 180
 181         if (bcr & FMC2_BCR_MTYP)
 182                 return 0;
 183
 184         return -EINVAL;
 185 }
 186
 187 static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
 188                                         const struct stm32_fmc2_prop *prop,
 189                                         int cs)
 190 {
 191         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 192         u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 193
 194         if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
 195                 return 0;
 196
 197         return -EINVAL;
 198 }
 199
 200 static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
 201                                            const struct stm32_fmc2_prop *prop,
 202                                            int cs)
 203 {
 204         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 205
 206         if (bcr & FMC2_BCR_BURSTEN)
 207                 return 0;
 208
 209         return -EINVAL;
 210 }
 211
 212 static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
 213                                             const struct stm32_fmc2_prop *prop,
 214                                             int cs)
 215 {
 216         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 217
 218         if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
 219                 return 0;
 220
 221         return -EINVAL;
 222 }
 223
 224 static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
 225                                        const struct stm32_fmc2_prop *prop,
 226                                        int cs)
 227 {
 228         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 229         u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 230
 231         if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
 232                 return 0;
 233
 234         return -EINVAL;
 235 }
 236
 237 static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
 238                                              const struct stm32_fmc2_prop *prop,
 239                                              int cs)
 240 {
 241         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 242         u32 bxtr = prop->reg_type == FMC2_REG_BWTR ?
 243                    readl(ebi->io_base + FMC2_BWTR(cs)) :
 244                    readl(ebi->io_base + FMC2_BTR(cs));
 245         u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 246
 247         if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
 248             ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
 249                 return 0;
 250
 251         return -EINVAL;
 252 }
 253
 254 static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
 255                                            const struct stm32_fmc2_prop *prop,
 256                                            int cs)
 257 {
 258         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 259         u32 bcr1 = cs ? readl(ebi->io_base + FMC2_BCR1) : bcr;
 260
 261         if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
 262                 return 0;
 263
 264         return -EINVAL;
 265 }
 266
 267 static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
 268                                      const struct stm32_fmc2_prop *prop,
 269                                      int cs)
 270 {
 271         if (cs)
 272                 return -EINVAL;
 273
 274         return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
 275 }
 276
 277 static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
 278                                              int cs, u32 setup)
 279 {
 280         unsigned long hclk = clk_get_rate(&ebi->clk);
 281         unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
 282
 283         return DIV_ROUND_UP(setup * 1000, hclkp);
 284 }
 285
 286 static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
 287                                            int cs, u32 setup)
 288 {
 289         u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
 290         u32 bcr = readl(ebi->io_base + FMC2_BCR1);
 291         u32 btr = bcr & FMC2_BCR1_CCLKEN || !cs ?
 292                   readl(ebi->io_base + FMC2_BTR1) :
 293                   readl(ebi->io_base + FMC2_BTR(cs));
 294         u32 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
 295
 296         return DIV_ROUND_UP(nb_clk_cycles, clk_period);
 297 }
 298
 299 static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
 300 {
 301         switch (reg_type) {
 302         case FMC2_REG_BCR:
 303                 *reg = FMC2_BCR(cs);
 304                 break;
 305         case FMC2_REG_BTR:
 306                 *reg = FMC2_BTR(cs);
 307                 break;
 308         case FMC2_REG_BWTR:
 309                 *reg = FMC2_BWTR(cs);
 310                 break;
 311         case FMC2_REG_PCSCNTR:
 312                 *reg = FMC2_PCSCNTR;
 313                 break;
 314         default:
 315                 return -EINVAL;
 316         }
 317
 318         return 0;
 319 }
 320
 321 static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
 322                                         const struct stm32_fmc2_prop *prop,
 323                                         int cs, u32 setup)
 324 {
 325         u32 reg;
 326         int ret;
 327
 328         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 329         if (ret)
 330                 return ret;
 331
 332         clrsetbits_le32(ebi->io_base + reg, prop->reg_mask,
 333                         setup ? prop->reg_mask : 0);
 334
 335         return 0;
 336 }
 337
 338 static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
 339                                          const struct stm32_fmc2_prop *prop,
 340                                          int cs, u32 setup)
 341 {
 342         u32 bcr_mask, bcr = FMC2_BCR_WREN;
 343         u32 btr_mask, btr = 0;
 344         u32 bwtr_mask, bwtr = 0;
 345
 346         bwtr_mask = FMC2_BXTR_ACCMOD;
 347         btr_mask = FMC2_BXTR_ACCMOD;
 348         bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
 349                    FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
 350                    FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
 351
 352         switch (setup) {
 353         case FMC2_ASYNC_MODE_1_SRAM:
 354                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
 355                 /*
 356                  * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 357                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 358                  */
 359                 break;
 360         case FMC2_ASYNC_MODE_1_PSRAM:
 361                 /*
 362                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 363                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 364                  */
 365                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 366                 break;
 367         case FMC2_ASYNC_MODE_A_SRAM:
 368                 /*
 369                  * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 370                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
 371                  */
 372                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
 373                 bcr |= FMC2_BCR_EXTMOD;
 374                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 375                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 376                 break;
 377         case FMC2_ASYNC_MODE_A_PSRAM:
 378                 /*
 379                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 380                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
 381                  */
 382                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 383                 bcr |= FMC2_BCR_EXTMOD;
 384                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 385                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 386                 break;
 387         case FMC2_ASYNC_MODE_2_NOR:
 388                 /*
 389                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 390                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 391                  */
 392                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 393                 bcr |= FMC2_BCR_FACCEN;
 394                 break;
 395         case FMC2_ASYNC_MODE_B_NOR:
 396                 /*
 397                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 398                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
 399                  */
 400                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 401                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 402                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
 403                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
 404                 break;
 405         case FMC2_ASYNC_MODE_C_NOR:
 406                 /*
 407                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 408                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
 409                  */
 410                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 411                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 412                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
 413                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
 414                 break;
 415         case FMC2_ASYNC_MODE_D_NOR:
 416                 /*
 417                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 418                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
 419                  */
 420                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 421                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 422                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 423                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 424                 break;
 425         case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
 426                 /*
 427                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
 428                  * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
 429                  */
 430                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 431                 bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
 432                 break;
 433         case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
 434                 /*
 435                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
 436                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 437                  */
 438                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 439                 bcr |= FMC2_BCR_BURSTEN;
 440                 break;
 441         case FMC2_SYNC_READ_SYNC_WRITE_NOR:
 442                 /*
 443                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
 444                  * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
 445                  */
 446                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 447                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
 448                 break;
 449         case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
 450                 /*
 451                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
 452                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 453                  */
 454                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 455                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
 456                 break;
 457         default:
 458                 /* Type of transaction not supported */
 459                 return -EINVAL;
 460         }
 461
 462         if (bcr & FMC2_BCR_EXTMOD)
 463                 clrsetbits_le32(ebi->io_base + FMC2_BWTR(cs),
 464                                 bwtr_mask, bwtr);
 465         clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), btr_mask, btr);
 466         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), bcr_mask, bcr);
 467
 468         return 0;
 469 }
 470
 471 static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
 472                                        const struct stm32_fmc2_prop *prop,
 473                                        int cs, u32 setup)
 474 {
 475         u32 val;
 476
 477         switch (setup) {
 478         case FMC2_BUSWIDTH_8:
 479                 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
 480                 break;
 481         case FMC2_BUSWIDTH_16:
 482                 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
 483                 break;
 484         default:
 485                 /* Buswidth not supported */
 486                 return -EINVAL;
 487         }
 488
 489         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MWID, val);
 490
 491         return 0;
 492 }
 493
 494 static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
 495                                      const struct stm32_fmc2_prop *prop,
 496                                      int cs, u32 setup)
 497 {
 498         u32 val;
 499
 500         switch (setup) {
 501         case FMC2_CPSIZE_0:
 502                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
 503                 break;
 504         case FMC2_CPSIZE_128:
 505                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
 506                 break;
 507         case FMC2_CPSIZE_256:
 508                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
 509                 break;
 510         case FMC2_CPSIZE_512:
 511                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
 512                 break;
 513         case FMC2_CPSIZE_1024:
 514                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
 515                 break;
 516         default:
 517                 /* Cpsize not supported */
 518                 return -EINVAL;
 519         }
 520
 521         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
 522
 523         return 0;
 524 }
 525
 526 static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
 527                                        const struct stm32_fmc2_prop *prop,
 528                                        int cs, u32 setup)
 529 {
 530         u32 val;
 531
 532         val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
 533         val = FIELD_PREP(FMC2_BCR_NBLSET, val);
 534         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
 535
 536         return 0;
 537 }
 538
 539 static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
 540                                             const struct stm32_fmc2_prop *prop,
 541                                             int cs, u32 setup)
 542 {
 543         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 544         u32 bxtr = prop->reg_type == FMC2_REG_BWTR ?
 545                    readl(ebi->io_base + FMC2_BWTR(cs)) :
 546                    readl(ebi->io_base + FMC2_BTR(cs));
 547         u32 reg, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 548         int ret;
 549
 550         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 551         if (ret)
 552                 return ret;
 553
 554         if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
 555                 val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
 556         else
 557                 val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
 558         val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
 559         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDSET, val);
 560
 561         return 0;
 562 }
 563
 564 static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
 565                                            const struct stm32_fmc2_prop *prop,
 566                                            int cs, u32 setup)
 567 {
 568         u32 val, reg;
 569         int ret;
 570
 571         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 572         if (ret)
 573                 return ret;
 574
 575         val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
 576         val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
 577         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDHLD, val);
 578
 579         return 0;
 580 }
 581
 582 static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
 583                                          const struct stm32_fmc2_prop *prop,
 584                                          int cs, u32 setup)
 585 {
 586         u32 val, reg;
 587         int ret;
 588
 589         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 590         if (ret)
 591                 return ret;
 592
 593         val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
 594         val = FIELD_PREP(FMC2_BXTR_DATAST, val);
 595         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAST, val);
 596
 597         return 0;
 598 }
 599
 600 static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
 601                                              const struct stm32_fmc2_prop *prop,
 602                                              int cs, u32 setup)
 603 {
 604         u32 val, reg;
 605         int ret;
 606
 607         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 608         if (ret)
 609                 return ret;
 610
 611         val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
 612         val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
 613         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_BUSTURN, val);
 614
 615         return 0;
 616 }
 617
 618 static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
 619                                         const struct stm32_fmc2_prop *prop,
 620                                         int cs, u32 setup)
 621 {
 622         u32 val, reg;
 623         int ret;
 624
 625         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 626         if (ret)
 627                 return ret;
 628
 629         if (prop->reg_type == FMC2_REG_BWTR)
 630                 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
 631         else
 632                 val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
 633         val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
 634         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAHLD, val);
 635
 636         return 0;
 637 }
 638
 639 static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
 640                                          const struct stm32_fmc2_prop *prop,
 641                                          int cs, u32 setup)
 642 {
 643         u32 val;
 644
 645         val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
 646         val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
 647         clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
 648
 649         return 0;
 650 }
 651
 652 static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
 653                                            const struct stm32_fmc2_prop *prop,
 654                                            int cs, u32 setup)
 655 {
 656         u32 val;
 657
 658         val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
 659         val = FIELD_PREP(FMC2_BTR_DATLAT, val);
 660         clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
 661
 662         return 0;
 663 }
 664
 665 static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
 666                                             const struct stm32_fmc2_prop *prop,
 667                                             int cs, u32 setup)
 668 {
 669         u32 old_val, new_val, pcscntr;
 670
 671         if (setup < 1)
 672                 return 0;
 673
 674         pcscntr = readl(ebi->io_base + FMC2_PCSCNTR);
 675
 676         /* Enable counter for the bank */
 677         setbits_le32(ebi->io_base + FMC2_PCSCNTR, FMC2_PCSCNTR_CNTBEN(cs));
 678
 679         new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
 680         old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
 681         if (old_val && new_val > old_val)
 682                 /* Keep current counter value */
 683                 return 0;
 684
 685         new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
 686         clrsetbits_le32(ebi->io_base + FMC2_PCSCNTR,
 687                         FMC2_PCSCNTR_CSCOUNT, new_val);
 688
 689         return 0;
 690 }
 691
 692 static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
 693         /* st,fmc2-ebi-cs-trans-type must be the first property */
 694         {
 695                 .name = "st,fmc2-ebi-cs-transaction-type",
 696                 .mprop = true,
 697                 .set = stm32_fmc2_ebi_set_trans_type,
 698         },
 699         {
 700                 .name = "st,fmc2-ebi-cs-cclk-enable",
 701                 .bprop = true,
 702                 .reg_type = FMC2_REG_BCR,
 703                 .reg_mask = FMC2_BCR1_CCLKEN,
 704                 .check = stm32_fmc2_ebi_check_cclk,
 705                 .set = stm32_fmc2_ebi_set_bit_field,
 706         },
 707         {
 708                 .name = "st,fmc2-ebi-cs-mux-enable",
 709                 .bprop = true,
 710                 .reg_type = FMC2_REG_BCR,
 711                 .reg_mask = FMC2_BCR_MUXEN,
 712                 .check = stm32_fmc2_ebi_check_mux,
 713                 .set = stm32_fmc2_ebi_set_bit_field,
 714         },
 715         {
 716                 .name = "st,fmc2-ebi-cs-buswidth",
 717                 .reset_val = FMC2_BUSWIDTH_16,
 718                 .set = stm32_fmc2_ebi_set_buswidth,
 719         },
 720         {
 721                 .name = "st,fmc2-ebi-cs-waitpol-high",
 722                 .bprop = true,
 723                 .reg_type = FMC2_REG_BCR,
 724                 .reg_mask = FMC2_BCR_WAITPOL,
 725                 .set = stm32_fmc2_ebi_set_bit_field,
 726         },
 727         {
 728                 .name = "st,fmc2-ebi-cs-waitcfg-enable",
 729                 .bprop = true,
 730                 .reg_type = FMC2_REG_BCR,
 731                 .reg_mask = FMC2_BCR_WAITCFG,
 732                 .check = stm32_fmc2_ebi_check_waitcfg,
 733                 .set = stm32_fmc2_ebi_set_bit_field,
 734         },
 735         {
 736                 .name = "st,fmc2-ebi-cs-wait-enable",
 737                 .bprop = true,
 738                 .reg_type = FMC2_REG_BCR,
 739                 .reg_mask = FMC2_BCR_WAITEN,
 740                 .check = stm32_fmc2_ebi_check_sync_trans,
 741                 .set = stm32_fmc2_ebi_set_bit_field,
 742         },
 743         {
 744                 .name = "st,fmc2-ebi-cs-asyncwait-enable",
 745                 .bprop = true,
 746                 .reg_type = FMC2_REG_BCR,
 747                 .reg_mask = FMC2_BCR_ASYNCWAIT,
 748                 .check = stm32_fmc2_ebi_check_async_trans,
 749                 .set = stm32_fmc2_ebi_set_bit_field,
 750         },
 751         {
 752                 .name = "st,fmc2-ebi-cs-cpsize",
 753                 .check = stm32_fmc2_ebi_check_cpsize,
 754                 .set = stm32_fmc2_ebi_set_cpsize,
 755         },
 756         {
 757                 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
 758                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 759                 .set = stm32_fmc2_ebi_set_bl_setup,
 760         },
 761         {
 762                 .name = "st,fmc2-ebi-cs-address-setup-ns",
 763                 .reg_type = FMC2_REG_BTR,
 764                 .reset_val = FMC2_BXTR_ADDSET_MAX,
 765                 .check = stm32_fmc2_ebi_check_async_trans,
 766                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 767                 .set = stm32_fmc2_ebi_set_address_setup,
 768         },
 769         {
 770                 .name = "st,fmc2-ebi-cs-address-hold-ns",
 771                 .reg_type = FMC2_REG_BTR,
 772                 .reset_val = FMC2_BXTR_ADDHLD_MAX,
 773                 .check = stm32_fmc2_ebi_check_address_hold,
 774                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 775                 .set = stm32_fmc2_ebi_set_address_hold,
 776         },
 777         {
 778                 .name = "st,fmc2-ebi-cs-data-setup-ns",
 779                 .reg_type = FMC2_REG_BTR,
 780                 .reset_val = FMC2_BXTR_DATAST_MAX,
 781                 .check = stm32_fmc2_ebi_check_async_trans,
 782                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 783                 .set = stm32_fmc2_ebi_set_data_setup,
 784         },
 785         {
 786                 .name = "st,fmc2-ebi-cs-bus-turnaround-ns",
 787                 .reg_type = FMC2_REG_BTR,
 788                 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
 789                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 790                 .set = stm32_fmc2_ebi_set_bus_turnaround,
 791         },
 792         {
 793                 .name = "st,fmc2-ebi-cs-data-hold-ns",
 794                 .reg_type = FMC2_REG_BTR,
 795                 .check = stm32_fmc2_ebi_check_async_trans,
 796                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 797                 .set = stm32_fmc2_ebi_set_data_hold,
 798         },
 799         {
 800                 .name = "st,fmc2-ebi-cs-clk-period-ns",
 801                 .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
 802                 .check = stm32_fmc2_ebi_check_clk_period,
 803                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 804                 .set = stm32_fmc2_ebi_set_clk_period,
 805         },
 806         {
 807                 .name = "st,fmc2-ebi-cs-data-latency-ns",
 808                 .check = stm32_fmc2_ebi_check_sync_trans,
 809                 .calculate = stm32_fmc2_ebi_ns_to_clk_period,
 810                 .set = stm32_fmc2_ebi_set_data_latency,
 811         },
 812         {
 813                 .name = "st,fmc2-ebi-cs-write-address-setup-ns",
 814                 .reg_type = FMC2_REG_BWTR,
 815                 .reset_val = FMC2_BXTR_ADDSET_MAX,
 816                 .check = stm32_fmc2_ebi_check_async_trans,
 817                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 818                 .set = stm32_fmc2_ebi_set_address_setup,
 819         },
 820         {
 821                 .name = "st,fmc2-ebi-cs-write-address-hold-ns",
 822                 .reg_type = FMC2_REG_BWTR,
 823                 .reset_val = FMC2_BXTR_ADDHLD_MAX,
 824                 .check = stm32_fmc2_ebi_check_address_hold,
 825                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 826                 .set = stm32_fmc2_ebi_set_address_hold,
 827         },
 828         {
 829                 .name = "st,fmc2-ebi-cs-write-data-setup-ns",
 830                 .reg_type = FMC2_REG_BWTR,
 831                 .reset_val = FMC2_BXTR_DATAST_MAX,
 832                 .check = stm32_fmc2_ebi_check_async_trans,
 833                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 834                 .set = stm32_fmc2_ebi_set_data_setup,
 835         },
 836         {
 837                 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
 838                 .reg_type = FMC2_REG_BWTR,
 839                 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
 840                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 841                 .set = stm32_fmc2_ebi_set_bus_turnaround,
 842         },
 843         {
 844                 .name = "st,fmc2-ebi-cs-write-data-hold-ns",
 845                 .reg_type = FMC2_REG_BWTR,
 846                 .check = stm32_fmc2_ebi_check_async_trans,
 847                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 848                 .set = stm32_fmc2_ebi_set_data_hold,
 849         },
 850         {
 851                 .name = "st,fmc2-ebi-cs-max-low-pulse-ns",
 852                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 853                 .set = stm32_fmc2_ebi_set_max_low_pulse,
 854         },
 855 };
 856
 857 static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
 858                                      ofnode node,
 859                                      const struct stm32_fmc2_prop *prop,
 860                                      int cs)
 861 {
 862         u32 setup = 0;
 863
 864         if (!prop->set) {
 865                 log_err("property %s is not well defined\n", prop->name);
 866                 return -EINVAL;
 867         }
 868
 869         if (prop->check && prop->check(ebi, prop, cs))
 870                 /* Skip this property */
 871                 return 0;
 872
 873         if (prop->bprop) {
 874                 bool bprop;
 875
 876                 bprop = ofnode_read_bool(node, prop->name);
 877                 if (prop->mprop && !bprop) {
 878                         log_err("mandatory property %s not defined in the device tree\n",
 879                                 prop->name);
 880                         return -EINVAL;
 881                 }
 882
 883                 if (bprop)
 884                         setup = 1;
 885         } else {
 886                 u32 val;
 887                 int ret;
 888
 889                 ret = ofnode_read_u32(node, prop->name, &val);
 890                 if (prop->mprop && ret) {
 891                         log_err("mandatory property %s not defined in the device tree\n",
 892                                 prop->name);
 893                         return ret;
 894                 }
 895
 896                 if (ret)
 897                         setup = prop->reset_val;
 898                 else if (prop->calculate)
 899                         setup = prop->calculate(ebi, cs, val);
 900                 else
 901                         setup = val;
 902         }
 903
 904         return prop->set(ebi, prop, cs, setup);
 905 }
 906
 907 static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
 908 {
 909         setbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN);
 910 }
 911
 912 static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
 913 {
 914         clrbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN);
 915 }
 916
 917 /* NWAIT signal can not be connected to EBI controller and NAND controller */
 918 static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
 919 {
 920         unsigned int cs;
 921         u32 bcr;
 922
 923         for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
 924                 if (!(ebi->bank_assigned & BIT(cs)))
 925                         continue;
 926
 927                 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 928                 if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
 929                     ebi->bank_assigned & BIT(FMC2_NAND))
 930                         return true;
 931         }
 932
 933         return false;
 934 }
 935
 936 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
 937 {
 938         setbits_le32(ebi->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN);
 939 }
 940
 941 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
 942                                    ofnode node, u32 cs)
 943 {
 944         unsigned int i;
 945         int ret;
 946
 947         stm32_fmc2_ebi_disable_bank(ebi, cs);
 948
 949         for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
 950                 const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
 951
 952                 ret = stm32_fmc2_ebi_parse_prop(ebi, node, p, cs);
 953                 if (ret) {
 954                         log_err("property %s could not be set: %d\n",
 955                                 p->name, ret);
 956                         return ret;
 957                 }
 958         }
 959
 960         stm32_fmc2_ebi_enable_bank(ebi, cs);
 961
 962         return 0;
 963 }
 964
 965 static int stm32_fmc2_ebi_parse_dt(struct udevice *dev,
 966                                    struct stm32_fmc2_ebi *ebi)
 967 {
 968         ofnode child;
 969         bool child_found = false;
 970         u32 bank;
 971         int ret;
 972
 973         dev_for_each_subnode(child, dev) {
 974                 ret = ofnode_read_u32(child, "reg", &bank);
 975                 if (ret) {
 976                         dev_err(dev, "could not retrieve reg property: %d\n", ret);
 977                         return ret;
 978                 }
 979
 980                 if (bank >= FMC2_MAX_BANKS) {
 981                         dev_err(dev, "invalid reg value: %d\n", bank);
 982                         return -EINVAL;
 983                 }
 984
 985                 if (ebi->bank_assigned & BIT(bank)) {
 986                         dev_err(dev, "bank already assigned: %d\n", bank);
 987                         return -EINVAL;
 988                 }
 989
 990                 if (bank < FMC2_MAX_EBI_CE) {
 991                         ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
 992                         if (ret) {
 993                                 dev_err(dev, "setup chip select %d failed: %d\n", bank, ret);
 994                                 return ret;
 995                         }
 996                 }
 997
 998                 ebi->bank_assigned |= BIT(bank);
 999                 child_found = true;
1000         }
1001
1002         if (!child_found) {
1003                 dev_warn(dev, "no subnodes found, disable the driver.\n");
1004                 return -ENODEV;
1005         }
1006
1007         if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
1008                 dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
1009                 return -EINVAL;
1010         }
1011
1012         stm32_fmc2_ebi_enable(ebi);
1013
1014         return 0;
1015 }
1016
1017 static int stm32_fmc2_ebi_probe(struct udevice *dev)
1018 {
1019         struct stm32_fmc2_ebi *ebi = dev_get_priv(dev);
1020         struct reset_ctl reset;
1021         int ret;
1022
1023         ebi->io_base = dev_read_addr(dev);
1024         if (ebi->io_base == FDT_ADDR_T_NONE)
1025                 return -EINVAL;
1026
1027         ret = clk_get_by_index(dev, 0, &ebi->clk);
1028         if (ret)
1029                 return ret;
1030
1031         ret = clk_enable(&ebi->clk);
1032         if (ret)
1033                 return ret;
1034
1035         ret = reset_get_by_index(dev, 0, &reset);
1036         if (!ret) {
1037                 reset_assert(&reset);
1038                 udelay(2);
1039                 reset_deassert(&reset);
1040         }
1041
1042         return stm32_fmc2_ebi_parse_dt(dev, ebi);
1043 }
1044
1045 static const struct udevice_id stm32_fmc2_ebi_match[] = {
1046         {.compatible = "st,stm32mp1-fmc2-ebi"},
1047         { /* Sentinel */ }
1048 };
1049
1050 U_BOOT_DRIVER(stm32_fmc2_ebi) = {
1051         .name = "stm32_fmc2_ebi",
1052         .id = UCLASS_NOP,
1053         .of_match = stm32_fmc2_ebi_match,
1054         .probe = stm32_fmc2_ebi_probe,
1055         .priv_auto      = sizeof(struct stm32_fmc2_ebi),
1056         .bind = dm_scan_fdt_dev,
1057 };