include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #define CONFIG_FSL_SATA_V2
  16 #define CONFIG_PCIE4
  17
  18 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  19
  20 #ifdef CONFIG_RAMBOOT_PBL
  21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  22 #ifndef CONFIG_SDCARD
  23 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  24 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  25 #else
  26 #define CONFIG_SPL_FLUSH_IMAGE
  27 #define CONFIG_SPL_PAD_TO               0x40000
  28 #define CONFIG_SPL_MAX_SIZE             0x28000
  29 #define RESET_VECTOR_OFFSET             0x27FFC
  30 #define BOOT_PAGE_OFFSET                0x27000
  31
  32 #ifdef  CONFIG_SDCARD
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  34 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  35 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  36 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  37 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  38 #ifndef CONFIG_SPL_BUILD
  39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  40 #endif
  41 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  42 #endif
  43
  44 #ifdef CONFIG_SPL_BUILD
  45 #define CONFIG_SPL_SKIP_RELOCATE
  46 #define CONFIG_SPL_COMMON_INIT_DDR
  47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  48 #endif
  49
  50 #endif
  51 #endif /* CONFIG_RAMBOOT_PBL */
  52
  53 /* High Level Configuration Options */
  54 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  55
  56 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  57 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  58 #endif
  59
  60 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  61 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  62 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  63 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  64 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  65 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  66
  67 /*
  68  * These can be toggled for performance analysis, otherwise use default.
  69  */
  70 #define CONFIG_SYS_CACHE_STASHING
  71 #define CONFIG_BTB                      /* toggle branch predition */
  72 #ifdef CONFIG_DDR_ECC
  73 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  74 #endif
  75
  76 #define CONFIG_ENABLE_36BIT_PHYS
  77
  78 /*
  79  *  Config the L3 Cache as L3 SRAM
  80  */
  81 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  82 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  83 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  84 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  85 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  86 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  87 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
  88
  89 #define CONFIG_SYS_DCSRBAR              0xf0000000
  90 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  91
  92 /*
  93  * DDR Setup
  94  */
  95 #define CONFIG_VERY_BIG_RAM
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  97 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  98
  99 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 100 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 101
 102 /*
 103  * IFC Definitions
 104  */
 105 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 106 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 107
 108 #ifdef CONFIG_SPL_BUILD
 109 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 110 #else
 111 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 112 #endif
 113
 114 #define CONFIG_HWCONFIG
 115
 116 /* define to use L1 as initial stack */
 117 #define CONFIG_L1_INIT_RAM
 118 #define CONFIG_SYS_INIT_RAM_LOCK
 119 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 120 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 121 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 122 /* The assembler doesn't like typecast */
 123 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 124         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 125           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 126 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 127
 128 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 129                                         GENERATED_GBL_DATA_SIZE)
 130 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 131
 132 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 133 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 134
 135 /* Serial Port - controlled on board with jumper J8
 136  * open - index 2
 137  * shorted - index 1
 138  */
 139 #define CONFIG_SYS_NS16550_SERIAL
 140 #define CONFIG_SYS_NS16550_REG_SIZE     1
 141 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 142
 143 #define CONFIG_SYS_BAUDRATE_TABLE       \
 144         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 145
 146 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 147 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 148 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 149 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 150
 151 /* I2C */
 152
 153 /*
 154  * General PCI
 155  * Memory space is mapped 1-1, but I/O space must start from 0.
 156  */
 157
 158 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 159 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 160 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 161 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 162 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 163
 164 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 165 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 166 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 167 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 168 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 169
 170 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 171 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 172 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 173 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 174 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 175
 176 /* controller 4, Base address 203000 */
 177 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 178 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 179 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 180
 181 #ifdef CONFIG_PCI
 182 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 183 #endif  /* CONFIG_PCI */
 184
 185 /* SATA */
 186 #ifdef CONFIG_FSL_SATA_V2
 187 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 188 #define CONFIG_SATA1
 189 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 190 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 191 #define CONFIG_SATA2
 192 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 193 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 194
 195 #define CONFIG_LBA48
 196 #endif
 197
 198 #ifdef CONFIG_FMAN_ENET
 199 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 200 #endif
 201
 202 /*
 203  * Environment
 204  */
 205 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 206 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 207
 208 /*
 209  * Miscellaneous configurable options
 210  */
 211 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 212
 213 /*
 214  * For booting Linux, the board info and command line data
 215  * have to be in the first 64 MB of memory, since this is
 216  * the maximum mapped by the Linux kernel during initialization.
 217  */
 218 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 219 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 220
 221 #ifdef CONFIG_CMD_KGDB
 222 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 223 #endif
 224
 225 /*
 226  * Environment Configuration
 227  */
 228 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 229 #define CONFIG_BOOTFILE         "uImage"
 230 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 231
 232 /* default location for tftp and bootm */
 233 #define CONFIG_LOADADDR         1000000
 234
 235 #define HVBOOT                                  \
 236         "setenv bootargs config-addr=0x60000000; "      \
 237         "bootm 0x01000000 - 0x00f00000"
 238
 239 #define CONFIG_SYS_CLK_FREQ     66666666
 240
 241 #ifndef __ASSEMBLY__
 242 unsigned long get_board_sys_clk(void);
 243 #endif
 244
 245 /*
 246  * DDR Setup
 247  */
 248 #define CONFIG_SYS_SPD_BUS_NUM  0
 249 #define SPD_EEPROM_ADDRESS1     0x52
 250 #define SPD_EEPROM_ADDRESS2     0x54
 251 #define SPD_EEPROM_ADDRESS3     0x56
 252 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 253 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 254
 255 /*
 256  * IFC Definitions
 257  */
 258 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 259 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 260                                 + 0x8000000) | \
 261                                 CSPR_PORT_SIZE_16 | \
 262                                 CSPR_MSEL_NOR | \
 263                                 CSPR_V)
 264 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 265 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 266                                 CSPR_PORT_SIZE_16 | \
 267                                 CSPR_MSEL_NOR | \
 268                                 CSPR_V)
 269 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 270 /* NOR Flash Timing Params */
 271 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 272
 273 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 274                                 FTIM0_NOR_TEADC(0x5) | \
 275                                 FTIM0_NOR_TEAHC(0x5))
 276 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 277                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 278                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 279 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 280                                 FTIM2_NOR_TCH(0x4) | \
 281                                 FTIM2_NOR_TWPH(0x0E) | \
 282                                 FTIM2_NOR_TWP(0x1c))
 283 #define CONFIG_SYS_NOR_FTIM3    0x0
 284
 285 #define CONFIG_SYS_FLASH_QUIET_TEST
 286 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 287
 288 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 289 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 290 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 291 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 292
 293 #define CONFIG_SYS_FLASH_EMPTY_INFO
 294 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 295                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 296
 297 /* NAND Flash on IFC */
 298 #define CONFIG_NAND_FSL_IFC
 299 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 300 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 301 #define CONFIG_SYS_NAND_BASE            0xff800000
 302 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 303
 304 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 305 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 306                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 307                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 308                                 | CSPR_V)
 309 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 310
 311 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 312                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 313                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 314                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 315                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 316                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 317                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 318
 319 #define CONFIG_SYS_NAND_ONFI_DETECTION
 320
 321 /* ONFI NAND Flash mode0 Timing Params */
 322 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 323                                         FTIM0_NAND_TWP(0x18)   | \
 324                                         FTIM0_NAND_TWCHT(0x07) | \
 325                                         FTIM0_NAND_TWH(0x0a))
 326 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 327                                         FTIM1_NAND_TWBE(0x39)  | \
 328                                         FTIM1_NAND_TRR(0x0e)   | \
 329                                         FTIM1_NAND_TRP(0x18))
 330 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 331                                         FTIM2_NAND_TREH(0x0a) | \
 332                                         FTIM2_NAND_TWHRE(0x1e))
 333 #define CONFIG_SYS_NAND_FTIM3           0x0
 334
 335 #define CONFIG_SYS_NAND_DDR_LAW         11
 336 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 337 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 338
 339 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 340
 341 #if defined(CONFIG_MTD_RAW_NAND)
 342 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 343 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 344 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 345 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 346 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 347 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 348 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 349 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 350 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 351 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 352 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 353 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 354 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 355 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 356 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 357 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 358 #else
 359 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 360 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 361 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 362 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 363 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 364 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 365 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 366 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 367 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 368 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 369 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 370 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 371 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 372 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 373 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 374 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 375 #endif
 376 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 377 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 378 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 379 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 380 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 381 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 382 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 383 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 384
 385 /* CPLD on IFC */
 386 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 387 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 388 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 389 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 390                                 | CSPR_PORT_SIZE_8 \
 391                                 | CSPR_MSEL_GPCM \
 392                                 | CSPR_V)
 393
 394 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 395 #define CONFIG_SYS_CSOR3        0x0
 396
 397 /* CPLD Timing parameters for IFC CS3 */
 398 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 399                                         FTIM0_GPCM_TEADC(0x0e) | \
 400                                         FTIM0_GPCM_TEAHC(0x0e))
 401 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 402                                         FTIM1_GPCM_TRAD(0x1f))
 403 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 404                                         FTIM2_GPCM_TCH(0x8) | \
 405                                         FTIM2_GPCM_TWP(0x1f))
 406 #define CONFIG_SYS_CS3_FTIM3            0x0
 407
 408 #if defined(CONFIG_RAMBOOT_PBL)
 409 #define CONFIG_SYS_RAMBOOT
 410 #endif
 411
 412 /* I2C */
 413 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 414 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 415
 416 #define I2C_MUX_CH_DEFAULT      0x8
 417 #define I2C_MUX_CH_VOL_MONITOR  0xa
 418 #define I2C_MUX_CH_VSC3316_FS   0xc
 419 #define I2C_MUX_CH_VSC3316_BS   0xd
 420
 421 /* Voltage monitor on channel 2*/
 422 #define I2C_VOL_MONITOR_ADDR            0x40
 423 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 424 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 425 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 426
 427 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 428 #ifndef CONFIG_SPL_BUILD
 429 #define CONFIG_VID
 430 #endif
 431 #define CONFIG_VOL_MONITOR_IR36021_SET
 432 #define CONFIG_VOL_MONITOR_IR36021_READ
 433 /* The lowest and highest voltage allowed for T4240RDB */
 434 #define VDD_MV_MIN                      819
 435 #define VDD_MV_MAX                      1212
 436
 437 /*
 438  * eSPI - Enhanced SPI
 439  */
 440
 441 /* Qman/Bman */
 442 #ifndef CONFIG_NOBQFMAN
 443 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 444 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 445 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 446 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 447 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 448 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 449 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 450 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 451 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 452                                         CONFIG_SYS_BMAN_CENA_SIZE)
 453 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 454 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 455 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 456 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 457 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 458 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 459 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 460 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 461 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 462 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 463 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 464                                         CONFIG_SYS_QMAN_CENA_SIZE)
 465 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 466 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 467
 468 #define CONFIG_SYS_DPAA_FMAN
 469 #define CONFIG_SYS_DPAA_PME
 470 #define CONFIG_SYS_PMAN
 471 #define CONFIG_SYS_DPAA_DCE
 472 #define CONFIG_SYS_DPAA_RMAN
 473 #define CONFIG_SYS_INTERLAKEN
 474
 475 /* Default address of microcode for the Linux Fman driver */
 476 #if defined(CONFIG_SPIFLASH)
 477 /*
 478  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 479  * env, so we got 0x110000.
 480  */
 481 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 482 #elif defined(CONFIG_SDCARD)
 483 /*
 484  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 485  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 486  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 487  */
 488 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 489 #elif defined(CONFIG_MTD_RAW_NAND)
 490 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 491 #else
 492 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 493 #endif
 494 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 495 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 496 #endif /* CONFIG_NOBQFMAN */
 497
 498 #ifdef CONFIG_SYS_DPAA_FMAN
 499 #define SGMII_PHY_ADDR1 0x0
 500 #define SGMII_PHY_ADDR2 0x1
 501 #define SGMII_PHY_ADDR3 0x2
 502 #define SGMII_PHY_ADDR4 0x3
 503 #define SGMII_PHY_ADDR5 0x4
 504 #define SGMII_PHY_ADDR6 0x5
 505 #define SGMII_PHY_ADDR7 0x6
 506 #define SGMII_PHY_ADDR8 0x7
 507 #define FM1_10GEC1_PHY_ADDR     0x10
 508 #define FM1_10GEC2_PHY_ADDR     0x11
 509 #define FM2_10GEC1_PHY_ADDR     0x12
 510 #define FM2_10GEC2_PHY_ADDR     0x13
 511 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 512 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 513 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 514 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 515 #endif
 516
 517 /* SATA */
 518 #ifdef CONFIG_FSL_SATA_V2
 519 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 520 #define CONFIG_SATA1
 521 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 522 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 523 #define CONFIG_SATA2
 524 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 525 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 526
 527 #define CONFIG_LBA48
 528 #endif
 529
 530 #ifdef CONFIG_FMAN_ENET
 531 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 532 #endif
 533
 534 /*
 535 * USB
 536 */
 537 #define CONFIG_USB_EHCI_FSL
 538 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 539 #define CONFIG_HAS_FSL_DR_USB
 540
 541 #ifdef CONFIG_MMC
 542 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 543 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 544 #endif
 545
 546
 547 #define __USB_PHY_TYPE  utmi
 548
 549 /*
 550  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 551  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 552  * interleaving. It can be cacheline, page, bank, superbank.
 553  * See doc/README.fsl-ddr for details.
 554  */
 555 #ifdef CONFIG_ARCH_T4240
 556 #define CTRL_INTLV_PREFERED 3way_4KB
 557 #else
 558 #define CTRL_INTLV_PREFERED cacheline
 559 #endif
 560
 561 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 562         "hwconfig=fsl_ddr:"                                     \
 563         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 564         "bank_intlv=auto;"                                      \
 565         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 566         "netdev=eth0\0"                                         \
 567         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 568         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 569         "tftpflash=tftpboot $loadaddr $uboot && "               \
 570         "protect off $ubootaddr +$filesize && "                 \
 571         "erase $ubootaddr +$filesize && "                       \
 572         "cp.b $loadaddr $ubootaddr $filesize && "               \
 573         "protect on $ubootaddr +$filesize && "                  \
 574         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 575         "consoledev=ttyS0\0"                                    \
 576         "ramdiskaddr=2000000\0"                                 \
 577         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 578         "fdtaddr=1e00000\0"                                     \
 579         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 580         "bdev=sda3\0"
 581
 582 #define HVBOOT                                  \
 583         "setenv bootargs config-addr=0x60000000; "      \
 584         "bootm 0x01000000 - 0x00f00000"
 585
 586 #define LINUXBOOTCOMMAND                                        \
 587         "setenv bootargs root=/dev/ram rw "             \
 588         "console=$consoledev,$baudrate $othbootargs;"   \
 589         "setenv ramdiskaddr 0x02000000;"                \
 590         "setenv fdtaddr 0x00c00000;"                    \
 591         "setenv loadaddr 0x1000000;"                    \
 592         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 593
 594 #define HDBOOT                                  \
 595         "setenv bootargs root=/dev/$bdev rw "           \
 596         "console=$consoledev,$baudrate $othbootargs;"   \
 597         "tftp $loadaddr $bootfile;"                     \
 598         "tftp $fdtaddr $fdtfile;"                       \
 599         "bootm $loadaddr - $fdtaddr"
 600
 601 #define NFSBOOTCOMMAND                  \
 602         "setenv bootargs root=/dev/nfs rw "     \
 603         "nfsroot=$serverip:$rootpath "          \
 604         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 605         "console=$consoledev,$baudrate $othbootargs;"   \
 606         "tftp $loadaddr $bootfile;"             \
 607         "tftp $fdtaddr $fdtfile;"               \
 608         "bootm $loadaddr - $fdtaddr"
 609
 610 #define RAMBOOTCOMMAND                          \
 611         "setenv bootargs root=/dev/ram rw "             \
 612         "console=$consoledev,$baudrate $othbootargs;"   \
 613         "tftp $ramdiskaddr $ramdiskfile;"               \
 614         "tftp $loadaddr $bootfile;"                     \
 615         "tftp $fdtaddr $fdtfile;"                       \
 616         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 617
 618 #define CONFIG_BOOTCOMMAND              LINUXBOOTCOMMAND
 619
 620 #include <asm/fsl_secure_boot.h>
 621
 622 #endif  /* __CONFIG_H */