include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  19 #endif
  20
  21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  22 /* Set 1M boot space */
  23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  25                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  27 #endif
  28
  29 /* High Level Configuration Options */
  30 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  31
  32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  34 #endif
  35
  36 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  37 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  38 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  39 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  40 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  41 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  42
  43 #define CONFIG_SYS_SRIO
  44 #define CONFIG_SRIO1                    /* SRIO port 1 */
  45 #define CONFIG_SRIO2                    /* SRIO port 2 */
  46 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  47 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  48
  49 #if defined(CONFIG_SPIFLASH)
  50 #elif defined(CONFIG_SDCARD)
  51         #define CONFIG_FSL_FIXED_MMC_LOCATION
  52 #endif
  53
  54 #ifndef __ASSEMBLY__
  55 unsigned long get_board_sys_clk(unsigned long dummy);
  56 #include <linux/stringify.h>
  57 #endif
  58 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  59
  60 /*
  61  * These can be toggled for performance analysis, otherwise use default.
  62  */
  63 #define CONFIG_SYS_CACHE_STASHING
  64 #define CONFIG_BACKSIDE_L2_CACHE
  65 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  66 #define CONFIG_BTB                      /* toggle branch predition */
  67
  68 #define CONFIG_ENABLE_36BIT_PHYS
  69
  70 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  71
  72 /*
  73  *  Config the L3 Cache as L3 SRAM
  74  */
  75 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  76 #ifdef CONFIG_PHYS_64BIT
  77 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  78                 CONFIG_RAMBOOT_TEXT_BASE)
  79 #else
  80 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  81 #endif
  82 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  83 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  84
  85 #ifdef CONFIG_PHYS_64BIT
  86 #define CONFIG_SYS_DCSRBAR              0xf0000000
  87 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  88 #endif
  89
  90 /* EEPROM */
  91 #define CONFIG_SYS_I2C_EEPROM_NXID
  92 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  93
  94 /*
  95  * DDR Setup
  96  */
  97 #define CONFIG_VERY_BIG_RAM
  98 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  99 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 100
 101 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 102 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 103
 104 #define CONFIG_SYS_SPD_BUS_NUM  0
 105 #define SPD_EEPROM_ADDRESS      0x52
 106 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 107
 108 /*
 109  * Local Bus Definitions
 110  */
 111
 112 /* Set the local bus clock 1/8 of platform clock */
 113 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 114
 115 /*
 116  * This board doesn't have a promjet connector.
 117  * However, it uses commone corenet board LAW and TLB.
 118  * It is necessary to use the same start address with proper offset.
 119  */
 120 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 121 #ifdef CONFIG_PHYS_64BIT
 122 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 123 #else
 124 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 125 #endif
 126
 127 #define CONFIG_SYS_FLASH_BR_PRELIM \
 128                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 129                 BR_PS_16 | BR_V)
 130 #define CONFIG_SYS_FLASH_OR_PRELIM \
 131                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 132                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 133
 134 #define CONFIG_FSL_CPLD
 135 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 136 #ifdef CONFIG_PHYS_64BIT
 137 #define CPLD_BASE_PHYS          0xfffdf0000ull
 138 #else
 139 #define CPLD_BASE_PHYS          CPLD_BASE
 140 #endif
 141
 142 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 143 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 144
 145 #define PIXIS_LBMAP_SWITCH      7
 146 #define PIXIS_LBMAP_MASK        0xf0
 147 #define PIXIS_LBMAP_SHIFT       4
 148 #define PIXIS_LBMAP_ALTBANK     0x40
 149
 150 #define CONFIG_SYS_FLASH_QUIET_TEST
 151 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 152
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 154 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 155 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 156 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 157
 158 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 159
 160 #if defined(CONFIG_RAMBOOT_PBL)
 161 #define CONFIG_SYS_RAMBOOT
 162 #endif
 163
 164 #define CONFIG_NAND_FSL_ELBC
 165 /* Nand Flash */
 166 #ifdef CONFIG_NAND_FSL_ELBC
 167 #define CONFIG_SYS_NAND_BASE            0xffa00000
 168 #ifdef CONFIG_PHYS_64BIT
 169 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 170 #else
 171 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 172 #endif
 173
 174 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 175 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 176 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 177
 178 /* NAND flash config */
 179 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 180                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 181                                | BR_PS_8               /* Port Size = 8 bit */ \
 182                                | BR_MS_FCM             /* MSEL = FCM */ \
 183                                | BR_V)                 /* valid */
 184 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 185                                | OR_FCM_PGS            /* Large Page*/ \
 186                                | OR_FCM_CSCT \
 187                                | OR_FCM_CST \
 188                                | OR_FCM_CHT \
 189                                | OR_FCM_SCY_1 \
 190                                | OR_FCM_TRLX \
 191                                | OR_FCM_EHTR)
 192
 193 #ifdef CONFIG_MTD_RAW_NAND
 194 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 195 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 196 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 197 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 198 #else
 199 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 200 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 201 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 202 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 203 #endif
 204 #else
 205 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 206 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 207 #endif /* CONFIG_NAND_FSL_ELBC */
 208
 209 #define CONFIG_SYS_FLASH_EMPTY_INFO
 210 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 211 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 212
 213 #define CONFIG_HWCONFIG
 214
 215 /* define to use L1 as initial stack */
 216 #define CONFIG_L1_INIT_RAM
 217 #define CONFIG_SYS_INIT_RAM_LOCK
 218 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 219 #ifdef CONFIG_PHYS_64BIT
 220 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 221 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 222 /* The assembler doesn't like typecast */
 223 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 224         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 225           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 226 #else
 227 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 228 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 229 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 230 #endif
 231 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 232
 233 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 234                                         GENERATED_GBL_DATA_SIZE)
 235 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 236
 237 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 238 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 239
 240 /* Serial Port - controlled on board with jumper J8
 241  * open - index 2
 242  * shorted - index 1
 243  */
 244 #define CONFIG_SYS_NS16550_SERIAL
 245 #define CONFIG_SYS_NS16550_REG_SIZE     1
 246 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 247
 248 #define CONFIG_SYS_BAUDRATE_TABLE       \
 249         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 250
 251 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 252 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 253 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 254 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 255
 256 /* I2C */
 257
 258
 259 /*
 260  * RapidIO
 261  */
 262 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 263 #ifdef CONFIG_PHYS_64BIT
 264 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 265 #else
 266 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 267 #endif
 268 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 269
 270 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 271 #ifdef CONFIG_PHYS_64BIT
 272 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 273 #else
 274 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 275 #endif
 276 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 277
 278 /*
 279  * for slave u-boot IMAGE instored in master memory space,
 280  * PHYS must be aligned based on the SIZE
 281  */
 282 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 283 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 284 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 285 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 286 /*
 287  * for slave UCODE and ENV instored in master memory space,
 288  * PHYS must be aligned based on the SIZE
 289  */
 290 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 291 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 292 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 293
 294 /* slave core release by master*/
 295 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 296 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 297
 298 /*
 299  * SRIO_PCIE_BOOT - SLAVE
 300  */
 301 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 302 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 303 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 304                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 305 #endif
 306
 307 /*
 308  * eSPI - Enhanced SPI
 309  */
 310
 311 /*
 312  * General PCI
 313  * Memory space is mapped 1-1, but I/O space must start from 0.
 314  */
 315
 316 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 317 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 318 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 319 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 320 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 321
 322 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 323 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 324 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 325 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 326 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 327
 328 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 329 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 330 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 331 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 332 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 333
 334 /* Qman/Bman */
 335 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 336 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 337 #ifdef CONFIG_PHYS_64BIT
 338 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 339 #else
 340 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 341 #endif
 342 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 343 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 344 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 345 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 346 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 347 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 348                                         CONFIG_SYS_BMAN_CENA_SIZE)
 349 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 350 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 351 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 352 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 353 #ifdef CONFIG_PHYS_64BIT
 354 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 355 #else
 356 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 357 #endif
 358 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 359 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 360 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 361 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 362 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 363 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 364                                         CONFIG_SYS_QMAN_CENA_SIZE)
 365 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 366 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 367
 368 #define CONFIG_SYS_DPAA_FMAN
 369 #define CONFIG_SYS_DPAA_PME
 370 /* Default address of microcode for the Linux Fman driver */
 371 #if defined(CONFIG_SPIFLASH)
 372 /*
 373  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 374  * env, so we got 0x110000.
 375  */
 376 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 377 #elif defined(CONFIG_SDCARD)
 378 /*
 379  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 380  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 381  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 382  */
 383 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 384 #elif defined(CONFIG_MTD_RAW_NAND)
 385 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 386 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 387 /*
 388  * Slave has no ucode locally, it can fetch this from remote. When implementing
 389  * in two corenet boards, slave's ucode could be stored in master's memory
 390  * space, the address can be mapped from slave TLB->slave LAW->
 391  * slave SRIO or PCIE outbound window->master inbound window->
 392  * master LAW->the ucode address in master's memory space.
 393  */
 394 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 395 #else
 396 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 397 #endif
 398 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 399 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 400
 401 #ifdef CONFIG_PCI
 402 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 403 #endif  /* CONFIG_PCI */
 404
 405 /* SATA */
 406 #define CONFIG_FSL_SATA_V2
 407
 408 #ifdef CONFIG_FSL_SATA_V2
 409 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 410 #define CONFIG_SATA1
 411 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 412 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 413 #define CONFIG_SATA2
 414 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 415 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 416
 417 #define CONFIG_LBA48
 418 #endif
 419
 420 #ifdef CONFIG_FMAN_ENET
 421 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 422 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 423 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 424 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 425 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 426
 427 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 428 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 429 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 430 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 431
 432 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 433
 434 #define CONFIG_SYS_TBIPA_VALUE  8
 435 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 436 #endif
 437
 438 /*
 439  * Environment
 440  */
 441 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 442 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 443
 444 /*
 445 * USB
 446 */
 447 #define CONFIG_HAS_FSL_DR_USB
 448 #define CONFIG_HAS_FSL_MPH_USB
 449
 450 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 451 #define CONFIG_USB_EHCI_FSL
 452 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 453 #endif
 454
 455 #ifdef CONFIG_MMC
 456 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 457 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 458 #endif
 459
 460 /*
 461  * Miscellaneous configurable options
 462  */
 463 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 464
 465 /*
 466  * For booting Linux, the board info and command line data
 467  * have to be in the first 64 MB of memory, since this is
 468  * the maximum mapped by the Linux kernel during initialization.
 469  */
 470 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 471 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 472
 473 #ifdef CONFIG_CMD_KGDB
 474 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 475 #endif
 476
 477 /*
 478  * Environment Configuration
 479  */
 480 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 481 #define CONFIG_BOOTFILE         "uImage"
 482 #define CONFIG_UBOOTPATH        u-boot.bin
 483
 484 /* default location for tftp and bootm */
 485 #define CONFIG_LOADADDR         1000000
 486
 487 #define __USB_PHY_TYPE  utmi
 488
 489 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 490         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 491         "bank_intlv=cs0_cs1\0"                                  \
 492         "netdev=eth0\0"                                         \
 493         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 494         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 495         "tftpflash=tftpboot $loadaddr $uboot && "               \
 496         "protect off $ubootaddr +$filesize && "                 \
 497         "erase $ubootaddr +$filesize && "                       \
 498         "cp.b $loadaddr $ubootaddr $filesize && "               \
 499         "protect on $ubootaddr +$filesize && "                  \
 500         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 501         "consoledev=ttyS0\0"                                    \
 502         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 503         "usb_dr_mode=host\0"                                    \
 504         "ramdiskaddr=2000000\0"                                 \
 505         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 506         "fdtaddr=1e00000\0"                                     \
 507         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 508         "bdev=sda3\0"
 509
 510 #define HDBOOT                                  \
 511         "setenv bootargs root=/dev/$bdev rw "           \
 512         "console=$consoledev,$baudrate $othbootargs;"   \
 513         "tftp $loadaddr $bootfile;"                     \
 514         "tftp $fdtaddr $fdtfile;"                       \
 515         "bootm $loadaddr - $fdtaddr"
 516
 517 #define NFSBOOTCOMMAND                  \
 518         "setenv bootargs root=/dev/nfs rw "     \
 519         "nfsroot=$serverip:$rootpath "          \
 520         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 521         "console=$consoledev,$baudrate $othbootargs;"   \
 522         "tftp $loadaddr $bootfile;"             \
 523         "tftp $fdtaddr $fdtfile;"               \
 524         "bootm $loadaddr - $fdtaddr"
 525
 526 #define RAMBOOTCOMMAND                          \
 527         "setenv bootargs root=/dev/ram rw "             \
 528         "console=$consoledev,$baudrate $othbootargs;"   \
 529         "tftp $ramdiskaddr $ramdiskfile;"               \
 530         "tftp $loadaddr $bootfile;"                     \
 531         "tftp $fdtaddr $fdtfile;"                       \
 532         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 533
 534 #define CONFIG_BOOTCOMMAND              HDBOOT
 535
 536 #include <asm/fsl_secure_boot.h>
 537
 538 #endif  /* __CONFIG_H */