2 * Configuation settings for the SAMA5D3xEK board.
4 * Copyright (C) 2012 - 2013 Atmel
6 * based on at91sam9m10g45ek.h by:
8 * Lead Tech Design <www.leadtechdesign.com>
10 * SPDX-License-Identifier: GPL-2.0+
16 #include "at91-sama5_common.h"
18 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
21 * This needs to be defined for the OHCI code to work but it is defined as
22 * ATMEL_ID_UHPHS in the CPU specific header files.
24 #define ATMEL_ID_UHP ATMEL_ID_UHPHS
27 * Specify the clock enable bit in the PMC_SCER register.
29 #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
32 #define LCD_BPP LCD_COLOR16
33 #define LCD_OUTPUT_BPP 24
34 #define CONFIG_LCD_LOGO
35 #define CONFIG_LCD_INFO
36 #define CONFIG_LCD_INFO_BELOW_LOGO
37 #define CONFIG_ATMEL_HLCD
38 #define CONFIG_ATMEL_LCD_RGB565
40 /* board specific (not enough SRAM) */
41 #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
44 #ifdef CONFIG_MTD_NOR_FLASH
45 #define CONFIG_FLASH_CFI_DRIVER
46 #define CONFIG_SYS_FLASH_CFI
47 #define CONFIG_SYS_FLASH_PROTECTION
48 #define CONFIG_SYS_FLASH_BASE 0x10000000
49 #define CONFIG_SYS_MAX_FLASH_SECT 131
50 #define CONFIG_SYS_MAX_FLASH_BANKS 1
54 #define CONFIG_NR_DRAM_BANKS 1
55 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
56 #define CONFIG_SYS_SDRAM_SIZE 0x20000000
58 #ifdef CONFIG_SPL_BUILD
59 #define CONFIG_SYS_INIT_SP_ADDR 0x318000
61 #define CONFIG_SYS_INIT_SP_ADDR \
62 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
68 #define CONFIG_SF_DEFAULT_SPEED 30000000
72 #define CONFIG_CMD_NAND
74 #ifdef CONFIG_CMD_NAND
75 #define CONFIG_NAND_ATMEL
76 #define CONFIG_SYS_MAX_NAND_DEVICE 1
77 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
79 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
81 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
82 #define CONFIG_SYS_NAND_ONFI_DETECTION
83 /* PMECC & PMERRLOC */
84 #define CONFIG_ATMEL_NAND_HWECC
85 #define CONFIG_ATMEL_NAND_HW_PMECC
86 #define CONFIG_PMECC_CAP 4
87 #define CONFIG_PMECC_SECTOR_SIZE 512
88 #define CONFIG_CMD_NAND_TRIMFFS
91 #define CONFIG_PHY_MICREL_KSZ9021
96 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
97 #define CONFIG_USB_OHCI_NEW
98 #define CONFIG_SYS_USB_OHCI_CPU_INIT
99 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
100 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
101 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
104 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
106 #ifdef CONFIG_SYS_USE_SERIALFLASH
107 /* override the bootcmd, bootargs and other configuration for spi flash env*/
108 #elif CONFIG_SYS_USE_NANDFLASH
109 /* override the bootcmd, bootargs and other configuration nandflash env */
110 #elif CONFIG_SYS_USE_MMC
111 /* override the bootcmd, bootargs and other configuration for sd/mmc env */
113 #define CONFIG_ENV_IS_NOWHERE
117 #define CONFIG_SPL_FRAMEWORK
118 #define CONFIG_SPL_TEXT_BASE 0x300000
119 #define CONFIG_SPL_MAX_SIZE 0x18000
120 #define CONFIG_SPL_BSS_START_ADDR 0x20000000
121 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
122 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
123 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
125 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
127 #ifdef CONFIG_SYS_USE_MMC
128 #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
129 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
130 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
132 #elif CONFIG_SYS_USE_NANDFLASH
133 #define CONFIG_SPL_NAND_DRIVERS
134 #define CONFIG_SPL_NAND_BASE
135 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
136 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
137 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
138 #define CONFIG_SYS_NAND_PAGE_COUNT 64
139 #define CONFIG_SYS_NAND_OOBSIZE 64
140 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
141 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
142 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
144 #elif CONFIG_SYS_USE_SERIALFLASH
145 #define CONFIG_SPL_SPI_LOAD
146 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000