board/cirrus/edb93xx/edb93xx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board initialization for EP93xx
   4  *
   5  * Copyright (C) 2013
   6  * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
   7  *
   8  * Copyright (C) 2009
   9  * Matthias Kaehlcke <matthias <at> kaehlcke.net>
  10  *
  11  * (C) Copyright 2002 2003
  12  * Network Audio Technologies, Inc. <www.netaudiotech.com>
  13  * Adam Bezanson <bezanson <at> netaudiotech.com>
  14  */
  15
  16 #include <config.h>
  17 #include <common.h>
  18 #include <cpu_func.h>
  19 #include <irq_func.h>
  20 #include <net.h>
  21 #include <netdev.h>
  22 #include <status_led.h>
  23 #include <asm/io.h>
  24 #include <asm/mach-types.h>
  25 #include <asm/arch/ep93xx.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /*
  30  * usb_div: 4, nbyp2: 1, pll2_en: 1
  31  * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
  32  * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
  33  */
  34 #define CLKSET2_VAL     (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |  \
  35                         24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |  \
  36                         24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |  \
  37                         1 << SYSCON_CLKSET_PLL_PS_SHIFT |       \
  38                         SYSCON_CLKSET2_PLL2_EN |                \
  39                         SYSCON_CLKSET2_NBYP2 |                  \
  40                         3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
  41
  42 #define SMC_BCR6_VALUE  (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
  43                         SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
  44                         1 << SMC_BCR_MW_SHIFT)
  45
  46 /* delay execution before timers are initialized */
  47 static inline void early_udelay(uint32_t usecs)
  48 {
  49         /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
  50         register uint32_t loops = (usecs * 1000) / 20;
  51
  52         __asm__ volatile ("1:\n"
  53                         "subs %0, %1, #1\n"
  54                         "bne 1b" : "=r" (loops) : "0" (loops));
  55 }
  56
  57 #ifndef CONFIG_EP93XX_NO_FLASH_CFG
  58 static void flash_cfg(void)
  59 {
  60         struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
  61
  62         writel(SMC_BCR6_VALUE, &smc->bcr6);
  63 }
  64 #else
  65 #define flash_cfg()
  66 #endif
  67
  68 int board_init(void)
  69 {
  70         /*
  71          * Setup PLL2, PPL1 has been set during lowlevel init
  72          */
  73         struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  74         writel(CLKSET2_VAL, &syscon->clkset2);
  75
  76         /*
  77          * the user's guide recommends to wait at least 1 ms for PLL2 to
  78          * stabilize
  79          */
  80         early_udelay(1000);
  81
  82         /* Go to Async mode */
  83         __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
  84         __asm__ volatile ("orr r0, r0, #0xc0000000");
  85         __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
  86
  87         icache_enable();
  88
  89 #ifdef USE_920T_MMU
  90         dcache_enable();
  91 #endif
  92
  93         /* Machine number, as defined in linux/arch/arm/tools/mach-types */
  94         gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
  95
  96         /* adress of boot parameters */
  97         gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  98
  99         /* We have a console */
 100         gd->have_console = 1;
 101
 102         enable_interrupts();
 103
 104         flash_cfg();
 105
 106         green_led_on();
 107         red_led_off();
 108
 109         return 0;
 110 }
 111
 112 int board_early_init_f(void)
 113 {
 114         /*
 115          * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
 116          * 14.7456/2 MHz
 117          */
 118         struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
 119         writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
 120         return 0;
 121 }
 122
 123 int board_eth_init(bd_t *bd)
 124 {
 125         return ep93xx_eth_initialize(0, MAC_BASE);
 126 }
 127
 128 static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
 129                                 unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
 130 {
 131         if (dram_bank_cnt == 1) {
 132                 dram_bank_base[0] = PHYS_SDRAM_1;
 133         } else {
 134                 /* Table lookup for holes in address space. Maximum memory
 135                  * for the single SDCS may be up to 256Mb. We start scanning
 136                  * banks from 1Mb, so it could be up to 128 banks theoretically.
 137                  * We need at maximum 7 bits for the loockup, 8 slots is
 138                  * enough for the worst case.
 139                  */
 140                 unsigned tbl[8];
 141                 unsigned i = dram_bank_cnt / 2;
 142                 unsigned j = 0x00100000; /* 1 Mb */
 143                 unsigned *ptbl = tbl;
 144                 do {
 145                         while (!(dram_addr_mask & j)) {
 146                                 j <<= 1;
 147                         }
 148                         *ptbl++ = j;
 149                         j <<= 1;
 150                         i >>= 1;
 151                 } while (i != 0);
 152
 153                 for (i = dram_bank_cnt, j = 0;
 154                      (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
 155                         unsigned addr = PHYS_SDRAM_1;
 156                         unsigned k;
 157                         unsigned bit;
 158
 159                         for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
 160                                 if (bit & j)
 161                                         addr |= tbl[k];
 162                         }
 163
 164                         dram_bank_base[j] = addr;
 165                 }
 166         }
 167 }
 168
 169 /* called in board_init_f (before relocation) */
 170 static unsigned dram_init_banksize_int(int print)
 171 {
 172         /*
 173          * Collect information of banks that has been filled during lowlevel
 174          * initialization
 175          */
 176         unsigned i;
 177         unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
 178         unsigned dram_total = 0;
 179         unsigned dram_bank_size = *(unsigned *)
 180                                   (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
 181         unsigned dram_addr_mask = *(unsigned *)
 182                                   (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
 183         unsigned dram_bank_cnt = *(unsigned *)
 184                                  (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
 185
 186         dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
 187
 188         for (i = 0; i < dram_bank_cnt; i++) {
 189                 gd->bd->bi_dram[i].start = dram_bank_base[i];
 190                 gd->bd->bi_dram[i].size = dram_bank_size;
 191                 dram_total += dram_bank_size;
 192         }
 193         for (; i < CONFIG_NR_DRAM_BANKS; i++) {
 194                 gd->bd->bi_dram[i].start = 0;
 195                 gd->bd->bi_dram[i].size = 0;
 196         }
 197
 198         if (print) {
 199                 printf("DRAM mask: %08x\n", dram_addr_mask);
 200                 printf("DRAM total %u banks:\n", dram_bank_cnt);
 201                 printf("bank          base-address          size\n");
 202
 203                 if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
 204                         printf("WARNING! UBoot was configured for %u banks,\n"
 205                                 "but %u has been found. "
 206                                 "Supressing extra memory banks\n",
 207                                  CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
 208                         dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
 209                 }
 210
 211                 for (i = 0; i < dram_bank_cnt; i++) {
 212                         printf("  %u             %08x            %08x\n",
 213                                i, dram_bank_base[i], dram_bank_size);
 214                 }
 215                 printf("  ------------------------------------------\n"
 216                         "Total                              %9d\n\n",
 217                         dram_total);
 218         }
 219
 220         return dram_total;
 221 }
 222
 223 int dram_init_banksize(void)
 224 {
 225         dram_init_banksize_int(0);
 226
 227         return 0;
 228 }
 229
 230 /* called in board_init_f (before relocation) */
 231 int dram_init(void)
 232 {
 233         struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
 234         unsigned sec_id = readl(SECURITY_EXTENSIONID);
 235         unsigned chip_id = readl(&syscon->chipid);
 236
 237         printf("CPU: Cirrus Logic ");
 238         switch (sec_id & 0x000001FE) {
 239         case 0x00000008:
 240                 printf("EP9301");
 241                 break;
 242         case 0x00000004:
 243                 printf("EP9307");
 244                 break;
 245         case 0x00000002:
 246                 printf("EP931x");
 247                 break;
 248         case 0x00000000:
 249                 printf("EP9315");
 250                 break;
 251         default:
 252                 printf("<unknown>");
 253                 break;
 254         }
 255
 256         printf(" - Rev. ");
 257         switch (chip_id & 0xF0000000) {
 258         case 0x00000000:
 259                 printf("A");
 260                 break;
 261         case 0x10000000:
 262                 printf("B");
 263                 break;
 264         case 0x20000000:
 265                 printf("C");
 266                 break;
 267         case 0x30000000:
 268                 printf("D0");
 269                 break;
 270         case 0x40000000:
 271                 printf("D1");
 272                 break;
 273         case 0x50000000:
 274                 printf("E0");
 275                 break;
 276         case 0x60000000:
 277                 printf("E1");
 278                 break;
 279         case 0x70000000:
 280                 printf("E2");
 281                 break;
 282         default:
 283                 printf("?");
 284                 break;
 285         }
 286         printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
 287
 288         gd->ram_size = dram_init_banksize_int(1);
 289         return 0;
 290 }