drivers/i2c/qup_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2014, Sony Mobile Communications AB.
   5  * Copyright (c) 2022-2023, Sumit Garg <[email protected]>
   6  *
   7  * Inspired by corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c
   8  */
   9
  10 #include <init.h>
  11 #include <env.h>
  12 #include <log.h>
  13 #include <dm/device_compat.h>
  14 #include <linux/delay.h>
  15 #include <linux/errno.h>
  16 #include <linux/err.h>
  17 #include <linux/compat.h>
  18 #include <linux/bitops.h>
  19 #include <asm/io.h>
  20 #include <i2c.h>
  21 #include <watchdog.h>
  22 #include <fdtdec.h>
  23 #include <clk.h>
  24 #include <reset.h>
  25 #include <asm/arch/gpio.h>
  26 #include <cpu_func.h>
  27 #include <asm/system.h>
  28 #include <asm/gpio.h>
  29 #include <dm.h>
  30 #include <dm/pinctrl.h>
  31
  32 /* QUP Registers */
  33 #define QUP_CONFIG                              0x000
  34 #define QUP_STATE                               0x004
  35 #define QUP_IO_MODE                             0x008
  36 #define QUP_SW_RESET                            0x00c
  37 #define QUP_OPERATIONAL                         0x018
  38 #define QUP_ERROR_FLAGS                         0x01c /* NOT USED */
  39 #define QUP_ERROR_FLAGS_EN                      0x020 /* NOT USED */
  40 #define QUP_TEST_CTRL                           0x024 /* NOT USED */
  41 #define QUP_OPERATIONAL_MASK                    0x028 /* NOT USED */
  42 #define QUP_HW_VERSION                          0x030
  43 #define QUP_MX_OUTPUT_CNT                       0x100
  44 #define QUP_OUT_DEBUG                           0x108 /* NOT USED */
  45 #define QUP_OUT_FIFO_CNT                        0x10C /* NOT USED */
  46 #define QUP_OUT_FIFO_BASE                       0x110
  47 #define QUP_MX_WRITE_CNT                        0x150
  48 #define QUP_MX_INPUT_CNT                        0x200
  49 #define QUP_MX_READ_CNT                         0x208
  50 #define QUP_IN_READ_CUR                         0x20C /* NOT USED */
  51 #define QUP_IN_DEBUG                            0x210 /* NOT USED */
  52 #define QUP_IN_FIFO_CNT                         0x214 /* NOT USED */
  53 #define QUP_IN_FIFO_BASE                        0x218
  54 #define QUP_I2C_CLK_CTL                         0x400
  55 #define QUP_I2C_STATUS                          0x404 /* NOT USED */
  56 #define QUP_I2C_MASTER_GEN                      0x408
  57 #define QUP_I2C_MASTER_BUS_CLR                  0x40C /* NOT USED */
  58
  59 /* QUP States and reset values */
  60 #define QUP_RESET_STATE                         0
  61 #define QUP_RUN_STATE                           1
  62 #define QUP_PAUSE_STATE                         3
  63 #define QUP_STATE_MASK                          3
  64
  65 #define QUP_STATE_VALID                         BIT(2)
  66 #define QUP_I2C_MAST_GEN                        BIT(4)
  67 #define QUP_I2C_FLUSH                           BIT(6)
  68
  69 #define QUP_OPERATIONAL_RESET                   0x000ff0
  70 #define QUP_I2C_STATUS_RESET                    0xfffffc
  71
  72 /* QUP OPERATIONAL FLAGS */
  73 #define QUP_I2C_NACK_FLAG                       BIT(3)
  74 #define QUP_OUT_NOT_EMPTY                       BIT(4)
  75 #define QUP_IN_NOT_EMPTY                        BIT(5)
  76 #define QUP_OUT_FULL                            BIT(6)
  77 #define QUP_OUT_SVC_FLAG                        BIT(8)
  78 #define QUP_IN_SVC_FLAG                         BIT(9)
  79 #define QUP_MX_OUTPUT_DONE                      BIT(10)
  80 #define QUP_MX_INPUT_DONE                       BIT(11)
  81 #define OUT_BLOCK_WRITE_REQ                     BIT(12)
  82 #define IN_BLOCK_READ_REQ                       BIT(13)
  83
  84 /*
  85  * QUP engine acting as I2C controller is referred to as
  86  * I2C mini core, following are related macros.
  87  */
  88 #define QUP_NO_OUTPUT                           BIT(6)
  89 #define QUP_NO_INPUT                            BIT(7)
  90 #define QUP_CLOCK_AUTO_GATE                     BIT(13)
  91 #define QUP_I2C_MINI_CORE                       (2 << 8)
  92 #define QUP_I2C_N_VAL_V2                        7
  93
  94 /* Packing/Unpacking words in FIFOs, and IO modes */
  95 #define QUP_OUTPUT_BLK_MODE                     BIT(10)
  96 #define QUP_OUTPUT_BAM_MODE                     (BIT(10) | BIT(11))
  97 #define QUP_INPUT_BLK_MODE                      BIT(12)
  98 #define QUP_INPUT_BAM_MODE                      (BIT(12) | BIT(13))
  99 #define QUP_BAM_MODE                            (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
 100 #define QUP_BLK_MODE                            (QUP_OUTPUT_BLK_MODE | QUP_INPUT_BLK_MODE)
 101 #define QUP_UNPACK_EN                           BIT(14)
 102 #define QUP_PACK_EN                             BIT(15)
 103
 104 #define QUP_REPACK_EN                           (QUP_UNPACK_EN | QUP_PACK_EN)
 105 #define QUP_V2_TAGS_EN                          1
 106
 107 #define QUP_OUTPUT_BLOCK_SIZE(x)                (((x) >> 0) & 0x03)
 108 #define QUP_OUTPUT_FIFO_SIZE(x)                 (((x) >> 2) & 0x07)
 109 #define QUP_INPUT_BLOCK_SIZE(x)                 (((x) >> 5) & 0x03)
 110 #define QUP_INPUT_FIFO_SIZE(x)                  (((x) >> 7) & 0x07)
 111
 112 /* QUP v2 tags */
 113 #define QUP_TAG_V2_START                        0x81
 114 #define QUP_TAG_V2_DATAWR                       0x82
 115 #define QUP_TAG_V2_DATAWR_STOP                  0x83
 116 #define QUP_TAG_V2_DATARD                       0x85
 117 #define QUP_TAG_V2_DATARD_NACK                  0x86
 118 #define QUP_TAG_V2_DATARD_STOP                  0x87
 119
 120 #define QUP_I2C_MX_CONFIG_DURING_RUN            BIT(31)
 121
 122 /* Minimum transfer timeout for i2c transfers in micro seconds */
 123 #define TOUT_CNT                                (2 * 1000 * 1000)
 124
 125 /* Default values. Use these if FW query fails */
 126 #define DEFAULT_CLK_FREQ                        I2C_SPEED_STANDARD_RATE
 127 #define DEFAULT_SRC_CLK                         19200000
 128
 129 /*
 130  * Max tags length (start, stop and maximum 2 bytes address) for each QUP
 131  * data transfer
 132  */
 133 #define QUP_MAX_TAGS_LEN                        4
 134 /* Max data length for each DATARD tags */
 135 #define RECV_MAX_DATA_LEN                       254
 136 /* TAG length for DATA READ in RX FIFO */
 137 #define READ_RX_TAGS_LEN                        2
 138
 139 struct qup_i2c_priv {
 140         phys_addr_t base;
 141         struct clk core;
 142         struct clk iface;
 143         u32 in_fifo_sz;
 144         u32 out_fifo_sz;
 145         u32 clk_ctl;
 146         u32 config_run;
 147 };
 148
 149 static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
 150 {
 151         return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
 152 }
 153
 154 static int qup_i2c_poll_state_mask(struct qup_i2c_priv *qup,
 155                                    u32 req_state, u32 req_mask)
 156 {
 157         int retries = 1;
 158         u32 state;
 159
 160         /*
 161          * State transition takes 3 AHB clocks cycles + 3 I2C master clock
 162          * cycles. So retry once after a 1uS delay.
 163          */
 164         do {
 165                 state = readl(qup->base + QUP_STATE);
 166
 167                 if (state & QUP_STATE_VALID &&
 168                     (state & req_mask) == req_state)
 169                         return 0;
 170
 171                 udelay(1);
 172         } while (retries--);
 173
 174         return -ETIMEDOUT;
 175 }
 176
 177 static int qup_i2c_poll_state(struct qup_i2c_priv *qup, u32 req_state)
 178 {
 179         return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
 180 }
 181
 182 static int qup_i2c_poll_state_valid(struct qup_i2c_priv *qup)
 183 {
 184         return qup_i2c_poll_state_mask(qup, 0, 0);
 185 }
 186
 187 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_priv *qup)
 188 {
 189         return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
 190 }
 191
 192 static int qup_i2c_change_state(struct qup_i2c_priv *qup, u32 state)
 193 {
 194         if (qup_i2c_poll_state_valid(qup) != 0)
 195                 return -EIO;
 196
 197         writel(state, qup->base + QUP_STATE);
 198
 199         if (qup_i2c_poll_state(qup, state) != 0)
 200                 return -EIO;
 201         return 0;
 202 }
 203
 204 /*
 205  * Function to check wheather Input or Output FIFO
 206  * has data to be serviced
 207  */
 208 static int qup_i2c_check_fifo_status(struct qup_i2c_priv *qup, u32 reg_addr,
 209                                      u32 flags)
 210 {
 211         unsigned long count = TOUT_CNT;
 212         u32 val, status_flag;
 213         int ret = 0;
 214
 215         do {
 216                 val = readl(qup->base + reg_addr);
 217                 status_flag = val & flags;
 218
 219                 if (!count) {
 220                         printf("%s, timeout\n", __func__);
 221                         ret = -ETIMEDOUT;
 222                         break;
 223                 }
 224
 225                 count--;
 226                 udelay(1);
 227         } while (!status_flag);
 228
 229         return ret;
 230 }
 231
 232 /*
 233  * Function to configure Input and Output enable/disable
 234  */
 235 static void qup_i2c_enable_io_config(struct qup_i2c_priv *qup, u32 write_cnt,
 236                                      u32 read_cnt)
 237 {
 238         u32 qup_config = QUP_I2C_MINI_CORE | QUP_I2C_N_VAL_V2;
 239
 240         writel(qup->config_run | write_cnt, qup->base + QUP_MX_WRITE_CNT);
 241
 242         if (read_cnt)
 243                 writel(qup->config_run | read_cnt, qup->base + QUP_MX_READ_CNT);
 244         else
 245                 qup_config |= QUP_NO_INPUT;
 246
 247         writel(qup_config, qup->base + QUP_CONFIG);
 248 }
 249
 250 static unsigned int qup_i2c_read_word(struct qup_i2c_priv *qup)
 251 {
 252         return readl(qup->base + QUP_IN_FIFO_BASE);
 253 }
 254
 255 static void qup_i2c_write_word(struct qup_i2c_priv *qup, u32 word)
 256 {
 257         writel(word, qup->base + QUP_OUT_FIFO_BASE);
 258 }
 259
 260 static int qup_i2c_blsp_read(struct qup_i2c_priv *qup, unsigned int addr,
 261                              bool last, u8 *buffer, unsigned int bytes)
 262 {
 263         unsigned int i, j, word;
 264         int ret = 0;
 265
 266         /* FIFO mode size limitation, for larger size implement block mode */
 267         if (bytes > (qup->in_fifo_sz - READ_RX_TAGS_LEN))
 268                 return -EINVAL;
 269
 270         qup_i2c_enable_io_config(qup, QUP_MAX_TAGS_LEN,
 271                                  bytes + READ_RX_TAGS_LEN);
 272
 273         if (last)
 274                 qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
 275                                         QUP_TAG_V2_DATARD_STOP << 16 |
 276                                         bytes << 24);
 277         else
 278                 qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
 279                                         QUP_TAG_V2_DATARD << 16 | bytes << 24);
 280
 281         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 282         if (ret)
 283                 return ret;
 284
 285         ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_OUT_SVC_FLAG);
 286         if (ret)
 287                 return ret;
 288         writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 289
 290         ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_IN_SVC_FLAG);
 291         if (ret)
 292                 return ret;
 293         writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 294
 295         word = qup_i2c_read_word(qup);
 296         *(buffer++) = (word >> (8 * READ_RX_TAGS_LEN)) & 0xff;
 297         if (bytes > 1)
 298                 *(buffer++) = (word >> (8 * (READ_RX_TAGS_LEN + 1))) & 0xff;
 299
 300         for (i = 2; i < bytes; i += 4) {
 301                 word = qup_i2c_read_word(qup);
 302
 303                 for (j = 0; j < 4; j++) {
 304                         if ((i + j) == bytes)
 305                                 break;
 306                         *buffer = (word >> (j * 8)) & 0xff;
 307                         buffer++;
 308                 }
 309         }
 310
 311         ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 312         return ret;
 313 }
 314
 315 static int qup_i2c_blsp_write(struct qup_i2c_priv *qup, unsigned int addr,
 316                               bool first, bool last, const u8 *buffer,
 317                               unsigned int bytes)
 318 {
 319         unsigned int i;
 320         u32 word = 0;
 321         int ret = 0;
 322
 323         /* FIFO mode size limitation, for larger size implement block mode */
 324         if (bytes > (qup->out_fifo_sz - QUP_MAX_TAGS_LEN))
 325                 return -EINVAL;
 326
 327         qup_i2c_enable_io_config(qup, bytes + QUP_MAX_TAGS_LEN, 0);
 328
 329         if (first) {
 330                 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 331                 if (ret)
 332                         return ret;
 333
 334                 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 335
 336                 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 337                 if (ret)
 338                         return ret;
 339         }
 340
 341         if (last)
 342                 qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
 343                                         QUP_TAG_V2_DATAWR_STOP << 16 |
 344                                         bytes << 24);
 345         else
 346                 qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
 347                                         QUP_TAG_V2_DATAWR << 16 | bytes << 24);
 348
 349         for (i = 0; i < bytes; i++) {
 350                 /* Write the byte of data */
 351                 word |= *buffer << ((i % 4) * 8);
 352                 if ((i % 4) == 3) {
 353                         qup_i2c_write_word(qup, word);
 354                         word = 0;
 355                 }
 356                 buffer++;
 357         }
 358
 359         if ((i % 4) != 0)
 360                 qup_i2c_write_word(qup, word);
 361
 362         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 363         if (ret)
 364                 return ret;
 365
 366         ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_OUT_SVC_FLAG);
 367         if (ret)
 368                 return ret;
 369         writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 370
 371         ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 372         return ret;
 373 }
 374
 375 static void qup_i2c_conf_mode_v2(struct qup_i2c_priv *qup)
 376 {
 377         u32 io_mode = QUP_REPACK_EN;
 378
 379         writel(0, qup->base + QUP_MX_OUTPUT_CNT);
 380         writel(0, qup->base + QUP_MX_INPUT_CNT);
 381
 382         writel(io_mode, qup->base + QUP_IO_MODE);
 383 }
 384
 385 static int qup_i2c_xfer_v2(struct udevice *bus, struct i2c_msg msgs[], int num)
 386 {
 387         struct qup_i2c_priv *qup = dev_get_priv(bus);
 388         int ret, idx = 0;
 389         u32 i2c_addr;
 390
 391         writel(1, qup->base + QUP_SW_RESET);
 392         ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
 393         if (ret)
 394                 goto out;
 395
 396         /* Configure QUP as I2C mini core */
 397         writel(QUP_I2C_MINI_CORE | QUP_I2C_N_VAL_V2 | QUP_NO_INPUT,
 398                qup->base + QUP_CONFIG);
 399         writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
 400
 401         if (qup_i2c_poll_state_i2c_master(qup)) {
 402                 ret = -EIO;
 403                 goto out;
 404         }
 405
 406         qup_i2c_conf_mode_v2(qup);
 407
 408         for (idx = 0; idx < num; idx++) {
 409                 struct i2c_msg *m = &msgs[idx];
 410
 411                 qup->config_run = !idx ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
 412                 i2c_addr = i2c_8bit_addr_from_msg(m);
 413
 414                 if (m->flags & I2C_M_RD)
 415                         ret = qup_i2c_blsp_read(qup, i2c_addr, idx == (num - 1),
 416                                                 m->buf, m->len);
 417                 else
 418                         ret = qup_i2c_blsp_write(qup, i2c_addr, idx == 0,
 419                                                  idx == (num - 1), m->buf,
 420                                                  m->len);
 421                 if (ret)
 422                         break;
 423         }
 424 out:
 425         qup_i2c_change_state(qup, QUP_RESET_STATE);
 426         return ret;
 427 }
 428
 429 static int qup_i2c_enable_clocks(struct udevice *dev, struct qup_i2c_priv *qup)
 430 {
 431         int ret;
 432
 433         ret = clk_enable(&qup->core);
 434         if (ret) {
 435                 dev_err(dev, "clk_enable failed %d\n", ret);
 436                 return ret;
 437         }
 438
 439         ret = clk_enable(&qup->iface);
 440         if (ret) {
 441                 dev_err(dev, "clk_enable failed %d\n", ret);
 442                 return ret;
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int qup_i2c_probe(struct udevice *dev)
 449 {
 450         static const int blk_sizes[] = {4, 16, 32};
 451         struct qup_i2c_priv *qup = dev_get_priv(dev);
 452         u32 io_mode, hw_ver, size, size_idx;
 453         int ret;
 454
 455         qup->base = (phys_addr_t)dev_read_addr_ptr(dev);
 456         if (!qup->base)
 457                 return -EINVAL;
 458
 459         ret = clk_get_by_name(dev, "core", &qup->core);
 460         if (ret) {
 461                 pr_err("clk_get_by_name(core) failed: %d\n", ret);
 462                 return ret;
 463         }
 464         ret = clk_get_by_name(dev, "iface", &qup->iface);
 465         if (ret) {
 466                 pr_err("clk_get_by_name(iface) failed: %d\n", ret);
 467                 return ret;
 468         }
 469         qup_i2c_enable_clocks(dev, qup);
 470
 471         writel(1, qup->base + QUP_SW_RESET);
 472         ret = qup_i2c_poll_state_valid(qup);
 473         if (ret)
 474                 return ret;
 475
 476         hw_ver = readl(qup->base + QUP_HW_VERSION);
 477         dev_dbg(dev, "Revision %x\n", hw_ver);
 478
 479         io_mode = readl(qup->base + QUP_IO_MODE);
 480
 481         /*
 482          * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
 483          * associated with each byte written/received
 484          */
 485         size_idx = QUP_OUTPUT_BLOCK_SIZE(io_mode);
 486         if (size_idx >= ARRAY_SIZE(blk_sizes)) {
 487                 ret = -EIO;
 488                 return ret;
 489         }
 490         size = QUP_OUTPUT_FIFO_SIZE(io_mode);
 491         qup->out_fifo_sz = blk_sizes[size_idx] * (2 << size);
 492
 493         size_idx = QUP_INPUT_BLOCK_SIZE(io_mode);
 494         if (size_idx >= ARRAY_SIZE(blk_sizes)) {
 495                 ret = -EIO;
 496                 return ret;
 497         }
 498         size = QUP_INPUT_FIFO_SIZE(io_mode);
 499         qup->in_fifo_sz = blk_sizes[size_idx] * (2 << size);
 500
 501         dev_dbg(dev, "IN:fifo:%d, OUT:fifo:%d\n", qup->in_fifo_sz,
 502                 qup->out_fifo_sz);
 503
 504         return 0;
 505 }
 506
 507 static int qup_i2c_set_bus_speed(struct udevice *dev, unsigned int clk_freq)
 508 {
 509         struct qup_i2c_priv *qup = dev_get_priv(dev);
 510         unsigned int src_clk_freq;
 511         int fs_div, hs_div;
 512
 513         /* We support frequencies up to FAST Mode Plus (1MHz) */
 514         if (!clk_freq || clk_freq > I2C_SPEED_FAST_PLUS_RATE) {
 515                 dev_err(dev, "clock frequency not supported %d\n", clk_freq);
 516                 return -EINVAL;
 517         }
 518
 519         src_clk_freq = clk_get_rate(&qup->iface);
 520         if ((int)src_clk_freq < 0) {
 521                 src_clk_freq = DEFAULT_SRC_CLK;
 522                 dev_dbg(dev, "using default core freq %d\n", src_clk_freq);
 523         }
 524
 525         dev_dbg(dev, "src_clk_freq %u\n", src_clk_freq);
 526         dev_dbg(dev, "clk_freq     %u\n", clk_freq);
 527
 528         hs_div = 3;
 529         if (clk_freq <= I2C_SPEED_STANDARD_RATE) {
 530                 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
 531                 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
 532         } else {
 533                 /* 33%/66% duty cycle */
 534                 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
 535                 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
 536         }
 537
 538         dev_dbg(dev, "clk_ctl      %u\n", qup->clk_ctl);
 539
 540         return 0;
 541 }
 542
 543 /* Probe to see if a chip is present. */
 544 static int qup_i2c_probe_chip(struct udevice *dev, uint chip_addr,
 545                               uint chip_flags)
 546 {
 547         struct qup_i2c_priv *qup = dev_get_priv(dev);
 548         u32 hw_ver = readl(qup->base + QUP_HW_VERSION);
 549
 550         return hw_ver ? 0 : -1;
 551 }
 552
 553 static const struct dm_i2c_ops qup_i2c_ops = {
 554         .xfer           = qup_i2c_xfer_v2,
 555         .probe_chip     = qup_i2c_probe_chip,
 556         .set_bus_speed  = qup_i2c_set_bus_speed,
 557 };
 558
 559 /*
 560  * Currently this driver only supports v2.x of QUP I2C controller, hence
 561  * functions above are named with a _v2 suffix. So when we have the
 562  * v1.1.1 support added as per the Linux counterpart then it should be easy
 563  * to add corresponding functions named with a _v1 suffix.
 564  */
 565 static const struct udevice_id qup_i2c_ids[] = {
 566         { .compatible = "qcom,i2c-qup-v2.1.1" },
 567         { .compatible = "qcom,i2c-qup-v2.2.1" },
 568         {}
 569 };
 570
 571 U_BOOT_DRIVER(i2c_qup) = {
 572         .name   = "i2c_qup",
 573         .id     = UCLASS_I2C,
 574         .of_match = qup_i2c_ids,
 575         .probe  = qup_i2c_probe,
 576         .priv_auto = sizeof(struct qup_i2c_priv),
 577         .ops    = &qup_i2c_ops,
 578 };