drivers/mtd/nand/raw/cortina_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2020, Cortina Access Inc..
   4  */
   5
   6 #include <common.h>
   7 #include <linux/delay.h>
   8 #include <linux/bitops.h>
   9 #include <linux/sizes.h>
  10 #include <log.h>
  11 #include <asm/io.h>
  12 #include <memalign.h>
  13 #include <nand.h>
  14 #include <dm/device_compat.h>
  15 #include <linux/bug.h>
  16 #include <linux/delay.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/errno.h>
  19 #include <linux/mtd/rawnand.h>
  20 #include <asm/gpio.h>
  21 #include <fdtdec.h>
  22 #include <bouncebuf.h>
  23 #include <dm.h>
  24 #include "cortina_nand.h"
  25
  26 static unsigned int *pread, *pwrite;
  27
  28 static const struct udevice_id cortina_nand_dt_ids[] = {
  29         {
  30          .compatible = "cortina,ca-nand",
  31          },
  32         { /* sentinel */ }
  33 };
  34
  35 static struct nand_ecclayout eccoob;
  36
  37 /* Information about an attached NAND chip */
  38 struct fdt_nand {
  39         int enabled;            /* 1 to enable, 0 to disable */
  40         s32 width;              /* bit width, must be 8 */
  41         u32 nand_ecc_strength;
  42 };
  43
  44 struct nand_drv {
  45         u32 fifo_index;
  46         struct nand_ctlr *reg;
  47         struct dma_global *dma_glb;
  48         struct dma_ssp *dma_nand;
  49         struct tx_descriptor_t *tx_desc;
  50         struct rx_descriptor_t *rx_desc;
  51         struct fdt_nand config;
  52         unsigned int flash_base;
  53 };
  54
  55 struct ca_nand_info {
  56         struct udevice *dev;
  57         struct nand_drv nand_ctrl;
  58         struct nand_chip nand_chip;
  59 };
  60
  61 /**
  62  * Wait for command completion
  63  *
  64  * @param reg   nand_ctlr structure
  65  * @return
  66  *      1 - Command completed
  67  *      0 - Timeout
  68  */
  69 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg, unsigned int mask)
  70 {
  71         unsigned int reg_v = 0;
  72
  73         if (readl_poll_timeout(&reg->flash_flash_access_start, reg_v,
  74                                !(reg_v & mask), (FLASH_LONG_DELAY << 2))) {
  75                 pr_err("Nand CMD timeout!\n");
  76                 return 0;
  77         }
  78
  79         return 1;
  80 }
  81
  82 /**
  83  * Read one byte from the chip
  84  *
  85  * @param mtd   MTD device structure
  86  * @return      data byte
  87  *
  88  * Read function for 8bit bus-width
  89  */
  90 static uint8_t read_byte(struct mtd_info *mtd)
  91 {
  92         struct nand_chip *chip = mtd_to_nand(mtd);
  93         struct nand_drv *info;
  94         u8 ret_v;
  95
  96         info = (struct nand_drv *)nand_get_controller_data(chip);
  97
  98         clrsetbits_le32(&info->reg->flash_flash_access_start, GENMASK(31, 0),
  99                         NFLASH_GO | NFLASH_RD);
 100
 101         if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO))
 102                 printf("%s: Command timeout\n", __func__);
 103
 104         ret_v = readl(&info->reg->flash_nf_data) >> (8 * info->fifo_index++);
 105         info->fifo_index %= 4;
 106
 107         return (uint8_t)ret_v;
 108 }
 109
 110 /**
 111  * Read len bytes from the chip into a buffer
 112  *
 113  * @param mtd   MTD device structure
 114  * @param buf   buffer to store data to
 115  * @param len   number of bytes to read
 116  *
 117  * Read function for 8bit bus-width
 118  */
 119 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 120 {
 121         int i;
 122         unsigned int reg;
 123         struct nand_chip *chip = mtd_to_nand(mtd);
 124         struct nand_drv *info =
 125             (struct nand_drv *)nand_get_controller_data(chip);
 126
 127         for (i = 0; i < len; i++) {
 128                 clrsetbits_le32(&info->reg->flash_flash_access_start,
 129                                 GENMASK(31, 0), NFLASH_GO | NFLASH_RD);
 130
 131                 if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO))
 132                         printf("%s: Command timeout\n", __func__);
 133
 134                 reg = readl(&info->reg->flash_nf_data) >>
 135                     (8 * info->fifo_index++);
 136                 memcpy(buf + i, &reg, 1);
 137                 info->fifo_index %= 4;
 138         }
 139 }
 140
 141 /**
 142  * Check READY pin status to see if it is ready or not
 143  *
 144  * @param mtd   MTD device structure
 145  * @return
 146  *      1 - ready
 147  *      0 - not ready
 148  */
 149 static int nand_dev_ready(struct mtd_info *mtd)
 150 {
 151         struct nand_chip *chip = mtd_to_nand(mtd);
 152         int reg_val;
 153         struct nand_drv *info =
 154             (struct nand_drv *)nand_get_controller_data(chip);
 155
 156         reg_val = readl(&info->reg->flash_status);
 157         if (reg_val & NFLASH_READY)
 158                 return 1;
 159         else
 160                 return 0;
 161 }
 162
 163 /* Dummy implementation: we don't support multiple chips */
 164 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 165 {
 166         switch (chipnr) {
 167         case -1:
 168         case 0:
 169                 break;
 170
 171         default:
 172                 WARN_ON(chipnr);
 173         }
 174 }
 175
 176 int init_nand_dma(struct nand_chip *nand)
 177 {
 178         int i;
 179         struct nand_drv *info =
 180             (struct nand_drv *)nand_get_controller_data(nand);
 181
 182         setbits_le32(&info->dma_glb->dma_glb_dma_lso_ctrl, TX_DMA_ENABLE);
 183         setbits_le32(&info->dma_glb->dma_glb_dma_ssp_rx_ctrl,
 184                      TX_DMA_ENABLE | DMA_CHECK_OWNER);
 185         setbits_le32(&info->dma_glb->dma_glb_dma_ssp_tx_ctrl,
 186                      RX_DMA_ENABLE | DMA_CHECK_OWNER);
 187
 188         info->tx_desc = malloc_cache_aligned((sizeof(struct tx_descriptor_t) *
 189                                               CA_DMA_DESC_NUM));
 190         info->rx_desc = malloc_cache_aligned((sizeof(struct rx_descriptor_t) *
 191                                               CA_DMA_DESC_NUM));
 192
 193         if (!info->rx_desc && info->tx_desc) {
 194                 printf("Fail to alloc DMA descript!\n");
 195                 kfree(info->tx_desc);
 196                 return -ENOMEM;
 197         } else if (info->rx_desc && !info->tx_desc) {
 198                 printf("Fail to alloc DMA descript!\n");
 199                 kfree(info->tx_desc);
 200                 return -ENOMEM;
 201         }
 202
 203         /* set RX DMA base address and depth */
 204         clrsetbits_le32(&info->dma_nand->dma_q_rxq_base_depth,
 205                         GENMASK(31, 4), (uintptr_t)info->rx_desc);
 206         clrsetbits_le32(&info->dma_nand->dma_q_rxq_base_depth,
 207                         GENMASK(3, 0), CA_DMA_DEPTH);
 208
 209         /* set TX DMA base address and depth */
 210         clrsetbits_le32(&info->dma_nand->dma_q_txq_base_depth,
 211                         GENMASK(31, 4), (uintptr_t)info->tx_desc);
 212         clrsetbits_le32(&info->dma_nand->dma_q_txq_base_depth,
 213                         GENMASK(3, 0), CA_DMA_DEPTH);
 214
 215         memset((unsigned char *)info->tx_desc, 0,
 216                (sizeof(struct tx_descriptor_t) * CA_DMA_DESC_NUM));
 217         memset((unsigned char *)info->rx_desc, 0,
 218                (sizeof(struct rx_descriptor_t) * CA_DMA_DESC_NUM));
 219
 220         for (i = 0; i < CA_DMA_DESC_NUM; i++) {
 221                 /* set owner bit as SW */
 222                 info->tx_desc[i].own = 1;
 223                 /* enable Scatter-Gather memory copy */
 224                 info->tx_desc[i].sgm = 0x1;
 225         }
 226
 227         return 0;
 228 }
 229
 230 /**
 231  * Send command to NAND device
 232  *
 233  * @param mtd           MTD device structure
 234  * @param command       the command to be sent
 235  * @param column        the column address for this command, -1 if none
 236  * @param page_addr     the page address for this command, -1 if none
 237  */
 238 static void ca_nand_command(struct mtd_info *mtd, unsigned int command,
 239                             int column, int page_addr)
 240 {
 241         struct nand_chip *chip = mtd_to_nand(mtd);
 242         struct nand_drv *info;
 243         unsigned int reg_v = 0;
 244         u32 cmd = 0, cnt = 0, addr1 = 0, addr2 = 0;
 245         int ret;
 246
 247         info = (struct nand_drv *)nand_get_controller_data(chip);
 248         /*
 249          * Write out the command to the device.
 250          *
 251          * Only command NAND_CMD_RESET or NAND_CMD_READID will come
 252          * here before mtd->writesize is initialized.
 253          */
 254
 255         /* Emulate NAND_CMD_READOOB */
 256         if (command == NAND_CMD_READOOB) {
 257                 assert(mtd->writesize != 0);
 258                 column += mtd->writesize;
 259                 command = NAND_CMD_READ0;
 260         }
 261
 262         /* Reset FIFO before issue new command */
 263         clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
 264                         ECC_RESET_ALL);
 265         ret =
 266             readl_poll_timeout(&info->reg->flash_nf_ecc_reset, reg_v,
 267                                !(reg_v & RESET_NFLASH_FIFO), FLASH_SHORT_DELAY);
 268         if (ret) {
 269                 printf("FIFO reset timeout\n");
 270                 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
 271                                 ECC_RESET_ALL);
 272                 udelay(10);
 273         }
 274
 275         /* Reset FIFO index
 276          * Next read start from flash_nf_data[0]
 277          */
 278         info->fifo_index = 0;
 279
 280         clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(11, 10),
 281                         NFLASH_REG_WIDTH_8);
 282
 283         /*
 284          * Program and erase have their own busy handlers
 285          * status and sequential in needs no delay
 286          */
 287         switch (command) {
 288         case NAND_CMD_READID:
 289                 /* Command */
 290                 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
 291                                 NAND_CMD_READID);
 292                 /* 1 byte CMD cycle */
 293                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0),
 294                                 REG_CMD_COUNT_1TOGO);
 295                 /* 1 byte CMD cycle */
 296                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4),
 297                                 REG_ADDR_COUNT_1);
 298                 /* Data cycle */
 299                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
 300                                 REG_DATA_COUNT_DATA_4);
 301                 /* 0 OOB cycle */
 302                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
 303                                 REG_OOB_COUNT_EMPTY);
 304
 305                 /* addresses */
 306                 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
 307                                 column & ADDR1_MASK2);
 308                 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
 309                                 0);
 310
 311                 /* clear FLASH_NF_ACCESS */
 312                 clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0),
 313                                 DISABLE_AUTO_RESET);
 314
 315                 break;
 316         case NAND_CMD_PARAM:
 317                 /* Command */
 318                 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
 319                                 NAND_CMD_PARAM);
 320                 /* 1 byte CMD cycle */
 321                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0),
 322                                 REG_CMD_COUNT_1TOGO);
 323                 /* 1 byte ADDR cycle */
 324                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4),
 325                                 REG_ADDR_COUNT_1);
 326                 /* Data cycle */
 327                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
 328                                 (SZ_4K - 1) << 8);
 329                 /* 0 OOB cycle */
 330                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
 331                                 REG_OOB_COUNT_EMPTY);
 332
 333                 /* addresses */
 334                 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
 335                                 column & ADDR1_MASK2);
 336                 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
 337                                 0);
 338
 339                 break;
 340         case NAND_CMD_READ0:
 341                 if (chip->chipsize < SZ_32M) {
 342                         cmd = NAND_CMD_READ0;
 343                         cnt = REG_CMD_COUNT_1TOGO | REG_ADDR_COUNT_3;
 344                         addr1 = (((page_addr & ADDR1_MASK0) << 8));
 345                         addr2 = ((page_addr & ADDR2_MASK0) >> 24);
 346                 } else if (chip->chipsize >= SZ_32M &&
 347                            (chip->chipsize <= SZ_128M)) {
 348                         cmd = NAND_CMD_READ0;
 349                         cnt = REG_ADDR_COUNT_4;
 350                         if (mtd->writesize > (REG_DATA_COUNT_512_DATA >> 8)) {
 351                                 cmd |= (NAND_CMD_READSTART << 8);
 352                                 cnt |= REG_CMD_COUNT_2TOGO;
 353                         } else {
 354                                 cnt |= REG_CMD_COUNT_1TOGO;
 355                         }
 356                         addr1 = ((page_addr << 16) | (column & ADDR1_MASK1));
 357                         addr2 = (page_addr >> 16);
 358                 } else {
 359                         cmd = NAND_CMD_READ0 | (NAND_CMD_READSTART << 8);
 360                         cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_5;
 361                         addr1 = ((page_addr << 16) | (column & ADDR1_MASK1));
 362                         addr2 = (page_addr >> 16);
 363                 }
 364
 365                 /* Command */
 366                 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
 367                                 cmd);
 368                 /* CMD & ADDR cycle */
 369                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(7, 0), cnt);
 370                 /* Data cycle */
 371                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
 372                                 (mtd->writesize - 1) << 8);
 373                 /* OOB cycle */
 374                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
 375                                 (mtd->oobsize - 1) << 22);
 376
 377                 /* addresses */
 378                 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
 379                                 addr1);
 380                 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
 381                                 addr2);
 382
 383                 return;
 384         case NAND_CMD_SEQIN:
 385                 if (chip->chipsize < SZ_32M) {
 386                         cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_3;
 387                         addr1 = (((page_addr & ADDR1_MASK0) << 8));
 388                         addr2 = ((page_addr & ADDR2_MASK0) >> 24);
 389                 } else if (chip->chipsize >= SZ_32M &&
 390                            (chip->chipsize <= SZ_128M)) {
 391                         cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_4;
 392                         addr1 = ((page_addr << 16) | (column & ADDR1_MASK1));
 393                         addr2 = (page_addr >> 16);
 394                 } else {
 395                         cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_5;
 396                         addr1 = ((page_addr << 16) | (column & ADDR1_MASK1));
 397                         addr2 = (page_addr >> 16);
 398                 }
 399
 400                 /* Command */
 401                 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
 402                                 NAND_CMD_SEQIN | (NAND_CMD_PAGEPROG << 8));
 403                 /* CMD cycle */
 404                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(7, 0), cnt);
 405                 /* Data cycle */
 406                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
 407                                 (mtd->writesize - 1) << 8);
 408                 /* OOB cycle */
 409                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
 410                                 (mtd->oobsize - 1) << 22);
 411
 412                 /* addresses */
 413                 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
 414                                 addr1);
 415                 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
 416                                 addr2);
 417
 418                 return;
 419         case NAND_CMD_PAGEPROG:
 420                 return;
 421         case NAND_CMD_ERASE1:
 422                 /* Command */
 423                 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
 424                                 NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8));
 425                 /* 2 byte CMD cycle */
 426                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0),
 427                                 REG_CMD_COUNT_2TOGO);
 428                 /* 3 byte ADDR cycle */
 429                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4),
 430                                 REG_ADDR_COUNT_3);
 431                 /* 0 Data cycle */
 432                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
 433                                 REG_DATA_COUNT_EMPTY);
 434                 /* 0 OOB cycle */
 435                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
 436                                 REG_OOB_COUNT_EMPTY);
 437
 438                 /* addresses */
 439                 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
 440                                 page_addr);
 441                 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
 442                                 0);
 443
 444                 /* Issue command */
 445                 clrsetbits_le32(&info->reg->flash_flash_access_start,
 446                                 GENMASK(31, 0), NFLASH_GO | NFLASH_RD);
 447                 break;
 448         case NAND_CMD_ERASE2:
 449                 return;
 450         case NAND_CMD_STATUS:
 451                 /* Command */
 452                 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
 453                                 NAND_CMD_STATUS);
 454                 /* 1 byte CMD cycle */
 455                 clrbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0));
 456                 /* 0 byte Addr cycle */
 457                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4),
 458                                 REG_ADDR_COUNT_EMPTY);
 459                 /* 1 Data cycle */
 460                 clrbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8));
 461                 /* 0 OOB cycle */
 462                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
 463                                 REG_OOB_COUNT_EMPTY);
 464
 465                 break;
 466         case NAND_CMD_RESET:
 467                 /* Command */
 468                 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
 469                                 NAND_CMD_RESET);
 470                 /* 1 byte CMD cycle */
 471                 clrbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0));
 472                 /* 0 byte Addr cycle */
 473                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4),
 474                                 REG_ADDR_COUNT_EMPTY);
 475                 /* 0 Data cycle */
 476                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
 477                                 REG_DATA_COUNT_EMPTY);
 478                 /* 0 OOB cycle */
 479                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
 480                                 REG_OOB_COUNT_EMPTY);
 481
 482                 /* addresses */
 483                 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
 484                                 column & ADDR1_MASK2);
 485                 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
 486                                 0);
 487
 488                 /* Issue command */
 489                 clrsetbits_le32(&info->reg->flash_flash_access_start,
 490                                 GENMASK(31, 0), NFLASH_GO | NFLASH_WT);
 491
 492                 break;
 493         case NAND_CMD_RNDOUT:
 494         default:
 495                 printf("%s: Unsupported command %d\n", __func__, command);
 496                 return;
 497         }
 498
 499         if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO))
 500                 printf("Command 0x%02X timeout\n", command);
 501 }
 502
 503 /**
 504  * Set up NAND bus width and page size
 505  *
 506  * @param info          nand_info structure
 507  * @return 0 if ok, -1 on error
 508  */
 509 static int set_bus_width_page_size(struct mtd_info *mtd)
 510 {
 511         struct nand_chip *chip = mtd_to_nand(mtd);
 512         struct nand_drv *info =
 513             (struct nand_drv *)nand_get_controller_data(chip);
 514
 515         if (info->config.width == SZ_8) {
 516                 clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0),
 517                                 NFLASH_REG_WIDTH_8);
 518         } else if (info->config.width == SZ_16) {
 519                 clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0),
 520                                 NFLASH_REG_WIDTH_16);
 521         } else {
 522                 debug("%s: Unsupported bus width %d\n", __func__,
 523                       info->config.width);
 524                 return -1;
 525         }
 526
 527         if (mtd->writesize == SZ_512) {
 528                 setbits_le32(&info->reg->flash_type, FLASH_TYPE_512);
 529         } else if (mtd->writesize == SZ_2K) {
 530                 setbits_le32(&info->reg->flash_type, FLASH_TYPE_2K);
 531         } else if (mtd->writesize == SZ_4K) {
 532                 setbits_le32(&info->reg->flash_type, FLASH_TYPE_4K);
 533         } else if (mtd->writesize == SZ_8K) {
 534                 setbits_le32(&info->reg->flash_type, FLASH_TYPE_8K);
 535         } else {
 536                 debug("%s: Unsupported page size %d\n", __func__,
 537                       mtd->writesize);
 538                 return -1;
 539         }
 540
 541         return 0;
 542 }
 543
 544 static int ca_do_bch_correction(struct nand_chip *chip,
 545                                 unsigned int err_num, u8 *buff_ptr, int i)
 546 {
 547         struct nand_drv *info =
 548             (struct nand_drv *)nand_get_controller_data(chip);
 549         unsigned int reg_v, err_loc0, err_loc1;
 550         int k, max_bitflips = 0;
 551
 552         for (k = 0; k < (err_num + 1) / 2; k++) {
 553                 reg_v = readl(&info->reg->flash_nf_bch_error_loc01 + k);
 554                 err_loc0 = reg_v & BCH_ERR_LOC_MASK;
 555                 err_loc1 = (reg_v >> 16) & BCH_ERR_LOC_MASK;
 556
 557                 if (err_loc0 / 8 < BCH_DATA_UNIT) {
 558                         printf("pdata[%x]:%x =>", ((i / chip->ecc.bytes) *
 559                                 chip->ecc.size + ((reg_v & 0x1fff) >> 3)),
 560                                 buff_ptr[(reg_v & 0x1fff) >> 3]);
 561
 562                         buff_ptr[err_loc0 / 8] ^=
 563                                 (1 << (reg_v & BCH_CORRECT_LOC_MASK));
 564
 565                         printf("%x\n", buff_ptr[(reg_v & 0x1fff) >> 3]);
 566
 567                         max_bitflips++;
 568                 }
 569
 570                 if (((k + 1) * 2) <= err_num && ((err_loc1 / 8) <
 571                                                  BCH_DATA_UNIT)) {
 572                         printf("pdata[%x]:%x =>", ((i / chip->ecc.bytes) *
 573                                 chip->ecc.size + (((reg_v >> 16) & 0x1fff) >>
 574                                 3)), buff_ptr[((reg_v >> 16) & 0x1fff) >> 3]);
 575
 576                         buff_ptr[err_loc1 / 8] ^= (1 << ((reg_v >> 16) &
 577                                                    BCH_CORRECT_LOC_MASK));
 578
 579                         printf("%x\n", buff_ptr[((reg_v >> 16) & 0x1fff) >> 3]);
 580
 581                         max_bitflips++;
 582                 }
 583         }
 584
 585         return max_bitflips;
 586 }
 587
 588 static int ca_do_bch_decode(struct mtd_info *mtd, struct nand_chip *chip,
 589                             const u8 *buf, int page, unsigned int addr)
 590 {
 591         struct nand_drv *info =
 592             (struct nand_drv *)nand_get_controller_data(chip);
 593         unsigned int reg_v, err_num;
 594         unsigned char *ecc_code = chip->buffers->ecccode;
 595         unsigned char *ecc_end_pos;
 596         int ret, i, j, k, n, step, eccsteps, max_bitflips = 0;
 597         u8 *buff_ptr = (u8 *)buf;
 598
 599         for (i = 0; i < chip->ecc.total; i++)
 600                 ecc_code[i] = chip->oob_poi[eccoob.eccpos[i]];
 601
 602         for (i = 0, eccsteps = chip->ecc.steps; eccsteps;
 603              i += chip->ecc.bytes, eccsteps--) {
 604                 ecc_end_pos = ecc_code + chip->ecc.bytes;
 605
 606                 for (j = 0, k = 0; j < chip->ecc.bytes; j += 4, k++) {
 607                         reg_v = 0;
 608                         for (n = 0; n < 4 && ecc_code != ecc_end_pos;
 609                              ++n, ++ecc_code) {
 610                                 reg_v |= *ecc_code << (8 * n);
 611                         }
 612                         clrsetbits_le32(&info->reg->flash_nf_bch_oob0 + k,
 613                                         GENMASK(31, 0), reg_v);
 614                 }
 615
 616                 /* Clear ECC buffer */
 617                 setbits_le32(&info->reg->flash_nf_ecc_reset, RESET_NFLASH_ECC);
 618                 ret = readl_poll_timeout(&info->reg->flash_nf_ecc_reset, reg_v,
 619                                          !(reg_v & RESET_NFLASH_ECC),
 620                                          FLASH_SHORT_DELAY);
 621                 if (ret)
 622                         pr_err("Reset ECC buffer fail\n");
 623
 624                 clrsetbits_le32(&info->reg->flash_nf_bch_control, GENMASK(8, 8),
 625                                 BCH_DISABLE);
 626
 627                 /* Start BCH */
 628                 step = i / chip->ecc.bytes;
 629                 clrsetbits_le32(&info->reg->flash_nf_bch_control,
 630                                 GENMASK(6, 4), step << 4);
 631                 setbits_le32(&info->reg->flash_nf_bch_control, BCH_ENABLE);
 632                 udelay(10);
 633                 setbits_le32(&info->reg->flash_nf_bch_control, BCH_COMPARE);
 634
 635                 ret = readl_poll_timeout(&info->reg->flash_nf_bch_status, reg_v,
 636                                          (reg_v & BCH_DECO_DONE),
 637                                          FLASH_SHORT_DELAY);
 638                 if (ret)
 639                         pr_err("ECC Decode timeout\n");
 640
 641                 /* Stop compare */
 642                 clrbits_le32(&info->reg->flash_nf_bch_control, BCH_COMPARE);
 643
 644                 reg_v = readl(&info->reg->flash_nf_bch_status);
 645                 err_num = (reg_v >> 8) & BCH_ERR_NUM_MASK;
 646                 reg_v &= BCH_ERR_MASK;
 647
 648                 /* Uncorrectable */
 649                 if (reg_v == BCH_UNCORRECTABLE) {
 650                         max_bitflips =
 651                         nand_check_erased_ecc_chunk(buff_ptr,
 652                                                     chip->ecc.size,
 653                                                     &chip->buffers->ecccode[i],
 654                                                     chip->ecc.bytes,
 655                                                     NULL, 0,
 656                                                     chip->ecc.strength);
 657
 658                         if (max_bitflips) {
 659                                 mtd->ecc_stats.failed++;
 660                                 pr_err("Uncorrectable error\n");
 661                                 pr_err(" Page:%x  step:%d\n", page, step);
 662
 663                                 return -1;
 664                         }
 665                 } else if (reg_v == BCH_CORRECTABLE_ERR) {
 666                         printf("Correctable error(%x)!! addr:%lx\n",
 667                                err_num, (unsigned long)addr - mtd->writesize);
 668                         printf("Dst buf: %p [ColSel:%x ]\n",
 669                                buff_ptr + reg_v * BCH_DATA_UNIT, step);
 670
 671                         max_bitflips =
 672                            ca_do_bch_correction(chip, err_num, buff_ptr, i);
 673                 }
 674
 675                 buff_ptr += BCH_DATA_UNIT;
 676         }
 677
 678         /* Disable BCH */
 679         clrsetbits_le32(&info->reg->flash_nf_bch_control, GENMASK(31, 0),
 680                         BCH_DISABLE);
 681
 682         return max_bitflips;
 683 }
 684
 685 static int ca_do_bch_encode(struct mtd_info *mtd, struct nand_chip *chip,
 686                             int page)
 687 {
 688         struct nand_drv *info;
 689         unsigned int reg_v;
 690         int i, j, n, eccsteps, gen_index;
 691
 692         info = (struct nand_drv *)nand_get_controller_data(chip);
 693
 694         for (i = 0, n = 0, eccsteps = chip->ecc.steps; eccsteps;
 695              i += chip->ecc.bytes, eccsteps--, n++) {
 696                 gen_index = 0;
 697                 for (j = 0; j < chip->ecc.bytes; j += 4, gen_index++) {
 698                         reg_v =
 699                             readl(&info->reg->flash_nf_bch_gen0_0 + gen_index +
 700                                   18 * n);
 701                         chip->oob_poi[eccoob.eccpos[i + j]] = reg_v & OOB_MASK;
 702                         chip->oob_poi[eccoob.eccpos[i + j + 1]] =
 703                             (reg_v >> 8) & OOB_MASK;
 704                         chip->oob_poi[eccoob.eccpos[i + j + 2]] =
 705                             (reg_v >> 16) & OOB_MASK;
 706                         chip->oob_poi[eccoob.eccpos[i + j + 3]] =
 707                             (reg_v >> 24) & OOB_MASK;
 708                 }
 709         }
 710
 711         /* Disable BCH */
 712         clrsetbits_le32(&info->reg->flash_nf_bch_control, GENMASK(8, 8),
 713                         BCH_DISABLE);
 714
 715         return 0;
 716 }
 717
 718 /**
 719  * Page read/write function
 720  *
 721  * @param mtd           mtd info structure
 722  * @param chip          nand chip info structure
 723  * @param buf           data buffer
 724  * @param page          page number
 725  * @param with_ecc      1 to enable ECC, 0 to disable ECC
 726  * @param is_writing    0 for read, 1 for write
 727  * @return              0 when successfully completed
 728  *                      -ETIMEDOUT when command timeout
 729  */
 730 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 731                         const u8 *buf, int page, int with_ecc, int is_writing)
 732 {
 733         unsigned int reg_v, ext_addr, addr, dma_index;
 734         struct tx_descriptor_t *tx_desc;
 735         struct rx_descriptor_t *rx_desc;
 736         struct nand_drv *info =
 737             (struct nand_drv *)nand_get_controller_data(chip);
 738         int ret;
 739
 740         /* reset ecc control */
 741         clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
 742                         RESET_NFLASH_ECC);
 743
 744         /*  flash interrupt */
 745         clrsetbits_le32(&info->reg->flash_flash_interrupt, GENMASK(0, 0),
 746                         REGIRQ_CLEAR);
 747
 748         /* reset ecc control */
 749         clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
 750                         RESET_NFLASH_ECC);
 751
 752         /* Disable TXQ */
 753         clrbits_le32(&info->dma_nand->dma_q_txq_control, GENMASK(0, 0));
 754
 755         /* Clear interrupt */
 756         setbits_le32(&info->dma_nand->dma_q_rxq_coal_interrupt, GENMASK(0, 0));
 757         setbits_le32(&info->dma_nand->dma_q_txq_coal_interrupt, GENMASK(0, 0));
 758
 759         if (with_ecc == 1) {
 760                 switch (info->config.nand_ecc_strength) {
 761                 case ECC_STRENGTH_8:
 762                         reg_v = BCH_ERR_CAP_8;
 763                         break;
 764                 case ECC_STRENGTH_16:
 765                         reg_v = BCH_ERR_CAP_16;
 766                         break;
 767                 case ECC_STRENGTH_24:
 768                         reg_v = BCH_ERR_CAP_24;
 769                         break;
 770                 case ECC_STRENGTH_40:
 771                         reg_v = BCH_ERR_CAP_40;
 772                         break;
 773                 default:
 774                         reg_v = BCH_ERR_CAP_16;
 775                         break;
 776                 }
 777                 reg_v |= BCH_ENABLE;
 778
 779                 /* BCH decode for flash read */
 780                 if (is_writing == 0)
 781                         reg_v |= BCH_DECODE;
 782                 clrsetbits_le32(&info->reg->flash_nf_bch_control,
 783                                 GENMASK(31, 0), reg_v);
 784         } else {
 785                 clrsetbits_le32(&info->reg->flash_nf_bch_control,
 786                                 GENMASK(31, 0), 0);
 787         }
 788
 789         /* Fill Extend address */
 790         ext_addr = ((page << chip->page_shift) / EXT_ADDR_MASK);
 791
 792         clrsetbits_le32(&info->reg->flash_nf_access,
 793                         GENMASK(7, 0), (uintptr_t)ext_addr);
 794
 795         addr = (uintptr_t)((page << chip->page_shift) % EXT_ADDR_MASK);
 796         addr = (uintptr_t)(addr + info->flash_base);
 797
 798         dma_index = readl(&info->dma_nand->dma_q_txq_wptr) & CA_DMA_Q_PTR_MASK;
 799
 800         tx_desc = info->tx_desc;
 801         rx_desc = info->rx_desc;
 802
 803         /* TX/RX descriptor for page data */
 804         tx_desc[dma_index].own = OWN_DMA;
 805         tx_desc[dma_index].buf_len = mtd->writesize;
 806         rx_desc[dma_index].own = OWN_DMA;
 807         rx_desc[dma_index].buf_len = mtd->writesize;
 808         if (is_writing == 0) {
 809                 tx_desc[dma_index].buf_adr = (uintptr_t)addr;
 810                 rx_desc[dma_index].buf_adr = (uintptr_t)(buf);
 811         } else {
 812                 tx_desc[dma_index].buf_adr = (uintptr_t)buf;
 813                 rx_desc[dma_index].buf_adr = (uintptr_t)(addr);
 814         }
 815
 816         dma_index++;
 817         dma_index %= CA_DMA_DESC_NUM;
 818
 819         /* TX/RX descriptor for OOB area */
 820         addr = (uintptr_t)(addr + mtd->writesize);
 821         tx_desc[dma_index].own = OWN_DMA;
 822         tx_desc[dma_index].buf_len = mtd->oobsize;
 823         rx_desc[dma_index].own = OWN_DMA;
 824         rx_desc[dma_index].buf_len = mtd->oobsize;
 825         if (is_writing) {
 826                 tx_desc[dma_index].buf_adr = (uintptr_t)(chip->oob_poi);
 827                 rx_desc[dma_index].buf_adr = (uintptr_t)addr;
 828         } else {
 829                 tx_desc[dma_index].buf_adr = (uintptr_t)addr;
 830                 rx_desc[dma_index].buf_adr = (uintptr_t)(chip->oob_poi);
 831                 dma_index++;
 832                 dma_index %= CA_DMA_DESC_NUM;
 833         }
 834
 835         if (is_writing == 1) {
 836                 clrsetbits_le32(&info->reg->flash_fifo_control, GENMASK(1, 0),
 837                                 FIFO_WRITE);
 838         } else {
 839                 clrsetbits_le32(&info->reg->flash_fifo_control, GENMASK(1, 0),
 840                                 FIFO_READ);
 841         }
 842
 843         /* Start FIFO request */
 844         clrsetbits_le32(&info->reg->flash_flash_access_start, GENMASK(2, 2),
 845                         NFLASH_FIFO_REQ);
 846
 847         /* Update DMA write pointer */
 848         clrsetbits_le32(&info->dma_nand->dma_q_txq_wptr, GENMASK(12, 0),
 849                         dma_index);
 850
 851         /* Start DMA */
 852         clrsetbits_le32(&info->dma_nand->dma_q_txq_control, GENMASK(0, 0),
 853                         TX_DMA_ENABLE);
 854
 855         /* Wait TX DMA done */
 856         ret =
 857             readl_poll_timeout(&info->dma_nand->dma_q_txq_coal_interrupt,
 858                                reg_v, (reg_v & 1), FLASH_LONG_DELAY);
 859         if (ret) {
 860                 pr_err("TX DMA timeout\n");
 861                 return -ETIMEDOUT;
 862         }
 863         /* clear tx interrupt */
 864         setbits_le32(&info->dma_nand->dma_q_txq_coal_interrupt, 1);
 865
 866         /* Wait RX DMA done */
 867         ret =
 868             readl_poll_timeout(&info->dma_nand->dma_q_rxq_coal_interrupt, reg_v,
 869                                (reg_v & 1), FLASH_LONG_DELAY);
 870         if (ret) {
 871                 pr_err("RX DMA timeout\n");
 872                 return -ETIMEDOUT;
 873         }
 874         /* clear rx interrupt */
 875         setbits_le32(&info->dma_nand->dma_q_rxq_coal_interrupt, 1);
 876
 877         /* wait NAND CMD done */
 878         if (is_writing == 0) {
 879                 if (!nand_waitfor_cmd_completion(info->reg, NFLASH_FIFO_REQ))
 880                         printf("%s: Command timeout\n", __func__);
 881         }
 882
 883         /* Update DMA read pointer */
 884         clrsetbits_le32(&info->dma_nand->dma_q_rxq_rptr, GENMASK(12, 0),
 885                         dma_index);
 886
 887         /* ECC correction */
 888         if (with_ecc == 1) {
 889                 ret =
 890                     readl_poll_timeout(&info->reg->flash_nf_bch_status,
 891                                        reg_v, (reg_v & BCH_GEN_DONE),
 892                                        FLASH_LONG_DELAY);
 893
 894                 if (ret) {
 895                         pr_err("BCH_GEN timeout! flash_nf_bch_status=[0x%x]\n",
 896                                reg_v);
 897                         return -ETIMEDOUT;
 898                 }
 899
 900                 if (is_writing == 0)
 901                         ca_do_bch_decode(mtd, chip, buf, page, addr);
 902                 else
 903                         ca_do_bch_encode(mtd, chip, page);
 904         }
 905
 906         if (is_writing) {
 907                 dma_index++;
 908                 dma_index %= CA_DMA_DESC_NUM;
 909
 910                 /* Update DMA R/W pointer */
 911                 clrsetbits_le32(&info->dma_nand->dma_q_txq_wptr, GENMASK(12, 0),
 912                                 dma_index);
 913
 914                 /* Wait TX DMA done */
 915                 ret =
 916                    readl_poll_timeout(&info->dma_nand->dma_q_txq_coal_interrupt,
 917                                       reg_v, (reg_v & 1), FLASH_LONG_DELAY);
 918                 if (ret) {
 919                         pr_err("TX DMA timeout\n");
 920                         return -ETIMEDOUT;
 921                 }
 922                 /* clear tx interrupt */
 923                 setbits_le32(&info->dma_nand->dma_q_txq_coal_interrupt, 1);
 924
 925                 /* Wait RX DMA done */
 926                 ret =
 927                    readl_poll_timeout(&info->dma_nand->dma_q_rxq_coal_interrupt,
 928                                       reg_v, (reg_v & 1), FLASH_LONG_DELAY);
 929                 if (ret) {
 930                         pr_err("RX DMA timeout\n");
 931                         return -ETIMEDOUT;
 932                 }
 933                 /* clear rx interrupt */
 934                 setbits_le32(&info->dma_nand->dma_q_rxq_coal_interrupt, 1);
 935
 936                 /* wait NAND CMD done */
 937                 if (!nand_waitfor_cmd_completion(info->reg, NFLASH_FIFO_REQ))
 938                         printf("%s: Command timeout\n", __func__);
 939
 940                 /* Update DMA R/W pointer */
 941                 clrsetbits_le32(&info->dma_nand->dma_q_rxq_rptr, GENMASK(12, 0),
 942                                 dma_index);
 943         }
 944
 945         return 0;
 946 }
 947
 948 /**
 949  * Hardware ecc based page read function
 950  *
 951  * @param mtd   mtd info structure
 952  * @param chip  nand chip info structure
 953  * @param buf   buffer to store read data
 954  * @param page  page number to read
 955  * @return      0 when successfully completed
 956  *              -ETIMEDOUT when command timeout
 957  */
 958 static int nand_read_page_hwecc(struct mtd_info *mtd,
 959                                 struct nand_chip *chip, uint8_t *buf,
 960                                 int oob_required, int page)
 961 {
 962         struct nand_drv *info =
 963             (struct nand_drv *)nand_get_controller_data(chip);
 964         int ret;
 965
 966         ret = nand_rw_page(mtd, chip, buf, page, 1, 0);
 967         if (ret)
 968                 return ret;
 969
 970         /* Reset FIFO */
 971         clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
 972                         ECC_RESET_ALL);
 973
 974         return 0;
 975 }
 976
 977 /**
 978  * Hardware ecc based page write function
 979  *
 980  * @param mtd   mtd info structure
 981  * @param chip  nand chip info structure
 982  * @param buf   data buffer
 983  * @return      0 when successfully completed
 984  *              -ETIMEDOUT when command timeout
 985  */
 986 static int nand_write_page_hwecc(struct mtd_info *mtd,
 987                                  struct nand_chip *chip, const uint8_t *buf,
 988                                  int oob_required, int page)
 989 {
 990         struct nand_drv *info =
 991             (struct nand_drv *)nand_get_controller_data(chip);
 992         int ret;
 993
 994         ret = nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
 995         if (ret)
 996                 return ret;
 997
 998         /* Reset FIFO */
 999         clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
1000                         ECC_RESET_ALL);
1001
1002         return 0;
1003 }
1004
1005 /**
1006  * Read raw page data without ecc
1007  *
1008  * @param mtd   mtd info structure
1009  * @param chip  nand chip info structure
1010  * @param buf   buffer to store read data
1011  * @param page  page number to read
1012  * @return      0 when successfully completed
1013  *              -ETIMEDOUT when command timeout
1014  */
1015 static int nand_read_page_raw(struct mtd_info *mtd,
1016                               struct nand_chip *chip, uint8_t *buf,
1017                               int oob_required, int page)
1018 {
1019         struct nand_drv *info =
1020             (struct nand_drv *)nand_get_controller_data(chip);
1021         int ret;
1022
1023         ret = nand_rw_page(mtd, chip, buf, page, 0, 0);
1024         if (ret)
1025                 return ret;
1026
1027         /* Reset FIFO */
1028         clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
1029                         ECC_RESET_ALL);
1030
1031         return 0;
1032 }
1033
1034 /**
1035  * Raw page write function
1036  *
1037  * @param mtd   mtd info structure
1038  * @param chip  nand chip info structure
1039  * @param buf   data buffer
1040  * @return      0 when successfully completed
1041  *              -ETIMEDOUT when command timeout
1042  */
1043 static int nand_write_page_raw(struct mtd_info *mtd,
1044                                struct nand_chip *chip, const uint8_t *buf,
1045                                int oob_required, int page)
1046 {
1047         struct nand_drv *info =
1048             (struct nand_drv *)nand_get_controller_data(chip);
1049         int ret;
1050
1051         ret = nand_rw_page(mtd, chip, buf, page, 0, 1);
1052         if (ret)
1053                 return ret;
1054
1055         /* Reset FIFO */
1056         clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
1057                         ECC_RESET_ALL);
1058
1059         return 0;
1060 }
1061
1062 /**
1063  * OOB data read/write function
1064  *
1065  * @param mtd           mtd info structure
1066  * @param chip          nand chip info structure
1067  * @param page          page number to read
1068  * @param with_ecc      1 to enable ECC, 0 to disable ECC
1069  * @param is_writing    0 for read, 1 for write
1070  * @return              0 when successfully completed
1071  *                      -ETIMEDOUT when command timeout
1072  */
1073 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
1074                        int page, int with_ecc, int is_writing)
1075 {
1076         struct nand_drv *info =
1077             (struct nand_drv *)nand_get_controller_data(chip);
1078         u32 reg_val;
1079         int rw_index;
1080
1081         if (is_writing) {
1082                 reg_val = NFLASH_GO | NFLASH_WT;
1083                 pwrite = (unsigned int *)chip->oob_poi;
1084         } else {
1085                 reg_val = NFLASH_GO | NFLASH_RD;
1086                 pread = (unsigned int *)chip->oob_poi;
1087         }
1088
1089         for (rw_index = 0; rw_index < mtd->oobsize / 4; rw_index++) {
1090                 clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0),
1091                                 NFLASH_REG_WIDTH_32);
1092                 if (is_writing)
1093                         clrsetbits_le32(&info->reg->flash_nf_data,
1094                                         GENMASK(31, 0), pwrite[rw_index]);
1095
1096                 clrsetbits_le32(&info->reg->flash_flash_access_start,
1097                                 GENMASK(11, 10), reg_val);
1098
1099                 if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO))
1100                         printf("%s: Command timeout\n", __func__);
1101
1102                 if (!is_writing)
1103                         pread[rw_index] = readl(&info->reg->flash_nf_data);
1104         }
1105         return 0;
1106 }
1107
1108 /**
1109  * OOB data read function
1110  *
1111  * @param mtd           mtd info structure
1112  * @param chip          nand chip info structure
1113  * @param page          page number to read
1114  */
1115 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
1116 {
1117         struct nand_drv *info =
1118             (struct nand_drv *)nand_get_controller_data(chip);
1119         int ret;
1120
1121         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1122         if (mtd->writesize <= (REG_DATA_COUNT_512_DATA >> 8))
1123                 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(7, 0),
1124                                 NAND_CMD_READOOB);
1125         ret = nand_rw_oob(mtd, chip, page, 0, 0);
1126
1127         /* Reset FIFO */
1128         clrsetbits_le32(&info->reg->flash_nf_ecc_reset,
1129                         GENMASK(31, 0), ECC_RESET_ALL);
1130
1131         return ret;
1132 }
1133
1134 /**
1135  * OOB data write function
1136  *
1137  * @param mtd   mtd info structure
1138  * @param chip  nand chip info structure
1139  * @param page  page number to write
1140  * @return      0 when successfully completed
1141  *              -ETIMEDOUT when command timeout
1142  */
1143 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1144                           int page)
1145 {
1146         struct nand_drv *info =
1147             (struct nand_drv *)nand_get_controller_data(chip);
1148         int ret;
1149
1150         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1151         if (mtd->writesize <= (REG_DATA_COUNT_512_DATA >> 8)) {
1152                 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
1153                                 NAND_CMD_READOOB | (NAND_CMD_SEQIN << 8) |
1154                                 (NAND_CMD_PAGEPROG << 16));
1155                 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0),
1156                                 REG_CMD_COUNT_3TOGO);
1157         }
1158         ret = nand_rw_oob(mtd, chip, page, 1, 1);
1159
1160         /* Reset FIFO */
1161         clrsetbits_le32(&info->reg->flash_nf_ecc_reset,
1162                         GENMASK(31, 0), ECC_RESET_ALL);
1163
1164         return ret;
1165 }
1166
1167 /**
1168  * Decode NAND parameters from the device tree
1169  *
1170  * @param dev           Driver model device
1171  * @param config        Device tree NAND configuration
1172  */
1173 static int fdt_decode_nand(struct udevice *dev, struct nand_drv *info)
1174 {
1175         int ecc_strength;
1176
1177         info->reg = (struct nand_ctlr *)dev_read_addr(dev);
1178         info->dma_glb = (struct dma_global *)dev_read_addr_index(dev, 1);
1179         info->dma_nand = (struct dma_ssp *)dev_read_addr_index(dev, 2);
1180         info->config.enabled = dev_read_enabled(dev);
1181         ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 16);
1182         info->flash_base =
1183             dev_read_u32_default(dev, "nand_flash_base_addr", NAND_BASE_ADDR);
1184
1185         switch (ecc_strength) {
1186         case ECC_STRENGTH_8:
1187                 info->config.nand_ecc_strength = ECC_STRENGTH_8;
1188                 break;
1189         case ECC_STRENGTH_16:
1190                 info->config.nand_ecc_strength = ECC_STRENGTH_16;
1191                 break;
1192         case ECC_STRENGTH_24:
1193                 info->config.nand_ecc_strength = ECC_STRENGTH_24;
1194                 break;
1195         case ECC_STRENGTH_40:
1196                 info->config.nand_ecc_strength = ECC_STRENGTH_40;
1197                 break;
1198         default:
1199                 info->config.nand_ecc_strength = ECC_STRENGTH_16;
1200         }
1201
1202         return 0;
1203 }
1204
1205 /**
1206  * config flash type
1207  *
1208  * @param chip  nand chip info structure
1209  */
1210 static void nand_config_flash_type(struct nand_chip *nand)
1211 {
1212         struct nand_drv *info =
1213             (struct nand_drv *)nand_get_controller_data(nand);
1214         struct mtd_info *mtd = nand_to_mtd(nand);
1215
1216         switch (mtd->writesize) {
1217         case WRITE_SIZE_512:
1218                 clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0),
1219                                 FLASH_PIN | FLASH_TYPE_512);
1220                 break;
1221         case WRITE_SIZE_2048:
1222                 clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0),
1223                                 FLASH_PIN | FLASH_TYPE_2K);
1224                 break;
1225         case WRITE_SIZE_4096:
1226                 clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0),
1227                                 FLASH_PIN | FLASH_TYPE_4K);
1228                 break;
1229         case WRITE_SIZE_8192:
1230                 clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0),
1231                                 FLASH_PIN | FLASH_TYPE_8K);
1232                 break;
1233         default:
1234                 pr_err("Unsupported page size(0x%x)!", nand->ecc.size);
1235         }
1236 }
1237
1238 /**
1239  * config oob layout
1240  *
1241  * @param chip  nand chip info structure
1242  * @return      0 when successfully completed
1243  *              -EINVAL when ECC bytes exceed OOB size
1244  */
1245 static int nand_config_oob_layout(struct nand_chip *nand)
1246 {
1247         int i, ecc_start_offset;
1248         struct mtd_info *mtd = nand_to_mtd(nand);
1249
1250         /* Calculate byte count for ECC */
1251         eccoob.eccbytes = mtd->writesize / nand->ecc.size * nand->ecc.bytes;
1252
1253         if (mtd->oobsize < eccoob.eccbytes) {
1254                 pr_err("Spare area(%d) too small for BCH%d\n", nand->ecc.bytes,
1255                        nand->ecc.strength / 8);
1256                 pr_err("page_sz: %d\n", nand->ecc.size);
1257                 pr_err("oob_sz: %d\n", nand->ecc.bytes);
1258                 return -EINVAL;
1259         }
1260
1261         /* Update OOB layout */
1262         ecc_start_offset = mtd->oobsize - eccoob.eccbytes;
1263         memset(eccoob.eccpos, 0, sizeof(eccoob.eccpos));
1264         for (i = 0; i < eccoob.eccbytes; ++i)
1265                 eccoob.eccpos[i] = i + ecc_start_offset;
1266
1267         /* Unused spare area
1268          * OOB[0] is bad block marker.
1269          * Extra two byte is reserved as
1270          * erase marker just right before ECC code.
1271          */
1272         eccoob.oobavail = nand->ecc.bytes - eccoob.eccbytes - 2;
1273         eccoob.oobfree[0].offset = 2;
1274         eccoob.oobfree[0].length =
1275             mtd->oobsize - eccoob.eccbytes - eccoob.oobfree[0].offset - 1;
1276
1277         return 0;
1278 }
1279
1280 static int ca_nand_probe(struct udevice *dev)
1281 {
1282         struct ca_nand_info *ca_nand = dev_get_priv(dev);
1283         struct nand_chip *nand = &ca_nand->nand_chip;
1284         struct nand_drv *info = &ca_nand->nand_ctrl;
1285         struct fdt_nand *config = &info->config;
1286         struct mtd_info *our_mtd;
1287         int ret;
1288
1289         if (fdt_decode_nand(dev, info)) {
1290                 printf("Could not decode nand-flash in device tree\n");
1291                 return -1;
1292         }
1293         if (!config->enabled)
1294                 return -1;
1295
1296         nand->ecc.mode = NAND_ECC_HW;
1297         nand->ecc.layout = &eccoob;
1298
1299         nand->cmdfunc = ca_nand_command;
1300         nand->read_byte = read_byte;
1301         nand->read_buf = read_buf;
1302         nand->ecc.read_page = nand_read_page_hwecc;
1303         nand->ecc.write_page = nand_write_page_hwecc;
1304         nand->ecc.read_page_raw = nand_read_page_raw;
1305         nand->ecc.write_page_raw = nand_write_page_raw;
1306         nand->ecc.read_oob = nand_read_oob;
1307         nand->ecc.write_oob = nand_write_oob;
1308         nand->ecc.strength = config->nand_ecc_strength;
1309         nand->select_chip = nand_select_chip;
1310         nand->dev_ready = nand_dev_ready;
1311         nand_set_controller_data(nand, &ca_nand->nand_ctrl);
1312
1313         /* Disable subpage writes as we do not provide ecc->hwctl */
1314         nand->options |= NAND_NO_SUBPAGE_WRITE | NAND_SKIP_BBTSCAN;
1315
1316         /* Configure flash type as P-NAND */
1317         clrsetbits_le32(&info->reg->flash_type, FLASH_PIN,
1318                         FLASH_TYPE_4K | FLASH_SIZE_436OOB);
1319         config->width = FLASH_WIDTH;
1320
1321         our_mtd = nand_to_mtd(nand);
1322         ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1323         if (ret)
1324                 return ret;
1325
1326         nand->ecc.size = BCH_DATA_UNIT;
1327         nand->ecc.bytes = BCH_GF_PARAM_M * (nand->ecc.strength / 8);
1328
1329         /* Reconfig flash type according to ONFI */
1330         nand_config_flash_type(nand);
1331
1332         ret = set_bus_width_page_size(our_mtd);
1333         if (ret)
1334                 return ret;
1335
1336         /* Set the bad block position */
1337         nand->badblockpos =
1338             our_mtd->writesize >
1339             512 ? NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
1340
1341         /* Arrange OOB layout */
1342         ret = nand_config_oob_layout(nand);
1343         if (ret)
1344                 return ret;
1345
1346         /* Init DMA descriptor ring */
1347         ret = init_nand_dma(nand);
1348         if (ret)
1349                 return ret;
1350
1351         ret = nand_scan_tail(our_mtd);
1352         if (ret)
1353                 return ret;
1354
1355         ret = nand_register(0, our_mtd);
1356         if (ret) {
1357                 dev_err(dev, "Failed to register MTD: %d\n", ret);
1358                 return ret;
1359         }
1360
1361         ret = set_bus_width_page_size(our_mtd);
1362         if (ret)
1363                 return ret;
1364
1365         printf("P-NAND    : %s\n", our_mtd->name);
1366         printf("Chip  Size: %lldMB\n", nand->chipsize / (1024 * 1024));
1367         printf("Block Size: %dKB\n", our_mtd->erasesize / 1024);
1368         printf("Page  Size: %dB\n", our_mtd->writesize);
1369         printf("OOB   Size: %dB\n", our_mtd->oobsize);
1370
1371         return 0;
1372 }
1373
1374 U_BOOT_DRIVER(cortina_nand) = {
1375         .name = "CA-PNAND",
1376         .id = UCLASS_MTD,
1377         .of_match = cortina_nand_dt_ids,
1378         .probe = ca_nand_probe,
1379         .priv_auto = sizeof(struct ca_nand_info),
1380 };
1381
1382 void board_nand_init(void)
1383 {
1384         struct udevice *dev;
1385         int ret;
1386
1387         ret = uclass_get_device_by_driver(UCLASS_MTD,
1388                                           DM_DRIVER_GET(cortina_nand), &dev);
1389         if (ret && ret != -ENODEV)
1390                 pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
1391 }