arch/arm/dts/socfpga_stratix10.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Intel Corporation
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         compatible = "altr,socfpga-stratix10";
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a53", "arm,armv8";
  21                         device_type = "cpu";
  22                         enable-method = "psci";
  23                         reg = <0x0>;
  24                 };
  25
  26                 cpu1: cpu@1 {
  27                         compatible = "arm,cortex-a53", "arm,armv8";
  28                         device_type = "cpu";
  29                         enable-method = "psci";
  30                         reg = <0x1>;
  31                 };
  32
  33                 cpu2: cpu@2 {
  34                         compatible = "arm,cortex-a53", "arm,armv8";
  35                         device_type = "cpu";
  36                         enable-method = "psci";
  37                         reg = <0x2>;
  38                 };
  39
  40                 cpu3: cpu@3 {
  41                         compatible = "arm,cortex-a53", "arm,armv8";
  42                         device_type = "cpu";
  43                         enable-method = "psci";
  44                         reg = <0x3>;
  45                 };
  46         };
  47
  48         pmu {
  49                 compatible = "arm,armv8-pmuv3";
  50                 interrupts = <0 120 8>,
  51                              <0 121 8>,
  52                              <0 122 8>,
  53                              <0 123 8>;
  54                 interrupt-affinity = <&cpu0>,
  55                                      <&cpu1>,
  56                                      <&cpu2>,
  57                                      <&cpu3>;
  58                 interrupt-parent = <&intc>;
  59         };
  60
  61         psci {
  62                 compatible = "arm,psci-0.2";
  63                 method = "smc";
  64         };
  65
  66         intc: intc@fffc1000 {
  67                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  68                 #interrupt-cells = <3>;
  69                 interrupt-controller;
  70                 reg = <0x0 0xfffc1000 0x0 0x1000>,
  71                       <0x0 0xfffc2000 0x0 0x2000>,
  72                       <0x0 0xfffc4000 0x0 0x2000>,
  73                       <0x0 0xfffc6000 0x0 0x2000>;
  74         };
  75
  76         soc {
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 compatible = "simple-bus";
  80                 device_type = "soc";
  81                 interrupt-parent = <&intc>;
  82                 ranges = <0 0 0 0xffffffff>;
  83
  84                 clkmgr@ffd1000 {
  85                         compatible = "altr,clk-mgr";
  86                         reg = <0xffd10000 0x1000>;
  87                 };
  88
  89                 gmac0: ethernet@ff800000 {
  90                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
  91                         reg = <0xff800000 0x2000>;
  92                         interrupts = <0 90 4>;
  93                         interrupt-names = "macirq";
  94                         mac-address = [00 00 00 00 00 00];
  95                         resets = <&rst EMAC0_RESET>;
  96                         reset-names = "stmmaceth";
  97                         status = "disabled";
  98                 };
  99
 100                 gmac1: ethernet@ff802000 {
 101                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 102                         reg = <0xff802000 0x2000>;
 103                         interrupts = <0 91 4>;
 104                         interrupt-names = "macirq";
 105                         mac-address = [00 00 00 00 00 00];
 106                         resets = <&rst EMAC1_RESET>;
 107                         reset-names = "stmmaceth";
 108                         status = "disabled";
 109                 };
 110
 111                 gmac2: ethernet@ff804000 {
 112                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 113                         reg = <0xff804000 0x2000>;
 114                         interrupts = <0 92 4>;
 115                         interrupt-names = "macirq";
 116                         mac-address = [00 00 00 00 00 00];
 117                         resets = <&rst EMAC2_RESET>;
 118                         reset-names = "stmmaceth";
 119                         status = "disabled";
 120                 };
 121
 122                 gpio0: gpio@ffc03200 {
 123                         #address-cells = <1>;
 124                         #size-cells = <0>;
 125                         compatible = "snps,dw-apb-gpio";
 126                         reg = <0xffc03200 0x100>;
 127                         resets = <&rst GPIO0_RESET>;
 128                         status = "disabled";
 129
 130                         porta: gpio-controller@0 {
 131                                 compatible = "snps,dw-apb-gpio-port";
 132                                 gpio-controller;
 133                                 #gpio-cells = <2>;
 134                                 snps,nr-gpios = <24>;
 135                                 reg = <0>;
 136                                 interrupt-controller;
 137                                 #interrupt-cells = <2>;
 138                                 interrupts = <0 110 4>;
 139                         };
 140                 };
 141
 142                 gpio1: gpio@ffc03300 {
 143                         #address-cells = <1>;
 144                         #size-cells = <0>;
 145                         compatible = "snps,dw-apb-gpio";
 146                         reg = <0xffc03300 0x100>;
 147                         resets = <&rst GPIO1_RESET>;
 148                         status = "disabled";
 149
 150                         portb: gpio-controller@0 {
 151                                 compatible = "snps,dw-apb-gpio-port";
 152                                 gpio-controller;
 153                                 #gpio-cells = <2>;
 154                                 snps,nr-gpios = <24>;
 155                                 reg = <0>;
 156                                 interrupt-controller;
 157                                 #interrupt-cells = <2>;
 158                                 interrupts = <0 111 4>;
 159                         };
 160                 };
 161
 162                 i2c0: i2c@ffc02800 {
 163                         #address-cells = <1>;
 164                         #size-cells = <0>;
 165                         compatible = "snps,designware-i2c";
 166                         reg = <0xffc02800 0x100>;
 167                         interrupts = <0 103 4>;
 168                         resets = <&rst I2C0_RESET>;
 169                         status = "disabled";
 170                 };
 171
 172                 i2c1: i2c@ffc02900 {
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         compatible = "snps,designware-i2c";
 176                         reg = <0xffc02900 0x100>;
 177                         interrupts = <0 104 4>;
 178                         resets = <&rst I2C1_RESET>;
 179                         status = "disabled";
 180                 };
 181
 182                 i2c2: i2c@ffc02a00 {
 183                         #address-cells = <1>;
 184                         #size-cells = <0>;
 185                         compatible = "snps,designware-i2c";
 186                         reg = <0xffc02a00 0x100>;
 187                         interrupts = <0 105 4>;
 188                         resets = <&rst I2C2_RESET>;
 189                         status = "disabled";
 190                 };
 191
 192                 i2c3: i2c@ffc02b00 {
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         compatible = "snps,designware-i2c";
 196                         reg = <0xffc02b00 0x100>;
 197                         interrupts = <0 106 4>;
 198                         resets = <&rst I2C3_RESET>;
 199                         status = "disabled";
 200                 };
 201
 202                 i2c4: i2c@ffc02c00 {
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         compatible = "snps,designware-i2c";
 206                         reg = <0xffc02c00 0x100>;
 207                         interrupts = <0 107 4>;
 208                         resets = <&rst I2C4_RESET>;
 209                         status = "disabled";
 210                 };
 211
 212                 mmc: dwmmc0@ff808000 {
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215                         compatible = "altr,socfpga-dw-mshc";
 216                         reg = <0xff808000 0x1000>;
 217                         interrupts = <0 96 4>;
 218                         fifo-depth = <0x400>;
 219                         resets = <&rst SDMMC_RESET>;
 220                         reset-names = "reset";
 221                         status = "disabled";
 222                 };
 223
 224                 ocram: sram@ffe00000 {
 225                         compatible = "mmio-sram";
 226                         reg = <0xffe00000 0x100000>;
 227                 };
 228
 229                 rst: rstmgr@ffd11000 {
 230                         #reset-cells = <1>;
 231                         compatible = "altr,rst-mgr";
 232                         reg = <0xffd11000 0x1000>;
 233                         altr,modrst-offset = <0x20>;
 234                 };
 235
 236                 spi0: spi@ffda4000 {
 237                         compatible = "snps,dw-apb-ssi";
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         reg = <0xffda4000 0x1000>;
 241                         interrupts = <0 99 4>;
 242                         resets = <&rst SPIM0_RESET>;
 243                         reg-io-width = <4>;
 244                         num-chipselect = <4>;
 245                         bus-num = <0>;
 246                         status = "disabled";
 247                 };
 248
 249                 spi1: spi@ffda5000 {
 250                         compatible = "snps,dw-apb-ssi";
 251                         #address-cells = <1>;
 252                         #size-cells = <0>;
 253                         reg = <0xffda5000 0x1000>;
 254                         interrupts = <0 100 4>;
 255                         resets = <&rst SPIM1_RESET>;
 256                         reg-io-width = <4>;
 257                         num-chipselect = <4>;
 258                         bus-num = <0>;
 259                         status = "disabled";
 260                 };
 261
 262                 sysmgr: sysmgr@ffd12000 {
 263                         compatible = "altr,sys-mgr", "syscon";
 264                         reg = <0xffd12000 0x1000>;
 265                 };
 266
 267                 /* Local timer */
 268                 timer {
 269                         compatible = "arm,armv8-timer";
 270                         interrupts = <1 13 0xf08>,
 271                                      <1 14 0xf08>,
 272                                      <1 11 0xf08>,
 273                                      <1 10 0xf08>;
 274                 };
 275
 276                 timer0: timer0@ffc03000 {
 277                         compatible = "snps,dw-apb-timer";
 278                         interrupts = <0 113 4>;
 279                         reg = <0xffc03000 0x100>;
 280                 };
 281
 282                 timer1: timer1@ffc03100 {
 283                         compatible = "snps,dw-apb-timer";
 284                         interrupts = <0 114 4>;
 285                         reg = <0xffc03100 0x100>;
 286                 };
 287
 288                 timer2: timer2@ffd00000 {
 289                         compatible = "snps,dw-apb-timer";
 290                         interrupts = <0 115 4>;
 291                         reg = <0xffd00000 0x100>;
 292                 };
 293
 294                 timer3: timer3@ffd00100 {
 295                         compatible = "snps,dw-apb-timer";
 296                         interrupts = <0 116 4>;
 297                         reg = <0xffd00100 0x100>;
 298                 };
 299
 300                 uart0: serial0@ffc02000 {
 301                         compatible = "snps,dw-apb-uart";
 302                         reg = <0xffc02000 0x100>;
 303                         interrupts = <0 108 4>;
 304                         reg-shift = <2>;
 305                         reg-io-width = <4>;
 306                         resets = <&rst UART0_RESET>;
 307                         status = "disabled";
 308                 };
 309
 310                 uart1: serial1@ffc02100 {
 311                         compatible = "snps,dw-apb-uart";
 312                         reg = <0xffc02100 0x100>;
 313                         interrupts = <0 109 4>;
 314                         reg-shift = <2>;
 315                         reg-io-width = <4>;
 316                         resets = <&rst UART1_RESET>;
 317                         status = "disabled";
 318                 };
 319
 320                 usbphy0: usbphy@0 {
 321                         #phy-cells = <0>;
 322                         compatible = "usb-nop-xceiv";
 323                         status = "okay";
 324                 };
 325
 326                 usb0: usb@ffb00000 {
 327                         compatible = "snps,dwc2";
 328                         reg = <0xffb00000 0x40000>;
 329                         interrupts = <0 93 4>;
 330                         phys = <&usbphy0>;
 331                         phy-names = "usb2-phy";
 332                         resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
 333                         reset-names = "dwc2", "dwc2-ecc";
 334                         status = "disabled";
 335                 };
 336
 337                 usb1: usb@ffb40000 {
 338                         compatible = "snps,dwc2";
 339                         reg = <0xffb40000 0x40000>;
 340                         interrupts = <0 94 4>;
 341                         phys = <&usbphy0>;
 342                         phy-names = "usb2-phy";
 343                         resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
 344                         reset-names = "dwc2", "dwc2-ecc";
 345                         status = "disabled";
 346                 };
 347
 348                 watchdog0: watchdog@ffd00200 {
 349                         compatible = "snps,dw-wdt";
 350                         reg = <0xffd00200 0x100>;
 351                         interrupts = <0 117 4>;
 352                         resets = <&rst WATCHDOG0_RESET>;
 353                         status = "disabled";
 354                 };
 355
 356                 watchdog1: watchdog@ffd00300 {
 357                         compatible = "snps,dw-wdt";
 358                         reg = <0xffd00300 0x100>;
 359                         interrupts = <0 118 4>;
 360                         resets = <&rst WATCHDOG1_RESET>;
 361                         status = "disabled";
 362                 };
 363
 364                 watchdog2: watchdog@ffd00400 {
 365                         compatible = "snps,dw-wdt";
 366                         reg = <0xffd00400 0x100>;
 367                         interrupts = <0 125 4>;
 368                         resets = <&rst WATCHDOG2_RESET>;
 369                         status = "disabled";
 370                 };
 371
 372                 watchdog3: watchdog@ffd00500 {
 373                         compatible = "snps,dw-wdt";
 374                         reg = <0xffd00500 0x100>;
 375                         interrupts = <0 126 4>;
 376                         resets = <&rst WATCHDOG3_RESET>;
 377                         status = "disabled";
 378                 };
 379         };
 380 };