arch/arm/mach-stm32mp/stm32mp13x.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #define LOG_CATEGORY LOGC_ARCH
   7
   8 #include <common.h>
   9 #include <log.h>
  10 #include <syscon.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/stm32.h>
  13 #include <asm/arch/sys_proto.h>
  14
  15 /* SYSCFG register */
  16 #define SYSCFG_IDC_OFFSET       0x380
  17 #define SYSCFG_IDC_DEV_ID_MASK  GENMASK(11, 0)
  18 #define SYSCFG_IDC_DEV_ID_SHIFT 0
  19 #define SYSCFG_IDC_REV_ID_MASK  GENMASK(31, 16)
  20 #define SYSCFG_IDC_REV_ID_SHIFT 16
  21
  22 /* Device Part Number (RPN) = OTP_DATA1 lower 11 bits */
  23 #define RPN_SHIFT       0
  24 #define RPN_MASK        GENMASK(11, 0)
  25
  26 static u32 read_idc(void)
  27 {
  28         void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  29
  30         return readl(syscfg + SYSCFG_IDC_OFFSET);
  31 }
  32
  33 u32 get_cpu_dev(void)
  34 {
  35         return (read_idc() & SYSCFG_IDC_DEV_ID_MASK) >> SYSCFG_IDC_DEV_ID_SHIFT;
  36 }
  37
  38 u32 get_cpu_rev(void)
  39 {
  40         return (read_idc() & SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT;
  41 }
  42
  43 /* Get Device Part Number (RPN) from OTP */
  44 static u32 get_cpu_rpn(void)
  45 {
  46         return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
  47 }
  48
  49 u32 get_cpu_type(void)
  50 {
  51         return (get_cpu_dev() << 16) | get_cpu_rpn();
  52 }
  53
  54 int get_eth_nb(void)
  55 {
  56         int nb_eth = 2;
  57
  58         switch (get_cpu_type()) {
  59         case CPU_STM32MP131Dxx:
  60                 fallthrough;
  61         case CPU_STM32MP131Cxx:
  62                 fallthrough;
  63         case CPU_STM32MP131Axx:
  64                 nb_eth = 1;
  65                 break;
  66         default:
  67                 nb_eth = 2;
  68                 break;
  69         }
  70
  71         return nb_eth;
  72 }
  73
  74 void get_soc_name(char name[SOC_NAME_SIZE])
  75 {
  76         char *cpu_s, *cpu_r;
  77
  78         /* MPUs Part Numbers */
  79         switch (get_cpu_type()) {
  80         case CPU_STM32MP135Fxx:
  81                 cpu_s = "135F";
  82                 break;
  83         case CPU_STM32MP135Dxx:
  84                 cpu_s = "135D";
  85                 break;
  86         case CPU_STM32MP135Cxx:
  87                 cpu_s = "135C";
  88                 break;
  89         case CPU_STM32MP135Axx:
  90                 cpu_s = "135A";
  91                 break;
  92         case CPU_STM32MP133Fxx:
  93                 cpu_s = "133F";
  94                 break;
  95         case CPU_STM32MP133Dxx:
  96                 cpu_s = "133D";
  97                 break;
  98         case CPU_STM32MP133Cxx:
  99                 cpu_s = "133C";
 100                 break;
 101         case CPU_STM32MP133Axx:
 102                 cpu_s = "133A";
 103                 break;
 104         case CPU_STM32MP131Fxx:
 105                 cpu_s = "131F";
 106                 break;
 107         case CPU_STM32MP131Dxx:
 108                 cpu_s = "131D";
 109                 break;
 110         case CPU_STM32MP131Cxx:
 111                 cpu_s = "131C";
 112                 break;
 113         case CPU_STM32MP131Axx:
 114                 cpu_s = "131A";
 115                 break;
 116         default:
 117                 cpu_s = "????";
 118                 break;
 119         }
 120
 121         /* REVISION */
 122         switch (get_cpu_rev()) {
 123         case CPU_REV1:
 124                 cpu_r = "A";
 125                 break;
 126         case CPU_REV1_1:
 127                 cpu_r = "Z";
 128                 break;
 129         case CPU_REV1_2:
 130                 cpu_r = "Y";
 131                 break;
 132         default:
 133                 cpu_r = "?";
 134                 break;
 135         }
 136
 137         snprintf(name, SOC_NAME_SIZE, "STM32MP%s Rev.%s", cpu_s, cpu_r);
 138 }