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Merge branch '2024-05-06-remove-include-common_h' into next
[J-u-boot.git] / arch / x86 / cpu / broadwell / cpu.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2016 Google, Inc
4  *
5  * Based on code from coreboot src/soc/intel/broadwell/cpu.c
6  */
7
8 #include <dm.h>
9 #include <cpu.h>
10 #include <event.h>
11 #include <init.h>
12 #include <log.h>
13 #include <spl.h>
14 #include <asm/cpu.h>
15 #include <asm/cpu_x86.h>
16 #include <asm/cpu_common.h>
17 #include <asm/global_data.h>
18 #include <asm/intel_regs.h>
19 #include <asm/lpc_common.h>
20 #include <asm/msr.h>
21 #include <asm/pci.h>
22 #include <asm/post.h>
23 #include <asm/turbo.h>
24 #include <asm/arch/cpu.h>
25 #include <asm/arch/pch.h>
26 #include <asm/arch/rcb.h>
27
28 static int broadwell_init_cpu(void)
29 {
30         struct udevice *dev;
31         int ret;
32
33         /* Start up the LPC so we have serial */
34         ret = uclass_first_device_err(UCLASS_LPC, &dev);
35         if (ret)
36                 return ret;
37         ret = cpu_set_flex_ratio_to_tdp_nominal();
38         if (ret)
39                 return ret;
40
41         return 0;
42 }
43 EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, broadwell_init_cpu);
44
45 void set_max_freq(void)
46 {
47         msr_t msr, perf_ctl;
48
49         if (cpu_config_tdp_levels()) {
50                 /* Set to nominal TDP ratio */
51                 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
52                 perf_ctl.lo = (msr.lo & 0xff) << 8;
53         } else {
54                 /* Platform Info bits 15:8 give max ratio */
55                 msr = msr_read(MSR_PLATFORM_INFO);
56                 perf_ctl.lo = msr.lo & 0xff00;
57         }
58
59         perf_ctl.hi = 0;
60         msr_write(MSR_IA32_PERF_CTL, perf_ctl);
61
62         debug("CPU: frequency set to %d MHz\n",
63               ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
64 }
65
66 int arch_cpu_init(void)
67 {
68         post_code(POST_CPU_INIT);
69
70         /* Do a mini-init if TPL has already done the full init */
71         if (IS_ENABLED(CONFIG_TPL) && spl_phase() != PHASE_TPL)
72                 return x86_cpu_reinit_f();
73         else
74                 return x86_cpu_init_f();
75 }
76
77 int checkcpu(void)
78 {
79         int ret;
80
81         set_max_freq();
82
83         ret = cpu_common_init();
84         if (ret)
85                 return ret;
86         gd->arch.pei_boot_mode = PEI_BOOT_NONE;
87
88         return 0;
89 }
90
91 int print_cpuinfo(void)
92 {
93         char processor_name[CPU_MAX_NAME_LEN];
94         const char *name;
95
96         /* Print processor name */
97         name = cpu_get_name(processor_name);
98         printf("CPU:   %s\n", name);
99
100         return 0;
101 }
102
103 void board_debug_uart_init(void)
104 {
105         /* com1 / com2 decode range */
106         pci_x86_write_config(PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
107
108         pci_x86_write_config(PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);
109 }
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