drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include <errno.h>
  11 #include "sequencer.h"
  12 #include "sequencer_auto.h"
  13 #include "sequencer_auto_ac_init.h"
  14 #include "sequencer_auto_inst_init.h"
  15 #include "sequencer_defines.h"
  16
  17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  18         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  19
  20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  21         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  22
  23 static struct socfpga_sdr_reg_file *sdr_reg_file =
  24         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  25
  26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  27         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  28
  29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  30         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  31
  32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  33         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  34
  35 static struct socfpga_data_mgr *data_mgr =
  36         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  37
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 #define DELTA_D         1
  42
  43 /*
  44  * In order to reduce ROM size, most of the selectable calibration steps are
  45  * decided at compile time based on the user's calibration mode selection,
  46  * as captured by the STATIC_CALIB_STEPS selection below.
  47  *
  48  * However, to support simulation-time selection of fast simulation mode, where
  49  * we skip everything except the bare minimum, we need a few of the steps to
  50  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  51  * check, which is based on the rtl-supplied value, or we dynamically compute
  52  * the value to use based on the dynamically-chosen calibration mode
  53  */
  54
  55 #define DLEVEL 0
  56 #define STATIC_IN_RTL_SIM 0
  57 #define STATIC_SKIP_DELAY_LOOPS 0
  58
  59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  60         STATIC_SKIP_DELAY_LOOPS)
  61
  62 /* calibration steps requested by the rtl */
  63 uint16_t dyn_calib_steps;
  64
  65 /*
  66  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  67  * instead of static, we use boolean logic to select between
  68  * non-skip and skip values
  69  *
  70  * The mask is set to include all bits when not-skipping, but is
  71  * zero when skipping
  72  */
  73
  74 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  75
  76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  77         ((non_skip_value) & skip_delay_mask)
  78
  79 struct gbl_type *gbl;
  80 struct param_type *param;
  81 uint32_t curr_shadow_reg;
  82
  83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  84         uint32_t write_group, uint32_t use_dm,
  85         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  86
  87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  88         uint32_t substage)
  89 {
  90         /*
  91          * Only set the global stage if there was not been any other
  92          * failing group
  93          */
  94         if (gbl->error_stage == CAL_STAGE_NIL)  {
  95                 gbl->error_substage = substage;
  96                 gbl->error_stage = stage;
  97                 gbl->error_group = group;
  98         }
  99 }
 100
 101 static void reg_file_set_group(u16 set_group)
 102 {
 103         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 104 }
 105
 106 static void reg_file_set_stage(u8 set_stage)
 107 {
 108         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 109 }
 110
 111 static void reg_file_set_sub_stage(u8 set_sub_stage)
 112 {
 113         set_sub_stage &= 0xff;
 114         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 115 }
 116
 117 /**
 118  * phy_mgr_initialize() - Initialize PHY Manager
 119  *
 120  * Initialize PHY Manager.
 121  */
 122 static void phy_mgr_initialize(void)
 123 {
 124         u32 ratio;
 125
 126         debug("%s:%d\n", __func__, __LINE__);
 127         /* Calibration has control over path to memory */
 128         /*
 129          * In Hard PHY this is a 2-bit control:
 130          * 0: AFI Mux Select
 131          * 1: DDIO Mux Select
 132          */
 133         writel(0x3, &phy_mgr_cfg->mux_sel);
 134
 135         /* USER memory clock is not stable we begin initialization  */
 136         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 137
 138         /* USER calibration status all set to zero */
 139         writel(0, &phy_mgr_cfg->cal_status);
 140
 141         writel(0, &phy_mgr_cfg->cal_debug_info);
 142
 143         /* Init params only if we do NOT skip calibration. */
 144         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
 145                 return;
 146
 147         ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
 148                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
 149         param->read_correct_mask_vg = (1 << ratio) - 1;
 150         param->write_correct_mask_vg = (1 << ratio) - 1;
 151         param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 152         param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 153         ratio = RW_MGR_MEM_DATA_WIDTH /
 154                 RW_MGR_MEM_DATA_MASK_WIDTH;
 155         param->dm_correct_mask = (1 << ratio) - 1;
 156 }
 157
 158 /**
 159  * set_rank_and_odt_mask() - Set Rank and ODT mask
 160  * @rank:       Rank mask
 161  * @odt_mode:   ODT mode, OFF or READ_WRITE
 162  *
 163  * Set Rank and ODT mask (On-Die Termination).
 164  */
 165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
 166 {
 167         u32 odt_mask_0 = 0;
 168         u32 odt_mask_1 = 0;
 169         u32 cs_and_odt_mask;
 170
 171         if (odt_mode == RW_MGR_ODT_MODE_OFF) {
 172                 odt_mask_0 = 0x0;
 173                 odt_mask_1 = 0x0;
 174         } else {        /* RW_MGR_ODT_MODE_READ_WRITE */
 175                 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
 176                 case 1: /* 1 Rank */
 177                         /* Read: ODT = 0 ; Write: ODT = 1 */
 178                         odt_mask_0 = 0x0;
 179                         odt_mask_1 = 0x1;
 180                         break;
 181                 case 2: /* 2 Ranks */
 182                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 183                                 /*
 184                                  * - Dual-Slot , Single-Rank (1 CS per DIMM)
 185                                  *   OR
 186                                  * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
 187                                  *
 188                                  * Since MEM_NUMBER_OF_RANKS is 2, they
 189                                  * are both single rank with 2 CS each
 190                                  * (special for RDIMM).
 191                                  *
 192                                  * Read: Turn on ODT on the opposite rank
 193                                  * Write: Turn on ODT on all ranks
 194                                  */
 195                                 odt_mask_0 = 0x3 & ~(1 << rank);
 196                                 odt_mask_1 = 0x3;
 197                         } else {
 198                                 /*
 199                                  * - Single-Slot , Dual-Rank (2 CS per DIMM)
 200                                  *
 201                                  * Read: Turn on ODT off on all ranks
 202                                  * Write: Turn on ODT on active rank
 203                                  */
 204                                 odt_mask_0 = 0x0;
 205                                 odt_mask_1 = 0x3 & (1 << rank);
 206                         }
 207                         break;
 208                 case 4: /* 4 Ranks */
 209                         /* Read:
 210                          * ----------+-----------------------+
 211                          *           |         ODT           |
 212                          * Read From +-----------------------+
 213                          *   Rank    |  3  |  2  |  1  |  0  |
 214                          * ----------+-----+-----+-----+-----+
 215                          *     0     |  0  |  1  |  0  |  0  |
 216                          *     1     |  1  |  0  |  0  |  0  |
 217                          *     2     |  0  |  0  |  0  |  1  |
 218                          *     3     |  0  |  0  |  1  |  0  |
 219                          * ----------+-----+-----+-----+-----+
 220                          *
 221                          * Write:
 222                          * ----------+-----------------------+
 223                          *           |         ODT           |
 224                          * Write To  +-----------------------+
 225                          *   Rank    |  3  |  2  |  1  |  0  |
 226                          * ----------+-----+-----+-----+-----+
 227                          *     0     |  0  |  1  |  0  |  1  |
 228                          *     1     |  1  |  0  |  1  |  0  |
 229                          *     2     |  0  |  1  |  0  |  1  |
 230                          *     3     |  1  |  0  |  1  |  0  |
 231                          * ----------+-----+-----+-----+-----+
 232                          */
 233                         switch (rank) {
 234                         case 0:
 235                                 odt_mask_0 = 0x4;
 236                                 odt_mask_1 = 0x5;
 237                                 break;
 238                         case 1:
 239                                 odt_mask_0 = 0x8;
 240                                 odt_mask_1 = 0xA;
 241                                 break;
 242                         case 2:
 243                                 odt_mask_0 = 0x1;
 244                                 odt_mask_1 = 0x5;
 245                                 break;
 246                         case 3:
 247                                 odt_mask_0 = 0x2;
 248                                 odt_mask_1 = 0xA;
 249                                 break;
 250                         }
 251                         break;
 252                 }
 253         }
 254
 255         cs_and_odt_mask = (0xFF & ~(1 << rank)) |
 256                           ((0xFF & odt_mask_0) << 8) |
 257                           ((0xFF & odt_mask_1) << 16);
 258         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 259                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 260 }
 261
 262 /**
 263  * scc_mgr_set() - Set SCC Manager register
 264  * @off:        Base offset in SCC Manager space
 265  * @grp:        Read/Write group
 266  * @val:        Value to be set
 267  *
 268  * This function sets the SCC Manager (Scan Chain Control Manager) register.
 269  */
 270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
 271 {
 272         writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
 273 }
 274
 275 /**
 276  * scc_mgr_initialize() - Initialize SCC Manager registers
 277  *
 278  * Initialize SCC Manager registers.
 279  */
 280 static void scc_mgr_initialize(void)
 281 {
 282         /*
 283          * Clear register file for HPS. 16 (2^4) is the size of the
 284          * full register file in the scc mgr:
 285          *      RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 286          *                             MEM_IF_READ_DQS_WIDTH - 1);
 287          */
 288         int i;
 289
 290         for (i = 0; i < 16; i++) {
 291                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 292                            __func__, __LINE__, i);
 293                 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
 294         }
 295 }
 296
 297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 298 {
 299         scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
 300 }
 301
 302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 303 {
 304         scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
 305 }
 306
 307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 308 {
 309         scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
 310 }
 311
 312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 313 {
 314         scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 315 }
 316
 317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
 318 {
 319         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 320                     delay);
 321 }
 322
 323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 324 {
 325         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
 326 }
 327
 328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 329 {
 330         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
 331 }
 332
 333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
 334 {
 335         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 336                     delay);
 337 }
 338
 339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 340 {
 341         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
 342                     RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
 343                     delay);
 344 }
 345
 346 /* load up dqs config settings */
 347 static void scc_mgr_load_dqs(uint32_t dqs)
 348 {
 349         writel(dqs, &sdr_scc_mgr->dqs_ena);
 350 }
 351
 352 /* load up dqs io config settings */
 353 static void scc_mgr_load_dqs_io(void)
 354 {
 355         writel(0, &sdr_scc_mgr->dqs_io_ena);
 356 }
 357
 358 /* load up dq config settings */
 359 static void scc_mgr_load_dq(uint32_t dq_in_group)
 360 {
 361         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 362 }
 363
 364 /* load up dm config settings */
 365 static void scc_mgr_load_dm(uint32_t dm)
 366 {
 367         writel(dm, &sdr_scc_mgr->dm_ena);
 368 }
 369
 370 /**
 371  * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
 372  * @off:        Base offset in SCC Manager space
 373  * @grp:        Read/Write group
 374  * @val:        Value to be set
 375  * @update:     If non-zero, trigger SCC Manager update for all ranks
 376  *
 377  * This function sets the SCC Manager (Scan Chain Control Manager) register
 378  * and optionally triggers the SCC update for all ranks.
 379  */
 380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
 381                                   const int update)
 382 {
 383         u32 r;
 384
 385         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 386              r += NUM_RANKS_PER_SHADOW_REG) {
 387                 scc_mgr_set(off, grp, val);
 388
 389                 if (update || (r == 0)) {
 390                         writel(grp, &sdr_scc_mgr->dqs_ena);
 391                         writel(0, &sdr_scc_mgr->update);
 392                 }
 393         }
 394 }
 395
 396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
 397 {
 398         /*
 399          * USER although the h/w doesn't support different phases per
 400          * shadow register, for simplicity our scc manager modeling
 401          * keeps different phase settings per shadow reg, and it's
 402          * important for us to keep them in sync to match h/w.
 403          * for efficiency, the scan chain update should occur only
 404          * once to sr0.
 405          */
 406         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
 407                               read_group, phase, 0);
 408 }
 409
 410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 411                                                      uint32_t phase)
 412 {
 413         /*
 414          * USER although the h/w doesn't support different phases per
 415          * shadow register, for simplicity our scc manager modeling
 416          * keeps different phase settings per shadow reg, and it's
 417          * important for us to keep them in sync to match h/w.
 418          * for efficiency, the scan chain update should occur only
 419          * once to sr0.
 420          */
 421         scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
 422                               write_group, phase, 0);
 423 }
 424
 425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 426                                                uint32_t delay)
 427 {
 428         /*
 429          * In shadow register mode, the T11 settings are stored in
 430          * registers in the core, which are updated by the DQS_ENA
 431          * signals. Not issuing the SCC_MGR_UPD command allows us to
 432          * save lots of rank switching overhead, by calling
 433          * select_shadow_regs_for_update with update_scan_chains
 434          * set to 0.
 435          */
 436         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 437                               read_group, delay, 1);
 438         writel(0, &sdr_scc_mgr->update);
 439 }
 440
 441 /**
 442  * scc_mgr_set_oct_out1_delay() - Set OCT output delay
 443  * @write_group:        Write group
 444  * @delay:              Delay value
 445  *
 446  * This function sets the OCT output delay in SCC manager.
 447  */
 448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 449 {
 450         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 451                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 452         const int base = write_group * ratio;
 453         int i;
 454         /*
 455          * Load the setting in the SCC manager
 456          * Although OCT affects only write data, the OCT delay is controlled
 457          * by the DQS logic block which is instantiated once per read group.
 458          * For protocols where a write group consists of multiple read groups,
 459          * the setting must be set multiple times.
 460          */
 461         for (i = 0; i < ratio; i++)
 462                 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 463 }
 464
 465 /**
 466  * scc_mgr_set_hhp_extras() - Set HHP extras.
 467  *
 468  * Load the fixed setting in the SCC manager HHP extras.
 469  */
 470 static void scc_mgr_set_hhp_extras(void)
 471 {
 472         /*
 473          * Load the fixed setting in the SCC manager
 474          * bits: 0:0 = 1'b1     - DQS bypass
 475          * bits: 1:1 = 1'b1     - DQ bypass
 476          * bits: 4:2 = 3'b001   - rfifo_mode
 477          * bits: 6:5 = 2'b01    - rfifo clock_select
 478          * bits: 7:7 = 1'b0     - separate gating from ungating setting
 479          * bits: 8:8 = 1'b0     - separate OE from Output delay setting
 480          */
 481         const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
 482                           (1 << 2) | (1 << 1) | (1 << 0);
 483         const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
 484                          SCC_MGR_HHP_GLOBALS_OFFSET |
 485                          SCC_MGR_HHP_EXTRAS_OFFSET;
 486
 487         debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
 488                    __func__, __LINE__);
 489         writel(value, addr);
 490         debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 491                    __func__, __LINE__);
 492 }
 493
 494 /**
 495  * scc_mgr_zero_all() - Zero all DQS config
 496  *
 497  * Zero all DQS config.
 498  */
 499 static void scc_mgr_zero_all(void)
 500 {
 501         int i, r;
 502
 503         /*
 504          * USER Zero all DQS config settings, across all groups and all
 505          * shadow registers
 506          */
 507         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 508              r += NUM_RANKS_PER_SHADOW_REG) {
 509                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 510                         /*
 511                          * The phases actually don't exist on a per-rank basis,
 512                          * but there's no harm updating them several times, so
 513                          * let's keep the code simple.
 514                          */
 515                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 516                         scc_mgr_set_dqs_en_phase(i, 0);
 517                         scc_mgr_set_dqs_en_delay(i, 0);
 518                 }
 519
 520                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 521                         scc_mgr_set_dqdqs_output_phase(i, 0);
 522                         /* Arria V/Cyclone V don't have out2. */
 523                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 524                 }
 525         }
 526
 527         /* Multicast to all DQS group enables. */
 528         writel(0xff, &sdr_scc_mgr->dqs_ena);
 529         writel(0, &sdr_scc_mgr->update);
 530 }
 531
 532 /**
 533  * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
 534  * @write_group:        Write group
 535  *
 536  * Set bypass mode and trigger SCC update.
 537  */
 538 static void scc_set_bypass_mode(const u32 write_group)
 539 {
 540         /* Multicast to all DQ enables. */
 541         writel(0xff, &sdr_scc_mgr->dq_ena);
 542         writel(0xff, &sdr_scc_mgr->dm_ena);
 543
 544         /* Update current DQS IO enable. */
 545         writel(0, &sdr_scc_mgr->dqs_io_ena);
 546
 547         /* Update the DQS logic. */
 548         writel(write_group, &sdr_scc_mgr->dqs_ena);
 549
 550         /* Hit update. */
 551         writel(0, &sdr_scc_mgr->update);
 552 }
 553
 554 /**
 555  * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
 556  * @write_group:        Write group
 557  *
 558  * Load DQS settings for Write Group, do not trigger SCC update.
 559  */
 560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
 561 {
 562         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 563                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 564         const int base = write_group * ratio;
 565         int i;
 566         /*
 567          * Load the setting in the SCC manager
 568          * Although OCT affects only write data, the OCT delay is controlled
 569          * by the DQS logic block which is instantiated once per read group.
 570          * For protocols where a write group consists of multiple read groups,
 571          * the setting must be set multiple times.
 572          */
 573         for (i = 0; i < ratio; i++)
 574                 writel(base + i, &sdr_scc_mgr->dqs_ena);
 575 }
 576
 577 /**
 578  * scc_mgr_zero_group() - Zero all configs for a group
 579  *
 580  * Zero DQ, DM, DQS and OCT configs for a group.
 581  */
 582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 583 {
 584         int i, r;
 585
 586         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 587              r += NUM_RANKS_PER_SHADOW_REG) {
 588                 /* Zero all DQ config settings. */
 589                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 590                         scc_mgr_set_dq_out1_delay(i, 0);
 591                         if (!out_only)
 592                                 scc_mgr_set_dq_in_delay(i, 0);
 593                 }
 594
 595                 /* Multicast to all DQ enables. */
 596                 writel(0xff, &sdr_scc_mgr->dq_ena);
 597
 598                 /* Zero all DM config settings. */
 599                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 600                         scc_mgr_set_dm_out1_delay(i, 0);
 601
 602                 /* Multicast to all DM enables. */
 603                 writel(0xff, &sdr_scc_mgr->dm_ena);
 604
 605                 /* Zero all DQS IO settings. */
 606                 if (!out_only)
 607                         scc_mgr_set_dqs_io_in_delay(0);
 608
 609                 /* Arria V/Cyclone V don't have out2. */
 610                 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
 611                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 612                 scc_mgr_load_dqs_for_write_group(write_group);
 613
 614                 /* Multicast to all DQS IO enables (only 1 in total). */
 615                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 616
 617                 /* Hit update to zero everything. */
 618                 writel(0, &sdr_scc_mgr->update);
 619         }
 620 }
 621
 622 /*
 623  * apply and load a particular input delay for the DQ pins in a group
 624  * group_bgn is the index of the first dq pin (in the write group)
 625  */
 626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
 627 {
 628         uint32_t i, p;
 629
 630         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 631                 scc_mgr_set_dq_in_delay(p, delay);
 632                 scc_mgr_load_dq(p);
 633         }
 634 }
 635
 636 /**
 637  * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
 638  * @delay:              Delay value
 639  *
 640  * Apply and load a particular output delay for the DQ pins in a group.
 641  */
 642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
 643 {
 644         int i;
 645
 646         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 647                 scc_mgr_set_dq_out1_delay(i, delay);
 648                 scc_mgr_load_dq(i);
 649         }
 650 }
 651
 652 /* apply and load a particular output delay for the DM pins in a group */
 653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
 654 {
 655         uint32_t i;
 656
 657         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 658                 scc_mgr_set_dm_out1_delay(i, delay1);
 659                 scc_mgr_load_dm(i);
 660         }
 661 }
 662
 663
 664 /* apply and load delay on both DQS and OCT out1 */
 665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 666                                                     uint32_t delay)
 667 {
 668         scc_mgr_set_dqs_out1_delay(delay);
 669         scc_mgr_load_dqs_io();
 670
 671         scc_mgr_set_oct_out1_delay(write_group, delay);
 672         scc_mgr_load_dqs_for_write_group(write_group);
 673 }
 674
 675 /**
 676  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
 677  * @write_group:        Write group
 678  * @delay:              Delay value
 679  *
 680  * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
 681  */
 682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 683                                                   const u32 delay)
 684 {
 685         u32 i, new_delay;
 686
 687         /* DQ shift */
 688         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
 689                 scc_mgr_load_dq(i);
 690
 691         /* DM shift */
 692         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 693                 scc_mgr_load_dm(i);
 694
 695         /* DQS shift */
 696         new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 697         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 698                 debug_cond(DLEVEL == 1,
 699                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 700                            __func__, __LINE__, write_group, delay, new_delay,
 701                            IO_IO_OUT2_DELAY_MAX,
 702                            new_delay - IO_IO_OUT2_DELAY_MAX);
 703                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 704                 scc_mgr_set_dqs_out1_delay(new_delay);
 705         }
 706
 707         scc_mgr_load_dqs_io();
 708
 709         /* OCT shift */
 710         new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 711         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 712                 debug_cond(DLEVEL == 1,
 713                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 714                            __func__, __LINE__, write_group, delay,
 715                            new_delay, IO_IO_OUT2_DELAY_MAX,
 716                            new_delay - IO_IO_OUT2_DELAY_MAX);
 717                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 718                 scc_mgr_set_oct_out1_delay(write_group, new_delay);
 719         }
 720
 721         scc_mgr_load_dqs_for_write_group(write_group);
 722 }
 723
 724 /**
 725  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
 726  * @write_group:        Write group
 727  * @delay:              Delay value
 728  *
 729  * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
 730  */
 731 static void
 732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
 733                                                 const u32 delay)
 734 {
 735         int r;
 736
 737         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 738              r += NUM_RANKS_PER_SHADOW_REG) {
 739                 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
 740                 writel(0, &sdr_scc_mgr->update);
 741         }
 742 }
 743
 744 /**
 745  * set_jump_as_return() - Return instruction optimization
 746  *
 747  * Optimization used to recover some slots in ddr3 inst_rom could be
 748  * applied to other protocols if we wanted to
 749  */
 750 static void set_jump_as_return(void)
 751 {
 752         /*
 753          * To save space, we replace return with jump to special shared
 754          * RETURN instruction so we set the counter to large value so that
 755          * we always jump.
 756          */
 757         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 758         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 759 }
 760
 761 /*
 762  * should always use constants as argument to ensure all computations are
 763  * performed at compile time
 764  */
 765 static void delay_for_n_mem_clocks(const uint32_t clocks)
 766 {
 767         uint32_t afi_clocks;
 768         uint8_t inner = 0;
 769         uint8_t outer = 0;
 770         uint16_t c_loop = 0;
 771
 772         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 773
 774
 775         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 776         /* scale (rounding up) to get afi clocks */
 777
 778         /*
 779          * Note, we don't bother accounting for being off a little bit
 780          * because of a few extra instructions in outer loops
 781          * Note, the loops have a test at the end, and do the test before
 782          * the decrement, and so always perform the loop
 783          * 1 time more than the counter value
 784          */
 785         if (afi_clocks == 0) {
 786                 ;
 787         } else if (afi_clocks <= 0x100) {
 788                 inner = afi_clocks-1;
 789                 outer = 0;
 790                 c_loop = 0;
 791         } else if (afi_clocks <= 0x10000) {
 792                 inner = 0xff;
 793                 outer = (afi_clocks-1) >> 8;
 794                 c_loop = 0;
 795         } else {
 796                 inner = 0xff;
 797                 outer = 0xff;
 798                 c_loop = (afi_clocks-1) >> 16;
 799         }
 800
 801         /*
 802          * rom instructions are structured as follows:
 803          *
 804          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 805          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 806          *                return
 807          *
 808          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 809          * TARGET_B is set to IDLE_LOOP2 as well
 810          *
 811          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 812          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 813          *
 814          * a little confusing, but it helps save precious space in the inst_rom
 815          * and sequencer rom and keeps the delays more accurate and reduces
 816          * overhead
 817          */
 818         if (afi_clocks <= 0x100) {
 819                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 820                         &sdr_rw_load_mgr_regs->load_cntr1);
 821
 822                 writel(RW_MGR_IDLE_LOOP1,
 823                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 824
 825                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 826                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 827         } else {
 828                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 829                         &sdr_rw_load_mgr_regs->load_cntr0);
 830
 831                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 832                         &sdr_rw_load_mgr_regs->load_cntr1);
 833
 834                 writel(RW_MGR_IDLE_LOOP2,
 835                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 836
 837                 writel(RW_MGR_IDLE_LOOP2,
 838                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 839
 840                 /* hack to get around compiler not being smart enough */
 841                 if (afi_clocks <= 0x10000) {
 842                         /* only need to run once */
 843                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 844                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 845                 } else {
 846                         do {
 847                                 writel(RW_MGR_IDLE_LOOP2,
 848                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 849                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 850                         } while (c_loop-- != 0);
 851                 }
 852         }
 853         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 854 }
 855
 856 /**
 857  * rw_mgr_mem_init_load_regs() - Load instruction registers
 858  * @cntr0:      Counter 0 value
 859  * @cntr1:      Counter 1 value
 860  * @cntr2:      Counter 2 value
 861  * @jump:       Jump instruction value
 862  *
 863  * Load instruction registers.
 864  */
 865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
 866 {
 867         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 868                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 869
 870         /* Load counters */
 871         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
 872                &sdr_rw_load_mgr_regs->load_cntr0);
 873         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
 874                &sdr_rw_load_mgr_regs->load_cntr1);
 875         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
 876                &sdr_rw_load_mgr_regs->load_cntr2);
 877
 878         /* Load jump address */
 879         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 880         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 881         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 882
 883         /* Execute count instruction */
 884         writel(jump, grpaddr);
 885 }
 886
 887 /**
 888  * rw_mgr_mem_load_user() - Load user calibration values
 889  * @fin1:       Final instruction 1
 890  * @fin2:       Final instruction 2
 891  * @precharge:  If 1, precharge the banks at the end
 892  *
 893  * Load user calibration values and optionally precharge the banks.
 894  */
 895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
 896                                  const int precharge)
 897 {
 898         u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 899                       RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 900         u32 r;
 901
 902         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 903                 if (param->skip_ranks[r]) {
 904                         /* request to skip the rank */
 905                         continue;
 906                 }
 907
 908                 /* set rank */
 909                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 910
 911                 /* precharge all banks ... */
 912                 if (precharge)
 913                         writel(RW_MGR_PRECHARGE_ALL, grpaddr);
 914
 915                 /*
 916                  * USER Use Mirror-ed commands for odd ranks if address
 917                  * mirrorring is on
 918                  */
 919                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 920                         set_jump_as_return();
 921                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 922                         delay_for_n_mem_clocks(4);
 923                         set_jump_as_return();
 924                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 925                         delay_for_n_mem_clocks(4);
 926                         set_jump_as_return();
 927                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 928                         delay_for_n_mem_clocks(4);
 929                         set_jump_as_return();
 930                         writel(fin1, grpaddr);
 931                 } else {
 932                         set_jump_as_return();
 933                         writel(RW_MGR_MRS2, grpaddr);
 934                         delay_for_n_mem_clocks(4);
 935                         set_jump_as_return();
 936                         writel(RW_MGR_MRS3, grpaddr);
 937                         delay_for_n_mem_clocks(4);
 938                         set_jump_as_return();
 939                         writel(RW_MGR_MRS1, grpaddr);
 940                         set_jump_as_return();
 941                         writel(fin2, grpaddr);
 942                 }
 943
 944                 if (precharge)
 945                         continue;
 946
 947                 set_jump_as_return();
 948                 writel(RW_MGR_ZQCL, grpaddr);
 949
 950                 /* tZQinit = tDLLK = 512 ck cycles */
 951                 delay_for_n_mem_clocks(512);
 952         }
 953 }
 954
 955 /**
 956  * rw_mgr_mem_initialize() - Initialize RW Manager
 957  *
 958  * Initialize RW Manager.
 959  */
 960 static void rw_mgr_mem_initialize(void)
 961 {
 962         debug("%s:%d\n", __func__, __LINE__);
 963
 964         /* The reset / cke part of initialization is broadcasted to all ranks */
 965         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 966                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 967
 968         /*
 969          * Here's how you load register for a loop
 970          * Counters are located @ 0x800
 971          * Jump address are located @ 0xC00
 972          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 973          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 974          * I know this ain't pretty, but Avalon bus throws away the 2 least
 975          * significant bits
 976          */
 977
 978         /* Start with memory RESET activated */
 979
 980         /* tINIT = 200us */
 981
 982         /*
 983          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 984          * If a and b are the number of iteration in 2 nested loops
 985          * it takes the following number of cycles to complete the operation:
 986          * number_of_cycles = ((2 + n) * a + 2) * b
 987          * where n is the number of instruction in the inner loop
 988          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 989          * b = 6A
 990          */
 991         rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
 992                                   SEQ_TINIT_CNTR2_VAL,
 993                                   RW_MGR_INIT_RESET_0_CKE_0);
 994
 995         /* Indicate that memory is stable. */
 996         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 997
 998         /*
 999          * transition the RESET to high
1000          * Wait for 500us
1001          */
1002
1003         /*
1004          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005          * If a and b are the number of iteration in 2 nested loops
1006          * it takes the following number of cycles to complete the operation
1007          * number_of_cycles = ((2 + n) * a + 2) * b
1008          * where n is the number of instruction in the inner loop
1009          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010          * b = FF
1011          */
1012         rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013                                   SEQ_TRESET_CNTR2_VAL,
1014                                   RW_MGR_INIT_RESET_1_CKE_0);
1015
1016         /* Bring up clock enable. */
1017
1018         /* tXRP < 250 ck cycles */
1019         delay_for_n_mem_clocks(250);
1020
1021         rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022                              0);
1023 }
1024
1025 /*
1026  * At the end of calibration we have to program the user settings in, and
1027  * USER  hand off the memory to the user.
1028  */
1029 static void rw_mgr_mem_handoff(void)
1030 {
1031         rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032         /*
1033          * USER  need to wait tMOD (12CK or 15ns) time before issuing
1034          * other commands, but we will have plenty of NIOS cycles before
1035          * actual handoff so its okay.
1036          */
1037 }
1038
1039 /**
1040  * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041  * @rank_bgn:   Rank number
1042  * @group:      Read/Write Group
1043  * @all_ranks:  Test all ranks
1044  *
1045  * Performs a guaranteed read on the patterns we are going to use during a
1046  * read test to ensure memory works.
1047  */
1048 static int
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050                                         const u32 all_ranks)
1051 {
1052         const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053                          RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054         const u32 addr_offset =
1055                          (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056         const u32 rank_end = all_ranks ?
1057                                 RW_MGR_MEM_NUMBER_OF_RANKS :
1058                                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059         const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061         const u32 correct_mask_vg = param->read_correct_mask_vg;
1062
1063         u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1064         int vg, r;
1065         int ret = 0;
1066
1067         bit_chk = param->read_correct_mask;
1068
1069         for (r = rank_bgn; r < rank_end; r++) {
1070                 /* Request to skip the rank */
1071                 if (param->skip_ranks[r])
1072                         continue;
1073
1074                 /* Set rank */
1075                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1076
1077                 /* Load up a constant bursts of read commands */
1078                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079                 writel(RW_MGR_GUARANTEED_READ,
1080                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1081
1082                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083                 writel(RW_MGR_GUARANTEED_READ_CONT,
1084                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1085
1086                 tmp_bit_chk = 0;
1087                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1088                      vg >= 0; vg--) {
1089                         /* Reset the FIFOs to get pointers to known state. */
1090                         writel(0, &phy_mgr_cmd->fifo_reset);
1091                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093                         writel(RW_MGR_GUARANTEED_READ,
1094                                addr + addr_offset + (vg << 2));
1095
1096                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097                         tmp_bit_chk <<= shift_ratio;
1098                         tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1099                 }
1100
1101                 bit_chk &= tmp_bit_chk;
1102         }
1103
1104         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1105
1106         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1107
1108         if (bit_chk != param->read_correct_mask)
1109                 ret = -EIO;
1110
1111         debug_cond(DLEVEL == 1,
1112                    "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113                    __func__, __LINE__, group, bit_chk,
1114                    param->read_correct_mask, ret);
1115
1116         return ret;
1117 }
1118
1119 /**
1120  * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121  * @rank_bgn:   Rank number
1122  * @all_ranks:  Test all ranks
1123  *
1124  * Load up the patterns we are going to use during a read test.
1125  */
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127                                                     const int all_ranks)
1128 {
1129         const u32 rank_end = all_ranks ?
1130                         RW_MGR_MEM_NUMBER_OF_RANKS :
1131                         (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1132         u32 r;
1133
1134         debug("%s:%d\n", __func__, __LINE__);
1135
1136         for (r = rank_bgn; r < rank_end; r++) {
1137                 if (param->skip_ranks[r])
1138                         /* request to skip the rank */
1139                         continue;
1140
1141                 /* set rank */
1142                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1143
1144                 /* Load up a constant bursts */
1145                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1146
1147                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1149
1150                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1151
1152                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1154
1155                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1156
1157                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1159
1160                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1161
1162                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1164
1165                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1167         }
1168
1169         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1170 }
1171
1172 /*
1173  * try a read and see if it returns correct data back. has dummy reads
1174  * inserted into the mix used to align dqs enable. has more thorough checks
1175  * than the regular read test.
1176  */
1177 static int
1178 rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1179                                const u32 num_tries, const u32 all_correct,
1180                                u32 *bit_chk,
1181                                const u32 all_groups, const u32 all_ranks)
1182 {
1183         const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1184                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1185         const u32 quick_read_mode =
1186                 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1187                  ENABLE_SUPER_QUICK_CALIBRATION);
1188         u32 correct_mask_vg = param->read_correct_mask_vg;
1189         u32 tmp_bit_chk;
1190         u32 base_rw_mgr;
1191         u32 addr;
1192
1193         int r, vg, ret;
1194
1195         *bit_chk = param->read_correct_mask;
1196
1197         for (r = rank_bgn; r < rank_end; r++) {
1198                 if (param->skip_ranks[r])
1199                         /* request to skip the rank */
1200                         continue;
1201
1202                 /* set rank */
1203                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1204
1205                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1206
1207                 writel(RW_MGR_READ_B2B_WAIT1,
1208                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1209
1210                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1211                 writel(RW_MGR_READ_B2B_WAIT2,
1212                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1213
1214                 if (quick_read_mode)
1215                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1216                         /* need at least two (1+1) reads to capture failures */
1217                 else if (all_groups)
1218                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1219                 else
1220                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1221
1222                 writel(RW_MGR_READ_B2B,
1223                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1224                 if (all_groups)
1225                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1226                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1227                                &sdr_rw_load_mgr_regs->load_cntr3);
1228                 else
1229                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1230
1231                 writel(RW_MGR_READ_B2B,
1232                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1233
1234                 tmp_bit_chk = 0;
1235                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
1236                      vg--) {
1237                         /* reset the fifos to get pointers to known state */
1238                         writel(0, &phy_mgr_cmd->fifo_reset);
1239                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1240                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1241
1242                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1243                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1244
1245                         if (all_groups)
1246                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1247                         else
1248                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1249
1250                         writel(RW_MGR_READ_B2B, addr +
1251                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1252                                vg) << 2));
1253
1254                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1255                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1256                 }
1257
1258                 *bit_chk &= tmp_bit_chk;
1259         }
1260
1261         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1262         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1263
1264         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1265
1266         if (all_correct) {
1267                 ret = (*bit_chk == param->read_correct_mask);
1268                 debug_cond(DLEVEL == 2,
1269                            "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1270                            __func__, __LINE__, group, all_groups, *bit_chk,
1271                            param->read_correct_mask, ret);
1272         } else  {
1273                 ret = (*bit_chk != 0x00);
1274                 debug_cond(DLEVEL == 2,
1275                            "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1276                            __func__, __LINE__, group, all_groups, *bit_chk,
1277                            0, ret);
1278         }
1279
1280         return ret;
1281 }
1282
1283 /**
1284  * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1285  * @grp:                Read/Write group
1286  * @num_tries:          Number of retries of the test
1287  * @all_correct:        All bits must be correct in the mask
1288  * @all_groups:         Test all R/W groups
1289  *
1290  * Perform a READ test across all memory ranks.
1291  */
1292 static int
1293 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1294                                          const u32 all_correct,
1295                                          const u32 all_groups)
1296 {
1297         u32 bit_chk;
1298         return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1299                                               &bit_chk, all_groups, 1);
1300 }
1301
1302 /**
1303  * rw_mgr_incr_vfifo() - Increase VFIFO value
1304  * @grp:        Read/Write group
1305  *
1306  * Increase VFIFO value.
1307  */
1308 static void rw_mgr_incr_vfifo(const u32 grp)
1309 {
1310         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1311 }
1312
1313 /**
1314  * rw_mgr_decr_vfifo() - Decrease VFIFO value
1315  * @grp:        Read/Write group
1316  *
1317  * Decrease VFIFO value.
1318  */
1319 static void rw_mgr_decr_vfifo(const u32 grp)
1320 {
1321         u32 i;
1322
1323         for (i = 0; i < VFIFO_SIZE - 1; i++)
1324                 rw_mgr_incr_vfifo(grp);
1325 }
1326
1327 /**
1328  * find_vfifo_failing_read() - Push VFIFO to get a failing read
1329  * @grp:        Read/Write group
1330  *
1331  * Push VFIFO until a failing read happens.
1332  */
1333 static int find_vfifo_failing_read(const u32 grp)
1334 {
1335         u32 v, ret, fail_cnt = 0;
1336
1337         for (v = 0; v < VFIFO_SIZE; v++) {
1338                 debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
1339                            __func__, __LINE__, v);
1340                 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1341                                                 PASS_ONE_BIT, 0);
1342                 if (!ret) {
1343                         fail_cnt++;
1344
1345                         if (fail_cnt == 2)
1346                                 return v;
1347                 }
1348
1349                 /* Fiddle with FIFO. */
1350                 rw_mgr_incr_vfifo(grp);
1351         }
1352
1353         /* No failing read found! Something must have gone wrong. */
1354         debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1355         return 0;
1356 }
1357
1358 /**
1359  * sdr_find_phase_delay() - Find DQS enable phase or delay
1360  * @working:    If 1, look for working phase/delay, if 0, look for non-working
1361  * @delay:      If 1, look for delay, if 0, look for phase
1362  * @grp:        Read/Write group
1363  * @work:       Working window position
1364  * @work_inc:   Working window increment
1365  * @pd:         DQS Phase/Delay Iterator
1366  *
1367  * Find working or non-working DQS enable phase setting.
1368  */
1369 static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1370                                 u32 *work, const u32 work_inc, u32 *pd)
1371 {
1372         const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
1373         u32 ret;
1374
1375         for (; *pd <= max; (*pd)++) {
1376                 if (delay)
1377                         scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1378                 else
1379                         scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1380
1381                 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1382                                         PASS_ONE_BIT, 0);
1383                 if (!working)
1384                         ret = !ret;
1385
1386                 if (ret)
1387                         return 0;
1388
1389                 if (work)
1390                         *work += work_inc;
1391         }
1392
1393         return -EINVAL;
1394 }
1395 /**
1396  * sdr_find_phase() - Find DQS enable phase
1397  * @working:    If 1, look for working phase, if 0, look for non-working phase
1398  * @grp:        Read/Write group
1399  * @work:       Working window position
1400  * @i:          Iterator
1401  * @p:          DQS Phase Iterator
1402  *
1403  * Find working or non-working DQS enable phase setting.
1404  */
1405 static int sdr_find_phase(int working, const u32 grp, u32 *work,
1406                           u32 *i, u32 *p)
1407 {
1408         const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1409         int ret;
1410
1411         for (; *i < end; (*i)++) {
1412                 if (working)
1413                         *p = 0;
1414
1415                 ret = sdr_find_phase_delay(working, 0, grp, work,
1416                                            IO_DELAY_PER_OPA_TAP, p);
1417                 if (!ret)
1418                         return 0;
1419
1420                 if (*p > IO_DQS_EN_PHASE_MAX) {
1421                         /* Fiddle with FIFO. */
1422                         rw_mgr_incr_vfifo(grp);
1423                         if (!working)
1424                                 *p = 0;
1425                 }
1426         }
1427
1428         return -EINVAL;
1429 }
1430
1431 /**
1432  * sdr_working_phase() - Find working DQS enable phase
1433  * @grp:        Read/Write group
1434  * @work_bgn:   Working window start position
1435  * @d:          dtaps output value
1436  * @p:          DQS Phase Iterator
1437  * @i:          Iterator
1438  *
1439  * Find working DQS enable phase setting.
1440  */
1441 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
1442                              u32 *p, u32 *i)
1443 {
1444         const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1445                                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1446         int ret;
1447
1448         *work_bgn = 0;
1449
1450         for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1451                 *i = 0;
1452                 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1453                 ret = sdr_find_phase(1, grp, work_bgn, i, p);
1454                 if (!ret)
1455                         return 0;
1456                 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1457         }
1458
1459         /* Cannot find working solution */
1460         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1461                    __func__, __LINE__);
1462         return -EINVAL;
1463 }
1464
1465 /**
1466  * sdr_backup_phase() - Find DQS enable backup phase
1467  * @grp:        Read/Write group
1468  * @work_bgn:   Working window start position
1469  * @p:          DQS Phase Iterator
1470  *
1471  * Find DQS enable backup phase setting.
1472  */
1473 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
1474 {
1475         u32 tmp_delay, d;
1476         int ret;
1477
1478         /* Special case code for backing up a phase */
1479         if (*p == 0) {
1480                 *p = IO_DQS_EN_PHASE_MAX;
1481                 rw_mgr_decr_vfifo(grp);
1482         } else {
1483                 (*p)--;
1484         }
1485         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1486         scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1487
1488         for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1489                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1490
1491                 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1492                                         PASS_ONE_BIT, 0);
1493                 if (ret) {
1494                         *work_bgn = tmp_delay;
1495                         break;
1496                 }
1497
1498                 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1499         }
1500
1501         /* Restore VFIFO to old state before we decremented it (if needed). */
1502         (*p)++;
1503         if (*p > IO_DQS_EN_PHASE_MAX) {
1504                 *p = 0;
1505                 rw_mgr_incr_vfifo(grp);
1506         }
1507
1508         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1509 }
1510
1511 /**
1512  * sdr_nonworking_phase() - Find non-working DQS enable phase
1513  * @grp:        Read/Write group
1514  * @work_end:   Working window end position
1515  * @p:          DQS Phase Iterator
1516  * @i:          Iterator
1517  *
1518  * Find non-working DQS enable phase setting.
1519  */
1520 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
1521 {
1522         int ret;
1523
1524         (*p)++;
1525         *work_end += IO_DELAY_PER_OPA_TAP;
1526         if (*p > IO_DQS_EN_PHASE_MAX) {
1527                 /* Fiddle with FIFO. */
1528                 *p = 0;
1529                 rw_mgr_incr_vfifo(grp);
1530         }
1531
1532         ret = sdr_find_phase(0, grp, work_end, i, p);
1533         if (ret) {
1534                 /* Cannot see edge of failing read. */
1535                 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1536                            __func__, __LINE__);
1537         }
1538
1539         return ret;
1540 }
1541
1542 /**
1543  * sdr_find_window_center() - Find center of the working DQS window.
1544  * @grp:        Read/Write group
1545  * @work_bgn:   First working settings
1546  * @work_end:   Last working settings
1547  *
1548  * Find center of the working DQS enable window.
1549  */
1550 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1551                                   const u32 work_end)
1552 {
1553         u32 work_mid;
1554         int tmp_delay = 0;
1555         int i, p, d;
1556
1557         work_mid = (work_bgn + work_end) / 2;
1558
1559         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1560                    work_bgn, work_end, work_mid);
1561         /* Get the middle delay to be less than a VFIFO delay */
1562         tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1563
1564         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1565         work_mid %= tmp_delay;
1566         debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1567
1568         tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1569         if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1570                 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1571         p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1572
1573         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1574
1575         d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1576         if (d > IO_DQS_EN_DELAY_MAX)
1577                 d = IO_DQS_EN_DELAY_MAX;
1578         tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1579
1580         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1581
1582         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1583         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1584
1585         /*
1586          * push vfifo until we can successfully calibrate. We can do this
1587          * because the largest possible margin in 1 VFIFO cycle.
1588          */
1589         for (i = 0; i < VFIFO_SIZE; i++) {
1590                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
1591                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1592                                                              PASS_ONE_BIT,
1593                                                              0)) {
1594                         debug_cond(DLEVEL == 2,
1595                                    "%s:%d center: found: ptap=%u dtap=%u\n",
1596                                    __func__, __LINE__, p, d);
1597                         return 0;
1598                 }
1599
1600                 /* Fiddle with FIFO. */
1601                 rw_mgr_incr_vfifo(grp);
1602         }
1603
1604         debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1605                    __func__, __LINE__);
1606         return -EINVAL;
1607 }
1608
1609 /**
1610  * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1611  * @grp:        Read/Write Group
1612  *
1613  * Find a good DQS enable to use.
1614  */
1615 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
1616 {
1617         u32 d, p, i;
1618         u32 dtaps_per_ptap;
1619         u32 work_bgn, work_end;
1620         u32 found_passing_read, found_failing_read, initial_failing_dtap;
1621         int ret;
1622
1623         debug("%s:%d %u\n", __func__, __LINE__, grp);
1624
1625         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1626
1627         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1628         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1629
1630         /* Step 0: Determine number of delay taps for each phase tap. */
1631         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1632
1633         /* Step 1: First push vfifo until we get a failing read. */
1634         find_vfifo_failing_read(grp);
1635
1636         /* Step 2: Find first working phase, increment in ptaps. */
1637         work_bgn = 0;
1638         ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1639         if (ret)
1640                 return ret;
1641
1642         work_end = work_bgn;
1643
1644         /*
1645          * If d is 0 then the working window covers a phase tap and we can
1646          * follow the old procedure. Otherwise, we've found the beginning
1647          * and we need to increment the dtaps until we find the end.
1648          */
1649         if (d == 0) {
1650                 /*
1651                  * Step 3a: If we have room, back off by one and
1652                  *          increment in dtaps.
1653                  */
1654                 sdr_backup_phase(grp, &work_bgn, &p);
1655
1656                 /*
1657                  * Step 4a: go forward from working phase to non working
1658                  * phase, increment in ptaps.
1659                  */
1660                 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1661                 if (ret)
1662                         return ret;
1663
1664                 /* Step 5a: Back off one from last, increment in dtaps. */
1665
1666                 /* Special case code for backing up a phase */
1667                 if (p == 0) {
1668                         p = IO_DQS_EN_PHASE_MAX;
1669                         rw_mgr_decr_vfifo(grp);
1670                 } else {
1671                         p = p - 1;
1672                 }
1673
1674                 work_end -= IO_DELAY_PER_OPA_TAP;
1675                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1676
1677                 d = 0;
1678
1679                 debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
1680                            __func__, __LINE__, p);
1681         }
1682
1683         /* The dtap increment to find the failing edge is done here. */
1684         sdr_find_phase_delay(0, 1, grp, &work_end,
1685                              IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
1686
1687         /* Go back to working dtap */
1688         if (d != 0)
1689                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1690
1691         debug_cond(DLEVEL == 2,
1692                    "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1693                    __func__, __LINE__, p, d - 1, work_end);
1694
1695         if (work_end < work_bgn) {
1696                 /* nil range */
1697                 debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
1698                            __func__, __LINE__);
1699                 return -EINVAL;
1700         }
1701
1702         debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
1703                    __func__, __LINE__, work_bgn, work_end);
1704
1705         /*
1706          * We need to calculate the number of dtaps that equal a ptap.
1707          * To do that we'll back up a ptap and re-find the edge of the
1708          * window using dtaps
1709          */
1710         debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1711                    __func__, __LINE__);
1712
1713         /* Special case code for backing up a phase */
1714         if (p == 0) {
1715                 p = IO_DQS_EN_PHASE_MAX;
1716                 rw_mgr_decr_vfifo(grp);
1717                 debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
1718                            __func__, __LINE__, p);
1719         } else {
1720                 p = p - 1;
1721                 debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
1722                            __func__, __LINE__, p);
1723         }
1724
1725         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1726
1727         /*
1728          * Increase dtap until we first see a passing read (in case the
1729          * window is smaller than a ptap), and then a failing read to
1730          * mark the edge of the window again.
1731          */
1732
1733         /* Find a passing read. */
1734         debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
1735                    __func__, __LINE__);
1736
1737         initial_failing_dtap = d;
1738
1739         found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
1740         if (found_passing_read) {
1741                 /* Find a failing read. */
1742                 debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
1743                            __func__, __LINE__);
1744                 d++;
1745                 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1746                                                            &d);
1747         } else {
1748                 debug_cond(DLEVEL == 1,
1749                            "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1750                            __func__, __LINE__);
1751         }
1752
1753         /*
1754          * The dynamically calculated dtaps_per_ptap is only valid if we
1755          * found a passing/failing read. If we didn't, it means d hit the max
1756          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1757          * statically calculated value.
1758          */
1759         if (found_passing_read && found_failing_read)
1760                 dtaps_per_ptap = d - initial_failing_dtap;
1761
1762         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1763         debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1764                    __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
1765
1766         /* Step 6: Find the centre of the window. */
1767         ret = sdr_find_window_center(grp, work_bgn, work_end);
1768
1769         return ret;
1770 }
1771
1772 /* per-bit deskew DQ and center */
1773 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1774         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1775         uint32_t use_read_test, uint32_t update_fom)
1776 {
1777         uint32_t i, p, d, min_index;
1778         /*
1779          * Store these as signed since there are comparisons with
1780          * signed numbers.
1781          */
1782         uint32_t bit_chk;
1783         uint32_t sticky_bit_chk;
1784         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1785         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1786         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1787         int32_t mid;
1788         int32_t orig_mid_min, mid_min;
1789         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1790                 final_dqs_en;
1791         int32_t dq_margin, dqs_margin;
1792         uint32_t stop;
1793         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1794         uint32_t addr;
1795
1796         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1797
1798         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1799         start_dqs = readl(addr + (read_group << 2));
1800         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1801                 start_dqs_en = readl(addr + ((read_group << 2)
1802                                      - IO_DQS_EN_DELAY_OFFSET));
1803
1804         /* set the left and right edge of each bit to an illegal value */
1805         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1806         sticky_bit_chk = 0;
1807         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1808                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1809                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1810         }
1811
1812         /* Search for the left edge of the window for each bit */
1813         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1814                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1815
1816                 writel(0, &sdr_scc_mgr->update);
1817
1818                 /*
1819                  * Stop searching when the read test doesn't pass AND when
1820                  * we've seen a passing read on every bit.
1821                  */
1822                 if (use_read_test) {
1823                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1824                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1825                                 &bit_chk, 0, 0);
1826                 } else {
1827                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1828                                                         0, PASS_ONE_BIT,
1829                                                         &bit_chk, 0);
1830                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1831                                 (read_group - (write_group *
1832                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1833                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1834                         stop = (bit_chk == 0);
1835                 }
1836                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1837                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1838                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1839                            && %u", __func__, __LINE__, d,
1840                            sticky_bit_chk,
1841                         param->read_correct_mask, stop);
1842
1843                 if (stop == 1) {
1844                         break;
1845                 } else {
1846                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1847                                 if (bit_chk & 1) {
1848                                         /* Remember a passing test as the
1849                                         left_edge */
1850                                         left_edge[i] = d;
1851                                 } else {
1852                                         /* If a left edge has not been seen yet,
1853                                         then a future passing test will mark
1854                                         this edge as the right edge */
1855                                         if (left_edge[i] ==
1856                                                 IO_IO_IN_DELAY_MAX + 1) {
1857                                                 right_edge[i] = -(d + 1);
1858                                         }
1859                                 }
1860                                 bit_chk = bit_chk >> 1;
1861                         }
1862                 }
1863         }
1864
1865         /* Reset DQ delay chains to 0 */
1866         scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1867         sticky_bit_chk = 0;
1868         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1869                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1870                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1871                            i, left_edge[i], i, right_edge[i]);
1872
1873                 /*
1874                  * Check for cases where we haven't found the left edge,
1875                  * which makes our assignment of the the right edge invalid.
1876                  * Reset it to the illegal value.
1877                  */
1878                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1879                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1880                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1881                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1882                                    right_edge[%u]: %d\n", __func__, __LINE__,
1883                                    i, right_edge[i]);
1884                 }
1885
1886                 /*
1887                  * Reset sticky bit (except for bits where we have seen
1888                  * both the left and right edge).
1889                  */
1890                 sticky_bit_chk = sticky_bit_chk << 1;
1891                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1892                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1893                         sticky_bit_chk = sticky_bit_chk | 1;
1894                 }
1895
1896                 if (i == 0)
1897                         break;
1898         }
1899
1900         /* Search for the right edge of the window for each bit */
1901         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1902                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1903                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1904                         uint32_t delay = d + start_dqs_en;
1905                         if (delay > IO_DQS_EN_DELAY_MAX)
1906                                 delay = IO_DQS_EN_DELAY_MAX;
1907                         scc_mgr_set_dqs_en_delay(read_group, delay);
1908                 }
1909                 scc_mgr_load_dqs(read_group);
1910
1911                 writel(0, &sdr_scc_mgr->update);
1912
1913                 /*
1914                  * Stop searching when the read test doesn't pass AND when
1915                  * we've seen a passing read on every bit.
1916                  */
1917                 if (use_read_test) {
1918                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1919                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1920                                 &bit_chk, 0, 0);
1921                 } else {
1922                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1923                                                         0, PASS_ONE_BIT,
1924                                                         &bit_chk, 0);
1925                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1926                                 (read_group - (write_group *
1927                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1928                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1929                         stop = (bit_chk == 0);
1930                 }
1931                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1932                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1933
1934                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1935                            %u && %u", __func__, __LINE__, d,
1936                            sticky_bit_chk, param->read_correct_mask, stop);
1937
1938                 if (stop == 1) {
1939                         break;
1940                 } else {
1941                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1942                                 if (bit_chk & 1) {
1943                                         /* Remember a passing test as
1944                                         the right_edge */
1945                                         right_edge[i] = d;
1946                                 } else {
1947                                         if (d != 0) {
1948                                                 /* If a right edge has not been
1949                                                 seen yet, then a future passing
1950                                                 test will mark this edge as the
1951                                                 left edge */
1952                                                 if (right_edge[i] ==
1953                                                 IO_IO_IN_DELAY_MAX + 1) {
1954                                                         left_edge[i] = -(d + 1);
1955                                                 }
1956                                         } else {
1957                                                 /* d = 0 failed, but it passed
1958                                                 when testing the left edge,
1959                                                 so it must be marginal,
1960                                                 set it to -1 */
1961                                                 if (right_edge[i] ==
1962                                                         IO_IO_IN_DELAY_MAX + 1 &&
1963                                                         left_edge[i] !=
1964                                                         IO_IO_IN_DELAY_MAX
1965                                                         + 1) {
1966                                                         right_edge[i] = -1;
1967                                                 }
1968                                                 /* If a right edge has not been
1969                                                 seen yet, then a future passing
1970                                                 test will mark this edge as the
1971                                                 left edge */
1972                                                 else if (right_edge[i] ==
1973                                                         IO_IO_IN_DELAY_MAX +
1974                                                         1) {
1975                                                         left_edge[i] = -(d + 1);
1976                                                 }
1977                                         }
1978                                 }
1979
1980                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
1981                                            d=%u]: ", __func__, __LINE__, d);
1982                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
1983                                            (int)(bit_chk & 1), i, left_edge[i]);
1984                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
1985                                            right_edge[i]);
1986                                 bit_chk = bit_chk >> 1;
1987                         }
1988                 }
1989         }
1990
1991         /* Check that all bits have a window */
1992         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1993                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1994                            %d right_edge[%u]: %d", __func__, __LINE__,
1995                            i, left_edge[i], i, right_edge[i]);
1996                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
1997                         == IO_IO_IN_DELAY_MAX + 1)) {
1998                         /*
1999                          * Restore delay chain settings before letting the loop
2000                          * in rw_mgr_mem_calibrate_vfifo to retry different
2001                          * dqs/ck relationships.
2002                          */
2003                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2004                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2005                                 scc_mgr_set_dqs_en_delay(read_group,
2006                                                          start_dqs_en);
2007                         }
2008                         scc_mgr_load_dqs(read_group);
2009                         writel(0, &sdr_scc_mgr->update);
2010
2011                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2012                                    find edge [%u]: %d %d", __func__, __LINE__,
2013                                    i, left_edge[i], right_edge[i]);
2014                         if (use_read_test) {
2015                                 set_failing_group_stage(read_group *
2016                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2017                                         CAL_STAGE_VFIFO,
2018                                         CAL_SUBSTAGE_VFIFO_CENTER);
2019                         } else {
2020                                 set_failing_group_stage(read_group *
2021                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2022                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2023                                         CAL_SUBSTAGE_VFIFO_CENTER);
2024                         }
2025                         return 0;
2026                 }
2027         }
2028
2029         /* Find middle of window for each DQ bit */
2030         mid_min = left_edge[0] - right_edge[0];
2031         min_index = 0;
2032         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2033                 mid = left_edge[i] - right_edge[i];
2034                 if (mid < mid_min) {
2035                         mid_min = mid;
2036                         min_index = i;
2037                 }
2038         }
2039
2040         /*
2041          * -mid_min/2 represents the amount that we need to move DQS.
2042          * If mid_min is odd and positive we'll need to add one to
2043          * make sure the rounding in further calculations is correct
2044          * (always bias to the right), so just add 1 for all positive values.
2045          */
2046         if (mid_min > 0)
2047                 mid_min++;
2048
2049         mid_min = mid_min / 2;
2050
2051         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2052                    __func__, __LINE__, mid_min, min_index);
2053
2054         /* Determine the amount we can change DQS (which is -mid_min) */
2055         orig_mid_min = mid_min;
2056         new_dqs = start_dqs - mid_min;
2057         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2058                 new_dqs = IO_DQS_IN_DELAY_MAX;
2059         else if (new_dqs < 0)
2060                 new_dqs = 0;
2061
2062         mid_min = start_dqs - new_dqs;
2063         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2064                    mid_min, new_dqs);
2065
2066         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2067                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2068                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2069                 else if (start_dqs_en - mid_min < 0)
2070                         mid_min += start_dqs_en - mid_min;
2071         }
2072         new_dqs = start_dqs - mid_min;
2073
2074         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2075                    new_dqs=%d mid_min=%d\n", start_dqs,
2076                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2077                    new_dqs, mid_min);
2078
2079         /* Initialize data for export structures */
2080         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2081         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2082
2083         /* add delay to bring centre of all DQ windows to the same "level" */
2084         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2085                 /* Use values before divide by 2 to reduce round off error */
2086                 shift_dq = (left_edge[i] - right_edge[i] -
2087                         (left_edge[min_index] - right_edge[min_index]))/2  +
2088                         (orig_mid_min - mid_min);
2089
2090                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2091                            shift_dq[%u]=%d\n", i, shift_dq);
2092
2093                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2094                 temp_dq_in_delay1 = readl(addr + (p << 2));
2095                 temp_dq_in_delay2 = readl(addr + (i << 2));
2096
2097                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2098                         (int32_t)IO_IO_IN_DELAY_MAX) {
2099                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2100                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2101                         shift_dq = -(int32_t)temp_dq_in_delay1;
2102                 }
2103                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2104                            shift_dq[%u]=%d\n", i, shift_dq);
2105                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2106                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2107                 scc_mgr_load_dq(p);
2108
2109                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2110                            left_edge[i] - shift_dq + (-mid_min),
2111                            right_edge[i] + shift_dq - (-mid_min));
2112                 /* To determine values for export structures */
2113                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2114                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2115
2116                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2117                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2118         }
2119
2120         final_dqs = new_dqs;
2121         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2122                 final_dqs_en = start_dqs_en - mid_min;
2123
2124         /* Move DQS-en */
2125         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2126                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2127                 scc_mgr_load_dqs(read_group);
2128         }
2129
2130         /* Move DQS */
2131         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2132         scc_mgr_load_dqs(read_group);
2133         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2134                    dqs_margin=%d", __func__, __LINE__,
2135                    dq_margin, dqs_margin);
2136
2137         /*
2138          * Do not remove this line as it makes sure all of our decisions
2139          * have been applied. Apply the update bit.
2140          */
2141         writel(0, &sdr_scc_mgr->update);
2142
2143         return (dq_margin >= 0) && (dqs_margin >= 0);
2144 }
2145
2146 /**
2147  * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2148  * @rw_group:   Read/Write Group
2149  * @phase:      DQ/DQS phase
2150  *
2151  * Because initially no communication ca be reliably performed with the memory
2152  * device, the sequencer uses a guaranteed write mechanism to write data into
2153  * the memory device.
2154  */
2155 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2156                                                  const u32 phase)
2157 {
2158         int ret;
2159
2160         /* Set a particular DQ/DQS phase. */
2161         scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2162
2163         debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2164                    __func__, __LINE__, rw_group, phase);
2165
2166         /*
2167          * Altera EMI_RM 2015.05.04 :: Figure 1-25
2168          * Load up the patterns used by read calibration using the
2169          * current DQDQS phase.
2170          */
2171         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2172
2173         if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2174                 return 0;
2175
2176         /*
2177          * Altera EMI_RM 2015.05.04 :: Figure 1-26
2178          * Back-to-Back reads of the patterns used for calibration.
2179          */
2180         ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2181         if (ret)
2182                 debug_cond(DLEVEL == 1,
2183                            "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2184                            __func__, __LINE__, rw_group, phase);
2185         return ret;
2186 }
2187
2188 /**
2189  * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2190  * @rw_group:   Read/Write Group
2191  * @test_bgn:   Rank at which the test begins
2192  *
2193  * DQS enable calibration ensures reliable capture of the DQ signal without
2194  * glitches on the DQS line.
2195  */
2196 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2197                                                        const u32 test_bgn)
2198 {
2199         /*
2200          * Altera EMI_RM 2015.05.04 :: Figure 1-27
2201          * DQS and DQS Eanble Signal Relationships.
2202          */
2203
2204         /* We start at zero, so have one less dq to devide among */
2205         const u32 delay_step = IO_IO_IN_DELAY_MAX /
2206                                (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2207         int ret;
2208         u32 i, p, d, r;
2209
2210         debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2211
2212         /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2213         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2214              r += NUM_RANKS_PER_SHADOW_REG) {
2215                 for (i = 0, p = test_bgn, d = 0;
2216                      i < RW_MGR_MEM_DQ_PER_READ_DQS;
2217                      i++, p++, d += delay_step) {
2218                         debug_cond(DLEVEL == 1,
2219                                    "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2220                                    __func__, __LINE__, rw_group, r, i, p, d);
2221
2222                         scc_mgr_set_dq_in_delay(p, d);
2223                         scc_mgr_load_dq(p);
2224                 }
2225
2226                 writel(0, &sdr_scc_mgr->update);
2227         }
2228
2229         /*
2230          * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2231          * dq_in_delay values
2232          */
2233         ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2234
2235         debug_cond(DLEVEL == 1,
2236                    "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2237                    __func__, __LINE__, rw_group, !ret);
2238
2239         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2240              r += NUM_RANKS_PER_SHADOW_REG) {
2241                 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2242                 writel(0, &sdr_scc_mgr->update);
2243         }
2244
2245         return ret;
2246 }
2247
2248 /**
2249  * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2250  * @rw_group:           Read/Write Group
2251  * @test_bgn:           Rank at which the test begins
2252  * @use_read_test:      Perform a read test
2253  * @update_fom:         Update FOM
2254  *
2255  * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2256  * within a group.
2257  */
2258 static int
2259 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2260                                       const int use_read_test,
2261                                       const int update_fom)
2262
2263 {
2264         int ret, grp_calibrated;
2265         u32 rank_bgn, sr;
2266
2267         /*
2268          * Altera EMI_RM 2015.05.04 :: Figure 1-28
2269          * Read per-bit deskew can be done on a per shadow register basis.
2270          */
2271         grp_calibrated = 1;
2272         for (rank_bgn = 0, sr = 0;
2273              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2274              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2275                 /* Check if this set of ranks should be skipped entirely. */
2276                 if (param->skip_shadow_regs[sr])
2277                         continue;
2278
2279                 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2280                                                         rw_group, test_bgn,
2281                                                         use_read_test,
2282                                                         update_fom);
2283                 if (ret)
2284                         continue;
2285
2286                 grp_calibrated = 0;
2287         }
2288
2289         if (!grp_calibrated)
2290                 return -EIO;
2291
2292         return 0;
2293 }
2294
2295 /**
2296  * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2297  * @rw_group:           Read/Write Group
2298  * @test_bgn:           Rank at which the test begins
2299  *
2300  * Stage 1: Calibrate the read valid prediction FIFO.
2301  *
2302  * This function implements UniPHY calibration Stage 1, as explained in
2303  * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2304  *
2305  * - read valid prediction will consist of finding:
2306  *   - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2307  *   - DQS input phase  and DQS input delay (DQ/DQS Centering)
2308  *  - we also do a per-bit deskew on the DQ lines.
2309  */
2310 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2311 {
2312         uint32_t p, d;
2313         uint32_t dtaps_per_ptap;
2314         uint32_t failed_substage;
2315
2316         int ret;
2317
2318         debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2319
2320         /* Update info for sims */
2321         reg_file_set_group(rw_group);
2322         reg_file_set_stage(CAL_STAGE_VFIFO);
2323         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2324
2325         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2326
2327         /* USER Determine number of delay taps for each phase tap. */
2328         dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2329                                       IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2330
2331         for (d = 0; d <= dtaps_per_ptap; d += 2) {
2332                 /*
2333                  * In RLDRAMX we may be messing the delay of pins in
2334                  * the same write rw_group but outside of the current read
2335                  * the rw_group, but that's ok because we haven't calibrated
2336                  * output side yet.
2337                  */
2338                 if (d > 0) {
2339                         scc_mgr_apply_group_all_out_delay_add_all_ranks(
2340                                                                 rw_group, d);
2341                 }
2342
2343                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2344                         /* 1) Guaranteed Write */
2345                         ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2346                         if (ret)
2347                                 break;
2348
2349                         /* 2) DQS Enable Calibration */
2350                         ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2351                                                                           test_bgn);
2352                         if (ret) {
2353                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2354                                 continue;
2355                         }
2356
2357                         /* 3) Centering DQ/DQS */
2358                         /*
2359                          * If doing read after write calibration, do not update
2360                          * FOM now. Do it then.
2361                          */
2362                         ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2363                                                                 test_bgn, 1, 0);
2364                         if (ret) {
2365                                 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2366                                 continue;
2367                         }
2368
2369                         /* All done. */
2370                         goto cal_done_ok;
2371                 }
2372         }
2373
2374         /* Calibration Stage 1 failed. */
2375         set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2376         return 0;
2377
2378         /* Calibration Stage 1 completed OK. */
2379 cal_done_ok:
2380         /*
2381          * Reset the delay chains back to zero if they have moved > 1
2382          * (check for > 1 because loop will increase d even when pass in
2383          * first case).
2384          */
2385         if (d > 2)
2386                 scc_mgr_zero_group(rw_group, 1);
2387
2388         return 1;
2389 }
2390
2391 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2392 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2393                                                uint32_t test_bgn)
2394 {
2395         uint32_t rank_bgn, sr;
2396         uint32_t grp_calibrated;
2397         uint32_t write_group;
2398
2399         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2400
2401         /* update info for sims */
2402
2403         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2404         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2405
2406         write_group = read_group;
2407
2408         /* update info for sims */
2409         reg_file_set_group(read_group);
2410
2411         grp_calibrated = 1;
2412         /* Read per-bit deskew can be done on a per shadow register basis */
2413         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2414                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2415                 /* Determine if this set of ranks should be skipped entirely */
2416                 if (!param->skip_shadow_regs[sr]) {
2417                 /* This is the last calibration round, update FOM here */
2418                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2419                                                                 write_group,
2420                                                                 read_group,
2421                                                                 test_bgn, 0,
2422                                                                 1)) {
2423                                 grp_calibrated = 0;
2424                         }
2425                 }
2426         }
2427
2428
2429         if (grp_calibrated == 0) {
2430                 set_failing_group_stage(write_group,
2431                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2432                                         CAL_SUBSTAGE_VFIFO_CENTER);
2433                 return 0;
2434         }
2435
2436         return 1;
2437 }
2438
2439 /* Calibrate LFIFO to find smallest read latency */
2440 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2441 {
2442         uint32_t found_one;
2443
2444         debug("%s:%d\n", __func__, __LINE__);
2445
2446         /* update info for sims */
2447         reg_file_set_stage(CAL_STAGE_LFIFO);
2448         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2449
2450         /* Load up the patterns used by read calibration for all ranks */
2451         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2452         found_one = 0;
2453
2454         do {
2455                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2456                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2457                            __func__, __LINE__, gbl->curr_read_lat);
2458
2459                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2460                                                               NUM_READ_TESTS,
2461                                                               PASS_ALL_BITS,
2462                                                               1)) {
2463                         break;
2464                 }
2465
2466                 found_one = 1;
2467                 /* reduce read latency and see if things are working */
2468                 /* correctly */
2469                 gbl->curr_read_lat--;
2470         } while (gbl->curr_read_lat > 0);
2471
2472         /* reset the fifos to get pointers to known state */
2473
2474         writel(0, &phy_mgr_cmd->fifo_reset);
2475
2476         if (found_one) {
2477                 /* add a fudge factor to the read latency that was determined */
2478                 gbl->curr_read_lat += 2;
2479                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2480                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2481                            read_lat=%u\n", __func__, __LINE__,
2482                            gbl->curr_read_lat);
2483                 return 1;
2484         } else {
2485                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2486                                         CAL_SUBSTAGE_READ_LATENCY);
2487
2488                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2489                            read_lat=%u\n", __func__, __LINE__,
2490                            gbl->curr_read_lat);
2491                 return 0;
2492         }
2493 }
2494
2495 /*
2496  * issue write test command.
2497  * two variants are provided. one that just tests a write pattern and
2498  * another that tests datamask functionality.
2499  */
2500 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2501                                                   uint32_t test_dm)
2502 {
2503         uint32_t mcc_instruction;
2504         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2505                 ENABLE_SUPER_QUICK_CALIBRATION);
2506         uint32_t rw_wl_nop_cycles;
2507         uint32_t addr;
2508
2509         /*
2510          * Set counter and jump addresses for the right
2511          * number of NOP cycles.
2512          * The number of supported NOP cycles can range from -1 to infinity
2513          * Three different cases are handled:
2514          *
2515          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2516          *    mechanism will be used to insert the right number of NOPs
2517          *
2518          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2519          *    issuing the write command will jump straight to the
2520          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2521          *    data (for RLD), skipping
2522          *    the NOP micro-instruction all together
2523          *
2524          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2525          *    turned on in the same micro-instruction that issues the write
2526          *    command. Then we need
2527          *    to directly jump to the micro-instruction that sends out the data
2528          *
2529          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2530          *       (2 and 3). One jump-counter (0) is used to perform multiple
2531          *       write-read operations.
2532          *       one counter left to issue this command in "multiple-group" mode
2533          */
2534
2535         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2536
2537         if (rw_wl_nop_cycles == -1) {
2538                 /*
2539                  * CNTR 2 - We want to execute the special write operation that
2540                  * turns on DQS right away and then skip directly to the
2541                  * instruction that sends out the data. We set the counter to a
2542                  * large number so that the jump is always taken.
2543                  */
2544                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2545
2546                 /* CNTR 3 - Not used */
2547                 if (test_dm) {
2548                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2549                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2550                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2551                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2552                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2553                 } else {
2554                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2555                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2556                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2557                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2558                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2559                 }
2560         } else if (rw_wl_nop_cycles == 0) {
2561                 /*
2562                  * CNTR 2 - We want to skip the NOP operation and go straight
2563                  * to the DQS enable instruction. We set the counter to a large
2564                  * number so that the jump is always taken.
2565                  */
2566                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2567
2568                 /* CNTR 3 - Not used */
2569                 if (test_dm) {
2570                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2571                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2572                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2573                 } else {
2574                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2575                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2576                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2577                 }
2578         } else {
2579                 /*
2580                  * CNTR 2 - In this case we want to execute the next instruction
2581                  * and NOT take the jump. So we set the counter to 0. The jump
2582                  * address doesn't count.
2583                  */
2584                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2585                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2586
2587                 /*
2588                  * CNTR 3 - Set the nop counter to the number of cycles we
2589                  * need to loop for, minus 1.
2590                  */
2591                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2592                 if (test_dm) {
2593                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2594                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2595                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2596                 } else {
2597                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2598                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2599                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2600                 }
2601         }
2602
2603         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2604                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2605
2606         if (quick_write_mode)
2607                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2608         else
2609                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2610
2611         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2612
2613         /*
2614          * CNTR 1 - This is used to ensure enough time elapses
2615          * for read data to come back.
2616          */
2617         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2618
2619         if (test_dm) {
2620                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2621                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2622         } else {
2623                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2624                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2625         }
2626
2627         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2628         writel(mcc_instruction, addr + (group << 2));
2629 }
2630
2631 /* Test writes, can check for a single bit pass or multiple bit pass */
2632 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2633         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2634         uint32_t *bit_chk, uint32_t all_ranks)
2635 {
2636         uint32_t r;
2637         uint32_t correct_mask_vg;
2638         uint32_t tmp_bit_chk;
2639         uint32_t vg;
2640         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2641                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2642         uint32_t addr_rw_mgr;
2643         uint32_t base_rw_mgr;
2644
2645         *bit_chk = param->write_correct_mask;
2646         correct_mask_vg = param->write_correct_mask_vg;
2647
2648         for (r = rank_bgn; r < rank_end; r++) {
2649                 if (param->skip_ranks[r]) {
2650                         /* request to skip the rank */
2651                         continue;
2652                 }
2653
2654                 /* set rank */
2655                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2656
2657                 tmp_bit_chk = 0;
2658                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2659                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2660                         /* reset the fifos to get pointers to known state */
2661                         writel(0, &phy_mgr_cmd->fifo_reset);
2662
2663                         tmp_bit_chk = tmp_bit_chk <<
2664                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2665                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2666                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2667                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2668                                 use_dm);
2669
2670                         base_rw_mgr = readl(addr_rw_mgr);
2671                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2672                         if (vg == 0)
2673                                 break;
2674                 }
2675                 *bit_chk &= tmp_bit_chk;
2676         }
2677
2678         if (all_correct) {
2679                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2680                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2681                            %u => %lu", write_group, use_dm,
2682                            *bit_chk, param->write_correct_mask,
2683                            (long unsigned int)(*bit_chk ==
2684                            param->write_correct_mask));
2685                 return *bit_chk == param->write_correct_mask;
2686         } else {
2687                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2688                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2689                        write_group, use_dm, *bit_chk);
2690                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2691                         (long unsigned int)(*bit_chk != 0));
2692                 return *bit_chk != 0x00;
2693         }
2694 }
2695
2696 /*
2697  * center all windows. do per-bit-deskew to possibly increase size of
2698  * certain windows.
2699  */
2700 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2701         uint32_t write_group, uint32_t test_bgn)
2702 {
2703         uint32_t i, p, min_index;
2704         int32_t d;
2705         /*
2706          * Store these as signed since there are comparisons with
2707          * signed numbers.
2708          */
2709         uint32_t bit_chk;
2710         uint32_t sticky_bit_chk;
2711         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2712         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2713         int32_t mid;
2714         int32_t mid_min, orig_mid_min;
2715         int32_t new_dqs, start_dqs, shift_dq;
2716         int32_t dq_margin, dqs_margin, dm_margin;
2717         uint32_t stop;
2718         uint32_t temp_dq_out1_delay;
2719         uint32_t addr;
2720
2721         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2722
2723         dm_margin = 0;
2724
2725         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2726         start_dqs = readl(addr +
2727                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2728
2729         /* per-bit deskew */
2730
2731         /*
2732          * set the left and right edge of each bit to an illegal value
2733          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2734          */
2735         sticky_bit_chk = 0;
2736         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2737                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2738                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2739         }
2740
2741         /* Search for the left edge of the window for each bit */
2742         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2743                 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2744
2745                 writel(0, &sdr_scc_mgr->update);
2746
2747                 /*
2748                  * Stop searching when the read test doesn't pass AND when
2749                  * we've seen a passing read on every bit.
2750                  */
2751                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2752                         0, PASS_ONE_BIT, &bit_chk, 0);
2753                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2754                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2755                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2756                            == %u && %u [bit_chk= %u ]\n",
2757                         d, sticky_bit_chk, param->write_correct_mask,
2758                         stop, bit_chk);
2759
2760                 if (stop == 1) {
2761                         break;
2762                 } else {
2763                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2764                                 if (bit_chk & 1) {
2765                                         /*
2766                                          * Remember a passing test as the
2767                                          * left_edge.
2768                                          */
2769                                         left_edge[i] = d;
2770                                 } else {
2771                                         /*
2772                                          * If a left edge has not been seen
2773                                          * yet, then a future passing test will
2774                                          * mark this edge as the right edge.
2775                                          */
2776                                         if (left_edge[i] ==
2777                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2778                                                 right_edge[i] = -(d + 1);
2779                                         }
2780                                 }
2781                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2782                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2783                                            (int)(bit_chk & 1), i, left_edge[i]);
2784                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2785                                        right_edge[i]);
2786                                 bit_chk = bit_chk >> 1;
2787                         }
2788                 }
2789         }
2790
2791         /* Reset DQ delay chains to 0 */
2792         scc_mgr_apply_group_dq_out1_delay(0);
2793         sticky_bit_chk = 0;
2794         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2795                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2796                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2797                            i, left_edge[i], i, right_edge[i]);
2798
2799                 /*
2800                  * Check for cases where we haven't found the left edge,
2801                  * which makes our assignment of the the right edge invalid.
2802                  * Reset it to the illegal value.
2803                  */
2804                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2805                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2806                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2807                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2808                                    right_edge[%u]: %d\n", __func__, __LINE__,
2809                                    i, right_edge[i]);
2810                 }
2811
2812                 /*
2813                  * Reset sticky bit (except for bits where we have
2814                  * seen the left edge).
2815                  */
2816                 sticky_bit_chk = sticky_bit_chk << 1;
2817                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2818                         sticky_bit_chk = sticky_bit_chk | 1;
2819
2820                 if (i == 0)
2821                         break;
2822         }
2823
2824         /* Search for the right edge of the window for each bit */
2825         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2826                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2827                                                         d + start_dqs);
2828
2829                 writel(0, &sdr_scc_mgr->update);
2830
2831                 /*
2832                  * Stop searching when the read test doesn't pass AND when
2833                  * we've seen a passing read on every bit.
2834                  */
2835                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2836                         0, PASS_ONE_BIT, &bit_chk, 0);
2837
2838                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2839                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2840
2841                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2842                            %u && %u\n", d, sticky_bit_chk,
2843                            param->write_correct_mask, stop);
2844
2845                 if (stop == 1) {
2846                         if (d == 0) {
2847                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2848                                         i++) {
2849                                         /* d = 0 failed, but it passed when
2850                                         testing the left edge, so it must be
2851                                         marginal, set it to -1 */
2852                                         if (right_edge[i] ==
2853                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2854                                                 left_edge[i] !=
2855                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2856                                                 right_edge[i] = -1;
2857                                         }
2858                                 }
2859                         }
2860                         break;
2861                 } else {
2862                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2863                                 if (bit_chk & 1) {
2864                                         /*
2865                                          * Remember a passing test as
2866                                          * the right_edge.
2867                                          */
2868                                         right_edge[i] = d;
2869                                 } else {
2870                                         if (d != 0) {
2871                                                 /*
2872                                                  * If a right edge has not
2873                                                  * been seen yet, then a future
2874                                                  * passing test will mark this
2875                                                  * edge as the left edge.
2876                                                  */
2877                                                 if (right_edge[i] ==
2878                                                     IO_IO_OUT1_DELAY_MAX + 1)
2879                                                         left_edge[i] = -(d + 1);
2880                                         } else {
2881                                                 /*
2882                                                  * d = 0 failed, but it passed
2883                                                  * when testing the left edge,
2884                                                  * so it must be marginal, set
2885                                                  * it to -1.
2886                                                  */
2887                                                 if (right_edge[i] ==
2888                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2889                                                     left_edge[i] !=
2890                                                     IO_IO_OUT1_DELAY_MAX + 1)
2891                                                         right_edge[i] = -1;
2892                                                 /*
2893                                                  * If a right edge has not been
2894                                                  * seen yet, then a future
2895                                                  * passing test will mark this
2896                                                  * edge as the left edge.
2897                                                  */
2898                                                 else if (right_edge[i] ==
2899                                                         IO_IO_OUT1_DELAY_MAX +
2900                                                         1)
2901                                                         left_edge[i] = -(d + 1);
2902                                         }
2903                                 }
2904                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2905                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2906                                            (int)(bit_chk & 1), i, left_edge[i]);
2907                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2908                                            right_edge[i]);
2909                                 bit_chk = bit_chk >> 1;
2910                         }
2911                 }
2912         }
2913
2914         /* Check that all bits have a window */
2915         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2916                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2917                            %d right_edge[%u]: %d", __func__, __LINE__,
2918                            i, left_edge[i], i, right_edge[i]);
2919                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2920                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2921                         set_failing_group_stage(test_bgn + i,
2922                                                 CAL_STAGE_WRITES,
2923                                                 CAL_SUBSTAGE_WRITES_CENTER);
2924                         return 0;
2925                 }
2926         }
2927
2928         /* Find middle of window for each DQ bit */
2929         mid_min = left_edge[0] - right_edge[0];
2930         min_index = 0;
2931         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2932                 mid = left_edge[i] - right_edge[i];
2933                 if (mid < mid_min) {
2934                         mid_min = mid;
2935                         min_index = i;
2936                 }
2937         }
2938
2939         /*
2940          * -mid_min/2 represents the amount that we need to move DQS.
2941          * If mid_min is odd and positive we'll need to add one to
2942          * make sure the rounding in further calculations is correct
2943          * (always bias to the right), so just add 1 for all positive values.
2944          */
2945         if (mid_min > 0)
2946                 mid_min++;
2947         mid_min = mid_min / 2;
2948         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2949                    __LINE__, mid_min);
2950
2951         /* Determine the amount we can change DQS (which is -mid_min) */
2952         orig_mid_min = mid_min;
2953         new_dqs = start_dqs;
2954         mid_min = 0;
2955         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2956                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2957         /* Initialize data for export structures */
2958         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2959         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2960
2961         /* add delay to bring centre of all DQ windows to the same "level" */
2962         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2963                 /* Use values before divide by 2 to reduce round off error */
2964                 shift_dq = (left_edge[i] - right_edge[i] -
2965                         (left_edge[min_index] - right_edge[min_index]))/2  +
2966                 (orig_mid_min - mid_min);
2967
2968                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2969                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2970
2971                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2972                 temp_dq_out1_delay = readl(addr + (i << 2));
2973                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2974                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2975                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2976                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2977                         shift_dq = -(int32_t)temp_dq_out1_delay;
2978                 }
2979                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2980                            i, shift_dq);
2981                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2982                 scc_mgr_load_dq(i);
2983
2984                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2985                            left_edge[i] - shift_dq + (-mid_min),
2986                            right_edge[i] + shift_dq - (-mid_min));
2987                 /* To determine values for export structures */
2988                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2989                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2990
2991                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2992                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2993         }
2994
2995         /* Move DQS */
2996         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2997         writel(0, &sdr_scc_mgr->update);
2998
2999         /* Centre DM */
3000         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3001
3002         /*
3003          * set the left and right edge of each bit to an illegal value,
3004          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3005          */
3006         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
3007         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3008         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3009         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3010         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3011         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3012         int32_t win_best = 0;
3013
3014         /* Search for the/part of the window with DM shift */
3015         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3016                 scc_mgr_apply_group_dm_out1_delay(d);
3017                 writel(0, &sdr_scc_mgr->update);
3018
3019                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3020                                                     PASS_ALL_BITS, &bit_chk,
3021                                                     0)) {
3022                         /* USE Set current end of the window */
3023                         end_curr = -d;
3024                         /*
3025                          * If a starting edge of our window has not been seen
3026                          * this is our current start of the DM window.
3027                          */
3028                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3029                                 bgn_curr = -d;
3030
3031                         /*
3032                          * If current window is bigger than best seen.
3033                          * Set best seen to be current window.
3034                          */
3035                         if ((end_curr-bgn_curr+1) > win_best) {
3036                                 win_best = end_curr-bgn_curr+1;
3037                                 bgn_best = bgn_curr;
3038                                 end_best = end_curr;
3039                         }
3040                 } else {
3041                         /* We just saw a failing test. Reset temp edge */
3042                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3043                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3044                         }
3045                 }
3046
3047
3048         /* Reset DM delay chains to 0 */
3049         scc_mgr_apply_group_dm_out1_delay(0);
3050
3051         /*
3052          * Check to see if the current window nudges up aganist 0 delay.
3053          * If so we need to continue the search by shifting DQS otherwise DQS
3054          * search begins as a new search. */
3055         if (end_curr != 0) {
3056                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3057                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3058         }
3059
3060         /* Search for the/part of the window with DQS shifts */
3061         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3062                 /*
3063                  * Note: This only shifts DQS, so are we limiting ourselve to
3064                  * width of DQ unnecessarily.
3065                  */
3066                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3067                                                         d + new_dqs);
3068
3069                 writel(0, &sdr_scc_mgr->update);
3070                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3071                                                     PASS_ALL_BITS, &bit_chk,
3072                                                     0)) {
3073                         /* USE Set current end of the window */
3074                         end_curr = d;
3075                         /*
3076                          * If a beginning edge of our window has not been seen
3077                          * this is our current begin of the DM window.
3078                          */
3079                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3080                                 bgn_curr = d;
3081
3082                         /*
3083                          * If current window is bigger than best seen. Set best
3084                          * seen to be current window.
3085                          */
3086                         if ((end_curr-bgn_curr+1) > win_best) {
3087                                 win_best = end_curr-bgn_curr+1;
3088                                 bgn_best = bgn_curr;
3089                                 end_best = end_curr;
3090                         }
3091                 } else {
3092                         /* We just saw a failing test. Reset temp edge */
3093                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3094                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3095
3096                         /* Early exit optimization: if ther remaining delay
3097                         chain space is less than already seen largest window
3098                         we can exit */
3099                         if ((win_best-1) >
3100                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3101                                         break;
3102                                 }
3103                         }
3104                 }
3105
3106         /* assign left and right edge for cal and reporting; */
3107         left_edge[0] = -1*bgn_best;
3108         right_edge[0] = end_best;
3109
3110         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3111                    __LINE__, left_edge[0], right_edge[0]);
3112
3113         /* Move DQS (back to orig) */
3114         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3115
3116         /* Move DM */
3117
3118         /* Find middle of window for the DM bit */
3119         mid = (left_edge[0] - right_edge[0]) / 2;
3120
3121         /* only move right, since we are not moving DQS/DQ */
3122         if (mid < 0)
3123                 mid = 0;
3124
3125         /* dm_marign should fail if we never find a window */
3126         if (win_best == 0)
3127                 dm_margin = -1;
3128         else
3129                 dm_margin = left_edge[0] - mid;
3130
3131         scc_mgr_apply_group_dm_out1_delay(mid);
3132         writel(0, &sdr_scc_mgr->update);
3133
3134         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3135                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3136                    right_edge[0], mid, dm_margin);
3137         /* Export values */
3138         gbl->fom_out += dq_margin + dqs_margin;
3139
3140         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3141                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3142                    dq_margin, dqs_margin, dm_margin);
3143
3144         /*
3145          * Do not remove this line as it makes sure all of our
3146          * decisions have been applied.
3147          */
3148         writel(0, &sdr_scc_mgr->update);
3149         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3150 }
3151
3152 /* calibrate the write operations */
3153 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3154         uint32_t test_bgn)
3155 {
3156         /* update info for sims */
3157         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3158
3159         reg_file_set_stage(CAL_STAGE_WRITES);
3160         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3161
3162         reg_file_set_group(g);
3163
3164         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3165                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3166                                         CAL_SUBSTAGE_WRITES_CENTER);
3167                 return 0;
3168         }
3169
3170         return 1;
3171 }
3172
3173 /**
3174  * mem_precharge_and_activate() - Precharge all banks and activate
3175  *
3176  * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3177  */
3178 static void mem_precharge_and_activate(void)
3179 {
3180         int r;
3181
3182         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3183                 /* Test if the rank should be skipped. */
3184                 if (param->skip_ranks[r])
3185                         continue;
3186
3187                 /* Set rank. */
3188                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3189
3190                 /* Precharge all banks. */
3191                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3192                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3193
3194                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3195                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3196                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3197
3198                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3199                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3200                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3201
3202                 /* Activate rows. */
3203                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3204                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3205         }
3206 }
3207
3208 /**
3209  * mem_init_latency() - Configure memory RLAT and WLAT settings
3210  *
3211  * Configure memory RLAT and WLAT parameters.
3212  */
3213 static void mem_init_latency(void)
3214 {
3215         /*
3216          * For AV/CV, LFIFO is hardened and always runs at full rate
3217          * so max latency in AFI clocks, used here, is correspondingly
3218          * smaller.
3219          */
3220         const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3221         u32 rlat, wlat;
3222
3223         debug("%s:%d\n", __func__, __LINE__);
3224
3225         /*
3226          * Read in write latency.
3227          * WL for Hard PHY does not include additive latency.
3228          */
3229         wlat = readl(&data_mgr->t_wl_add);
3230         wlat += readl(&data_mgr->mem_t_add);
3231
3232         gbl->rw_wl_nop_cycles = wlat - 1;
3233
3234         /* Read in readl latency. */
3235         rlat = readl(&data_mgr->t_rl_add);
3236
3237         /* Set a pretty high read latency initially. */
3238         gbl->curr_read_lat = rlat + 16;
3239         if (gbl->curr_read_lat > max_latency)
3240                 gbl->curr_read_lat = max_latency;
3241
3242         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3243
3244         /* Advertise write latency. */
3245         writel(wlat, &phy_mgr_cfg->afi_wlat);
3246 }
3247
3248 /**
3249  * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3250  *
3251  * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3252  */
3253 static void mem_skip_calibrate(void)
3254 {
3255         uint32_t vfifo_offset;
3256         uint32_t i, j, r;
3257
3258         debug("%s:%d\n", __func__, __LINE__);
3259         /* Need to update every shadow register set used by the interface */
3260         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3261              r += NUM_RANKS_PER_SHADOW_REG) {
3262                 /*
3263                  * Set output phase alignment settings appropriate for
3264                  * skip calibration.
3265                  */
3266                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3267                         scc_mgr_set_dqs_en_phase(i, 0);
3268 #if IO_DLL_CHAIN_LENGTH == 6
3269                         scc_mgr_set_dqdqs_output_phase(i, 6);
3270 #else
3271                         scc_mgr_set_dqdqs_output_phase(i, 7);
3272 #endif
3273                         /*
3274                          * Case:33398
3275                          *
3276                          * Write data arrives to the I/O two cycles before write
3277                          * latency is reached (720 deg).
3278                          *   -> due to bit-slip in a/c bus
3279                          *   -> to allow board skew where dqs is longer than ck
3280                          *      -> how often can this happen!?
3281                          *      -> can claim back some ptaps for high freq
3282                          *       support if we can relax this, but i digress...
3283                          *
3284                          * The write_clk leads mem_ck by 90 deg
3285                          * The minimum ptap of the OPA is 180 deg
3286                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3287                          * The write_clk is always delayed by 2 ptaps
3288                          *
3289                          * Hence, to make DQS aligned to CK, we need to delay
3290                          * DQS by:
3291                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3292                          *
3293                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3294                          * gives us the number of ptaps, which simplies to:
3295                          *
3296                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3297                          */
3298                         scc_mgr_set_dqdqs_output_phase(i,
3299                                         1.25 * IO_DLL_CHAIN_LENGTH - 2);
3300                 }
3301                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3302                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3303
3304                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3305                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3306                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3307                 }
3308                 writel(0xff, &sdr_scc_mgr->dq_ena);
3309                 writel(0xff, &sdr_scc_mgr->dm_ena);
3310                 writel(0, &sdr_scc_mgr->update);
3311         }
3312
3313         /* Compensate for simulation model behaviour */
3314         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3315                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3316                 scc_mgr_load_dqs(i);
3317         }
3318         writel(0, &sdr_scc_mgr->update);
3319
3320         /*
3321          * ArriaV has hard FIFOs that can only be initialized by incrementing
3322          * in sequencer.
3323          */
3324         vfifo_offset = CALIB_VFIFO_OFFSET;
3325         for (j = 0; j < vfifo_offset; j++)
3326                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3327         writel(0, &phy_mgr_cmd->fifo_reset);
3328
3329         /*
3330          * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3331          * setting from generation-time constant.
3332          */
3333         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3334         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3335 }
3336
3337 /**
3338  * mem_calibrate() - Memory calibration entry point.
3339  *
3340  * Perform memory calibration.
3341  */
3342 static uint32_t mem_calibrate(void)
3343 {
3344         uint32_t i;
3345         uint32_t rank_bgn, sr;
3346         uint32_t write_group, write_test_bgn;
3347         uint32_t read_group, read_test_bgn;
3348         uint32_t run_groups, current_run;
3349         uint32_t failing_groups = 0;
3350         uint32_t group_failed = 0;
3351
3352         const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3353                                 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3354
3355         debug("%s:%d\n", __func__, __LINE__);
3356
3357         /* Initialize the data settings */
3358         gbl->error_substage = CAL_SUBSTAGE_NIL;
3359         gbl->error_stage = CAL_STAGE_NIL;
3360         gbl->error_group = 0xff;
3361         gbl->fom_in = 0;
3362         gbl->fom_out = 0;
3363
3364         /* Initialize WLAT and RLAT. */
3365         mem_init_latency();
3366
3367         /* Initialize bit slips. */
3368         mem_precharge_and_activate();
3369
3370         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3371                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3372                           SCC_MGR_GROUP_COUNTER_OFFSET);
3373                 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3374                 if (i == 0)
3375                         scc_mgr_set_hhp_extras();
3376
3377                 scc_set_bypass_mode(i);
3378         }
3379
3380         /* Calibration is skipped. */
3381         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3382                 /*
3383                  * Set VFIFO and LFIFO to instant-on settings in skip
3384                  * calibration mode.
3385                  */
3386                 mem_skip_calibrate();
3387
3388                 /*
3389                  * Do not remove this line as it makes sure all of our
3390                  * decisions have been applied.
3391                  */
3392                 writel(0, &sdr_scc_mgr->update);
3393                 return 1;
3394         }
3395
3396         /* Calibration is not skipped. */
3397         for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3398                 /*
3399                  * Zero all delay chain/phase settings for all
3400                  * groups and all shadow register sets.
3401                  */
3402                 scc_mgr_zero_all();
3403
3404                 run_groups = ~param->skip_groups;
3405
3406                 for (write_group = 0, write_test_bgn = 0; write_group
3407                         < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3408                         write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3409
3410                         /* Initialize the group failure */
3411                         group_failed = 0;
3412
3413                         current_run = run_groups & ((1 <<
3414                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3415                         run_groups = run_groups >>
3416                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3417
3418                         if (current_run == 0)
3419                                 continue;
3420
3421                         writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3422                                             SCC_MGR_GROUP_COUNTER_OFFSET);
3423                         scc_mgr_zero_group(write_group, 0);
3424
3425                         for (read_group = write_group * rwdqs_ratio,
3426                              read_test_bgn = 0;
3427                              read_group < (write_group + 1) * rwdqs_ratio;
3428                              read_group++,
3429                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3430                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3431                                         continue;
3432
3433                                 /* Calibrate the VFIFO */
3434                                 if (rw_mgr_mem_calibrate_vfifo(read_group,
3435                                                                read_test_bgn))
3436                                         continue;
3437
3438                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3439                                         return 0;
3440
3441                                 /* The group failed, we're done. */
3442                                 goto grp_failed;
3443                         }
3444
3445                         /* Calibrate the output side */
3446                         for (rank_bgn = 0, sr = 0;
3447                              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3448                              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3449                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3450                                         continue;
3451
3452                                 /* Not needed in quick mode! */
3453                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3454                                         continue;
3455
3456                                 /*
3457                                  * Determine if this set of ranks
3458                                  * should be skipped entirely.
3459                                  */
3460                                 if (param->skip_shadow_regs[sr])
3461                                         continue;
3462
3463                                 /* Calibrate WRITEs */
3464                                 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3465                                                 write_group, write_test_bgn))
3466                                         continue;
3467
3468                                 group_failed = 1;
3469                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3470                                         return 0;
3471                         }
3472
3473                         /* Some group failed, we're done. */
3474                         if (group_failed)
3475                                 goto grp_failed;
3476
3477                         for (read_group = write_group * rwdqs_ratio,
3478                              read_test_bgn = 0;
3479                              read_group < (write_group + 1) * rwdqs_ratio;
3480                              read_group++,
3481                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3482                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3483                                         continue;
3484
3485                                 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3486                                                                 read_test_bgn))
3487                                         continue;
3488
3489                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3490                                         return 0;
3491
3492                                 /* The group failed, we're done. */
3493                                 goto grp_failed;
3494                         }
3495
3496                         /* No group failed, continue as usual. */
3497                         continue;
3498
3499 grp_failed:             /* A group failed, increment the counter. */
3500                         failing_groups++;
3501                 }
3502
3503                 /*
3504                  * USER If there are any failing groups then report
3505                  * the failure.
3506                  */
3507                 if (failing_groups != 0)
3508                         return 0;
3509
3510                 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3511                         continue;
3512
3513                 /*
3514                  * If we're skipping groups as part of debug,
3515                  * don't calibrate LFIFO.
3516                  */
3517                 if (param->skip_groups != 0)
3518                         continue;
3519
3520                 /* Calibrate the LFIFO */
3521                 if (!rw_mgr_mem_calibrate_lfifo())
3522                         return 0;
3523         }
3524
3525         /*
3526          * Do not remove this line as it makes sure all of our decisions
3527          * have been applied.
3528          */
3529         writel(0, &sdr_scc_mgr->update);
3530         return 1;
3531 }
3532
3533 /**
3534  * run_mem_calibrate() - Perform memory calibration
3535  *
3536  * This function triggers the entire memory calibration procedure.
3537  */
3538 static int run_mem_calibrate(void)
3539 {
3540         int pass;
3541
3542         debug("%s:%d\n", __func__, __LINE__);
3543
3544         /* Reset pass/fail status shown on afi_cal_success/fail */
3545         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3546
3547         /* Stop tracking manager. */
3548         clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3549
3550         phy_mgr_initialize();
3551         rw_mgr_mem_initialize();
3552
3553         /* Perform the actual memory calibration. */
3554         pass = mem_calibrate();
3555
3556         mem_precharge_and_activate();
3557         writel(0, &phy_mgr_cmd->fifo_reset);
3558
3559         /* Handoff. */
3560         rw_mgr_mem_handoff();
3561         /*
3562          * In Hard PHY this is a 2-bit control:
3563          * 0: AFI Mux Select
3564          * 1: DDIO Mux Select
3565          */
3566         writel(0x2, &phy_mgr_cfg->mux_sel);
3567
3568         /* Start tracking manager. */
3569         setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3570
3571         return pass;
3572 }
3573
3574 /**
3575  * debug_mem_calibrate() - Report result of memory calibration
3576  * @pass:       Value indicating whether calibration passed or failed
3577  *
3578  * This function reports the results of the memory calibration
3579  * and writes debug information into the register file.
3580  */
3581 static void debug_mem_calibrate(int pass)
3582 {
3583         uint32_t debug_info;
3584
3585         if (pass) {
3586                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3587
3588                 gbl->fom_in /= 2;
3589                 gbl->fom_out /= 2;
3590
3591                 if (gbl->fom_in > 0xff)
3592                         gbl->fom_in = 0xff;
3593
3594                 if (gbl->fom_out > 0xff)
3595                         gbl->fom_out = 0xff;
3596
3597                 /* Update the FOM in the register file */
3598                 debug_info = gbl->fom_in;
3599                 debug_info |= gbl->fom_out << 8;
3600                 writel(debug_info, &sdr_reg_file->fom);
3601
3602                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3603                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3604         } else {
3605                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3606
3607                 debug_info = gbl->error_stage;
3608                 debug_info |= gbl->error_substage << 8;
3609                 debug_info |= gbl->error_group << 16;
3610
3611                 writel(debug_info, &sdr_reg_file->failing_stage);
3612                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3613                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3614
3615                 /* Update the failing group/stage in the register file */
3616                 debug_info = gbl->error_stage;
3617                 debug_info |= gbl->error_substage << 8;
3618                 debug_info |= gbl->error_group << 16;
3619                 writel(debug_info, &sdr_reg_file->failing_stage);
3620         }
3621
3622         printf("%s: Calibration complete\n", __FILE__);
3623 }
3624
3625 /**
3626  * hc_initialize_rom_data() - Initialize ROM data
3627  *
3628  * Initialize ROM data.
3629  */
3630 static void hc_initialize_rom_data(void)
3631 {
3632         u32 i, addr;
3633
3634         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3635         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3636                 writel(inst_rom_init[i], addr + (i << 2));
3637
3638         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3639         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3640                 writel(ac_rom_init[i], addr + (i << 2));
3641 }
3642
3643 /**
3644  * initialize_reg_file() - Initialize SDR register file
3645  *
3646  * Initialize SDR register file.
3647  */
3648 static void initialize_reg_file(void)
3649 {
3650         /* Initialize the register file with the correct data */
3651         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3652         writel(0, &sdr_reg_file->debug_data_addr);
3653         writel(0, &sdr_reg_file->cur_stage);
3654         writel(0, &sdr_reg_file->fom);
3655         writel(0, &sdr_reg_file->failing_stage);
3656         writel(0, &sdr_reg_file->debug1);
3657         writel(0, &sdr_reg_file->debug2);
3658 }
3659
3660 /**
3661  * initialize_hps_phy() - Initialize HPS PHY
3662  *
3663  * Initialize HPS PHY.
3664  */
3665 static void initialize_hps_phy(void)
3666 {
3667         uint32_t reg;
3668         /*
3669          * Tracking also gets configured here because it's in the
3670          * same register.
3671          */
3672         uint32_t trk_sample_count = 7500;
3673         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3674         /*
3675          * Format is number of outer loops in the 16 MSB, sample
3676          * count in 16 LSB.
3677          */
3678
3679         reg = 0;
3680         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3681         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3682         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3683         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3684         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3685         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3686         /*
3687          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3688          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3689          */
3690         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3691         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3692                 trk_sample_count);
3693         writel(reg, &sdr_ctrl->phy_ctrl0);
3694
3695         reg = 0;
3696         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3697                 trk_sample_count >>
3698                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3699         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3700                 trk_long_idle_sample_count);
3701         writel(reg, &sdr_ctrl->phy_ctrl1);
3702
3703         reg = 0;
3704         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3705                 trk_long_idle_sample_count >>
3706                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3707         writel(reg, &sdr_ctrl->phy_ctrl2);
3708 }
3709
3710 /**
3711  * initialize_tracking() - Initialize tracking
3712  *
3713  * Initialize the register file with usable initial data.
3714  */
3715 static void initialize_tracking(void)
3716 {
3717         /*
3718          * Initialize the register file with the correct data.
3719          * Compute usable version of value in case we skip full
3720          * computation later.
3721          */
3722         writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3723                &sdr_reg_file->dtaps_per_ptap);
3724
3725         /* trk_sample_count */
3726         writel(7500, &sdr_reg_file->trk_sample_count);
3727
3728         /* longidle outer loop [15:0] */
3729         writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3730
3731         /*
3732          * longidle sample count [31:24]
3733          * trfc, worst case of 933Mhz 4Gb [23:16]
3734          * trcd, worst case [15:8]
3735          * vfifo wait [7:0]
3736          */
3737         writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3738                &sdr_reg_file->delays);
3739
3740         /* mux delay */
3741         writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3742                (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3743                &sdr_reg_file->trk_rw_mgr_addr);
3744
3745         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3746                &sdr_reg_file->trk_read_dqs_width);
3747
3748         /* trefi [7:0] */
3749         writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3750                &sdr_reg_file->trk_rfsh);
3751 }
3752
3753 int sdram_calibration_full(void)
3754 {
3755         struct param_type my_param;
3756         struct gbl_type my_gbl;
3757         uint32_t pass;
3758
3759         memset(&my_param, 0, sizeof(my_param));
3760         memset(&my_gbl, 0, sizeof(my_gbl));
3761
3762         param = &my_param;
3763         gbl = &my_gbl;
3764
3765         /* Set the calibration enabled by default */
3766         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3767         /*
3768          * Only sweep all groups (regardless of fail state) by default
3769          * Set enabled read test by default.
3770          */
3771 #if DISABLE_GUARANTEED_READ
3772         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3773 #endif
3774         /* Initialize the register file */
3775         initialize_reg_file();
3776
3777         /* Initialize any PHY CSR */
3778         initialize_hps_phy();
3779
3780         scc_mgr_initialize();
3781
3782         initialize_tracking();
3783
3784         printf("%s: Preparing to start memory calibration\n", __FILE__);
3785
3786         debug("%s:%d\n", __func__, __LINE__);
3787         debug_cond(DLEVEL == 1,
3788                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3789                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3790                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3791                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3792                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3793         debug_cond(DLEVEL == 1,
3794                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3795                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3796                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3797                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3798         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3799                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3800         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3801                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3802                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3803         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3804                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3805                    IO_IO_OUT2_DELAY_MAX);
3806         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3807                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3808
3809         hc_initialize_rom_data();
3810
3811         /* update info for sims */
3812         reg_file_set_stage(CAL_STAGE_NIL);
3813         reg_file_set_group(0);
3814
3815         /*
3816          * Load global needed for those actions that require
3817          * some dynamic calibration support.
3818          */
3819         dyn_calib_steps = STATIC_CALIB_STEPS;
3820         /*
3821          * Load global to allow dynamic selection of delay loop settings
3822          * based on calibration mode.
3823          */
3824         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3825                 skip_delay_mask = 0xff;
3826         else
3827                 skip_delay_mask = 0x0;
3828
3829         pass = run_mem_calibrate();
3830         debug_mem_calibrate(pass);
3831         return pass;
3832 }