drivers/mmc/stm32_sdmmc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <[email protected]> for STMicroelectronics.
   5  */
   6
   7 #define LOG_CATEGORY UCLASS_MMC
   8
   9 #include <clk.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <fdtdec.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <asm/bitops.h>
  16 #include <asm/cache.h>
  17 #include <dm/device_compat.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/bitops.h>
  20 #include <linux/delay.h>
  21 #include <linux/libfdt.h>
  22 #include <mmc.h>
  23 #include <reset.h>
  24 #include <asm/io.h>
  25 #include <asm/gpio.h>
  26 #include <linux/iopoll.h>
  27 #include <power/regulator.h>
  28 #include <watchdog.h>
  29 #include <linux/printk.h>
  30
  31 struct stm32_sdmmc2_plat {
  32         struct mmc_config cfg;
  33         struct mmc mmc;
  34         fdt_addr_t base;
  35         struct clk clk;
  36         struct reset_ctl reset_ctl;
  37         struct gpio_desc cd_gpio;
  38         u32 clk_reg_msk;
  39         u32 pwr_reg_msk;
  40 #if CONFIG_IS_ENABLED(DM_REGULATOR)
  41         bool vqmmc_enabled;
  42 #endif
  43 };
  44
  45 struct stm32_sdmmc2_ctx {
  46         u32 cache_start;
  47         u32 cache_end;
  48         u32 data_length;
  49         bool dpsm_abort;
  50 };
  51
  52 /* SDMMC REGISTERS OFFSET */
  53 #define SDMMC_POWER             0x00    /* SDMMC power control             */
  54 #define SDMMC_CLKCR             0x04    /* SDMMC clock control             */
  55 #define SDMMC_ARG               0x08    /* SDMMC argument                  */
  56 #define SDMMC_CMD               0x0C    /* SDMMC command                   */
  57 #define SDMMC_RESP1             0x14    /* SDMMC response 1                */
  58 #define SDMMC_RESP2             0x18    /* SDMMC response 2                */
  59 #define SDMMC_RESP3             0x1C    /* SDMMC response 3                */
  60 #define SDMMC_RESP4             0x20    /* SDMMC response 4                */
  61 #define SDMMC_DTIMER            0x24    /* SDMMC data timer                */
  62 #define SDMMC_DLEN              0x28    /* SDMMC data length               */
  63 #define SDMMC_DCTRL             0x2C    /* SDMMC data control              */
  64 #define SDMMC_DCOUNT            0x30    /* SDMMC data counter              */
  65 #define SDMMC_STA               0x34    /* SDMMC status                    */
  66 #define SDMMC_ICR               0x38    /* SDMMC interrupt clear           */
  67 #define SDMMC_MASK              0x3C    /* SDMMC mask                      */
  68 #define SDMMC_IDMACTRL          0x50    /* SDMMC DMA control               */
  69 #define SDMMC_IDMABASE0         0x58    /* SDMMC DMA buffer 0 base address */
  70
  71 /* SDMMC_POWER register */
  72 #define SDMMC_POWER_PWRCTRL_MASK        GENMASK(1, 0)
  73 #define SDMMC_POWER_PWRCTRL_OFF         0
  74 #define SDMMC_POWER_PWRCTRL_CYCLE       2
  75 #define SDMMC_POWER_PWRCTRL_ON          3
  76 #define SDMMC_POWER_VSWITCH             BIT(2)
  77 #define SDMMC_POWER_VSWITCHEN           BIT(3)
  78 #define SDMMC_POWER_DIRPOL              BIT(4)
  79
  80 /* SDMMC_CLKCR register */
  81 #define SDMMC_CLKCR_CLKDIV              GENMASK(9, 0)
  82 #define SDMMC_CLKCR_CLKDIV_MAX          SDMMC_CLKCR_CLKDIV
  83 #define SDMMC_CLKCR_PWRSAV              BIT(12)
  84 #define SDMMC_CLKCR_WIDBUS_4            BIT(14)
  85 #define SDMMC_CLKCR_WIDBUS_8            BIT(15)
  86 #define SDMMC_CLKCR_NEGEDGE             BIT(16)
  87 #define SDMMC_CLKCR_HWFC_EN             BIT(17)
  88 #define SDMMC_CLKCR_DDR                 BIT(18)
  89 #define SDMMC_CLKCR_BUSSPEED            BIT(19)
  90 #define SDMMC_CLKCR_SELCLKRX_MASK       GENMASK(21, 20)
  91 #define SDMMC_CLKCR_SELCLKRX_CK         0
  92 #define SDMMC_CLKCR_SELCLKRX_CKIN       BIT(20)
  93 #define SDMMC_CLKCR_SELCLKRX_FBCK       BIT(21)
  94
  95 /* SDMMC_CMD register */
  96 #define SDMMC_CMD_CMDINDEX              GENMASK(5, 0)
  97 #define SDMMC_CMD_CMDTRANS              BIT(6)
  98 #define SDMMC_CMD_CMDSTOP               BIT(7)
  99 #define SDMMC_CMD_WAITRESP              GENMASK(9, 8)
 100 #define SDMMC_CMD_WAITRESP_0            BIT(8)
 101 #define SDMMC_CMD_WAITRESP_1            BIT(9)
 102 #define SDMMC_CMD_WAITINT               BIT(10)
 103 #define SDMMC_CMD_WAITPEND              BIT(11)
 104 #define SDMMC_CMD_CPSMEN                BIT(12)
 105 #define SDMMC_CMD_DTHOLD                BIT(13)
 106 #define SDMMC_CMD_BOOTMODE              BIT(14)
 107 #define SDMMC_CMD_BOOTEN                BIT(15)
 108 #define SDMMC_CMD_CMDSUSPEND            BIT(16)
 109
 110 /* SDMMC_DCTRL register */
 111 #define SDMMC_DCTRL_DTEN                BIT(0)
 112 #define SDMMC_DCTRL_DTDIR               BIT(1)
 113 #define SDMMC_DCTRL_DTMODE              GENMASK(3, 2)
 114 #define SDMMC_DCTRL_DBLOCKSIZE          GENMASK(7, 4)
 115 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT    4
 116 #define SDMMC_DCTRL_RWSTART             BIT(8)
 117 #define SDMMC_DCTRL_RWSTOP              BIT(9)
 118 #define SDMMC_DCTRL_RWMOD               BIT(10)
 119 #define SDMMC_DCTRL_SDMMCEN             BIT(11)
 120 #define SDMMC_DCTRL_BOOTACKEN           BIT(12)
 121 #define SDMMC_DCTRL_FIFORST             BIT(13)
 122
 123 /* SDMMC_STA register */
 124 #define SDMMC_STA_CCRCFAIL              BIT(0)
 125 #define SDMMC_STA_DCRCFAIL              BIT(1)
 126 #define SDMMC_STA_CTIMEOUT              BIT(2)
 127 #define SDMMC_STA_DTIMEOUT              BIT(3)
 128 #define SDMMC_STA_TXUNDERR              BIT(4)
 129 #define SDMMC_STA_RXOVERR               BIT(5)
 130 #define SDMMC_STA_CMDREND               BIT(6)
 131 #define SDMMC_STA_CMDSENT               BIT(7)
 132 #define SDMMC_STA_DATAEND               BIT(8)
 133 #define SDMMC_STA_DHOLD                 BIT(9)
 134 #define SDMMC_STA_DBCKEND               BIT(10)
 135 #define SDMMC_STA_DABORT                BIT(11)
 136 #define SDMMC_STA_DPSMACT               BIT(12)
 137 #define SDMMC_STA_CPSMACT               BIT(13)
 138 #define SDMMC_STA_TXFIFOHE              BIT(14)
 139 #define SDMMC_STA_RXFIFOHF              BIT(15)
 140 #define SDMMC_STA_TXFIFOF               BIT(16)
 141 #define SDMMC_STA_RXFIFOF               BIT(17)
 142 #define SDMMC_STA_TXFIFOE               BIT(18)
 143 #define SDMMC_STA_RXFIFOE               BIT(19)
 144 #define SDMMC_STA_BUSYD0                BIT(20)
 145 #define SDMMC_STA_BUSYD0END             BIT(21)
 146 #define SDMMC_STA_SDMMCIT               BIT(22)
 147 #define SDMMC_STA_ACKFAIL               BIT(23)
 148 #define SDMMC_STA_ACKTIMEOUT            BIT(24)
 149 #define SDMMC_STA_VSWEND                BIT(25)
 150 #define SDMMC_STA_CKSTOP                BIT(26)
 151 #define SDMMC_STA_IDMATE                BIT(27)
 152 #define SDMMC_STA_IDMABTC               BIT(28)
 153
 154 /* SDMMC_ICR register */
 155 #define SDMMC_ICR_CCRCFAILC             BIT(0)
 156 #define SDMMC_ICR_DCRCFAILC             BIT(1)
 157 #define SDMMC_ICR_CTIMEOUTC             BIT(2)
 158 #define SDMMC_ICR_DTIMEOUTC             BIT(3)
 159 #define SDMMC_ICR_TXUNDERRC             BIT(4)
 160 #define SDMMC_ICR_RXOVERRC              BIT(5)
 161 #define SDMMC_ICR_CMDRENDC              BIT(6)
 162 #define SDMMC_ICR_CMDSENTC              BIT(7)
 163 #define SDMMC_ICR_DATAENDC              BIT(8)
 164 #define SDMMC_ICR_DHOLDC                BIT(9)
 165 #define SDMMC_ICR_DBCKENDC              BIT(10)
 166 #define SDMMC_ICR_DABORTC               BIT(11)
 167 #define SDMMC_ICR_BUSYD0ENDC            BIT(21)
 168 #define SDMMC_ICR_SDMMCITC              BIT(22)
 169 #define SDMMC_ICR_ACKFAILC              BIT(23)
 170 #define SDMMC_ICR_ACKTIMEOUTC           BIT(24)
 171 #define SDMMC_ICR_VSWENDC               BIT(25)
 172 #define SDMMC_ICR_CKSTOPC               BIT(26)
 173 #define SDMMC_ICR_IDMATEC               BIT(27)
 174 #define SDMMC_ICR_IDMABTCC              BIT(28)
 175 #define SDMMC_ICR_STATIC_FLAGS          ((GENMASK(28, 21)) | (GENMASK(11, 0)))
 176
 177 /* SDMMC_MASK register */
 178 #define SDMMC_MASK_CCRCFAILIE           BIT(0)
 179 #define SDMMC_MASK_DCRCFAILIE           BIT(1)
 180 #define SDMMC_MASK_CTIMEOUTIE           BIT(2)
 181 #define SDMMC_MASK_DTIMEOUTIE           BIT(3)
 182 #define SDMMC_MASK_TXUNDERRIE           BIT(4)
 183 #define SDMMC_MASK_RXOVERRIE            BIT(5)
 184 #define SDMMC_MASK_CMDRENDIE            BIT(6)
 185 #define SDMMC_MASK_CMDSENTIE            BIT(7)
 186 #define SDMMC_MASK_DATAENDIE            BIT(8)
 187 #define SDMMC_MASK_DHOLDIE              BIT(9)
 188 #define SDMMC_MASK_DBCKENDIE            BIT(10)
 189 #define SDMMC_MASK_DABORTIE             BIT(11)
 190 #define SDMMC_MASK_TXFIFOHEIE           BIT(14)
 191 #define SDMMC_MASK_RXFIFOHFIE           BIT(15)
 192 #define SDMMC_MASK_RXFIFOFIE            BIT(17)
 193 #define SDMMC_MASK_TXFIFOEIE            BIT(18)
 194 #define SDMMC_MASK_BUSYD0ENDIE          BIT(21)
 195 #define SDMMC_MASK_SDMMCITIE            BIT(22)
 196 #define SDMMC_MASK_ACKFAILIE            BIT(23)
 197 #define SDMMC_MASK_ACKTIMEOUTIE         BIT(24)
 198 #define SDMMC_MASK_VSWENDIE             BIT(25)
 199 #define SDMMC_MASK_CKSTOPIE             BIT(26)
 200 #define SDMMC_MASK_IDMABTCIE            BIT(28)
 201
 202 /* SDMMC_IDMACTRL register */
 203 #define SDMMC_IDMACTRL_IDMAEN           BIT(0)
 204
 205 #define SDMMC_CMD_TIMEOUT               0xFFFFFFFF
 206 #define SDMMC_BUSYD0END_TIMEOUT_US      2000000
 207
 208 static void stm32_sdmmc2_start_data(struct udevice *dev,
 209                                     struct mmc_data *data,
 210                                     struct stm32_sdmmc2_ctx *ctx)
 211 {
 212         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 213         u32 data_ctrl, idmabase0;
 214
 215         /* Configure the SDMMC DPSM (Data Path State Machine) */
 216         data_ctrl = (__ilog2(data->blocksize) <<
 217                      SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
 218                     SDMMC_DCTRL_DBLOCKSIZE;
 219
 220         if (data->flags & MMC_DATA_READ) {
 221                 data_ctrl |= SDMMC_DCTRL_DTDIR;
 222                 idmabase0 = (u32)(long)data->dest;
 223         } else {
 224                 idmabase0 = (u32)(long)data->src;
 225         }
 226
 227         /* Set the SDMMC DataLength value */
 228         writel(ctx->data_length, plat->base + SDMMC_DLEN);
 229
 230         /* Write to SDMMC DCTRL */
 231         writel(data_ctrl, plat->base + SDMMC_DCTRL);
 232
 233         /* Cache align */
 234         ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
 235         ctx->cache_end = roundup(idmabase0 + ctx->data_length,
 236                                  ARCH_DMA_MINALIGN);
 237
 238         /*
 239          * Flush data cache before DMA start (clean and invalidate)
 240          * Clean also needed for read
 241          * Avoid issue on buffer not cached-aligned
 242          */
 243         flush_dcache_range(ctx->cache_start, ctx->cache_end);
 244
 245         /* Enable internal DMA */
 246         writel(idmabase0, plat->base + SDMMC_IDMABASE0);
 247         writel(SDMMC_IDMACTRL_IDMAEN, plat->base + SDMMC_IDMACTRL);
 248 }
 249
 250 static void stm32_sdmmc2_start_cmd(struct udevice *dev,
 251                                    struct mmc_cmd *cmd, u32 cmd_param,
 252                                    struct stm32_sdmmc2_ctx *ctx)
 253 {
 254         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 255         u32 timeout = 0;
 256
 257         if (readl(plat->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
 258                 writel(0, plat->base + SDMMC_CMD);
 259
 260         cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
 261         if (cmd->resp_type & MMC_RSP_PRESENT) {
 262                 if (cmd->resp_type & MMC_RSP_136)
 263                         cmd_param |= SDMMC_CMD_WAITRESP;
 264                 else if (cmd->resp_type & MMC_RSP_CRC)
 265                         cmd_param |= SDMMC_CMD_WAITRESP_0;
 266                 else
 267                         cmd_param |= SDMMC_CMD_WAITRESP_1;
 268         }
 269
 270         /*
 271          * SDMMC_DTIME must be set in two case:
 272          * - on data transfert.
 273          * - on busy request.
 274          * If not done or too short, the dtimeout flag occurs and DPSM stays
 275          * enabled/busy and waits for abort (stop transmission cmd).
 276          * Next data command is not possible whereas DPSM is activated.
 277          */
 278         if (ctx->data_length) {
 279                 timeout = SDMMC_CMD_TIMEOUT;
 280         } else {
 281                 writel(0, plat->base + SDMMC_DCTRL);
 282
 283                 if (cmd->resp_type & MMC_RSP_BUSY)
 284                         timeout = SDMMC_CMD_TIMEOUT;
 285         }
 286
 287         /* Set the SDMMC Data TimeOut value */
 288         writel(timeout, plat->base + SDMMC_DTIMER);
 289
 290         /* Clear flags */
 291         writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR);
 292
 293         /* Set SDMMC argument value */
 294         writel(cmd->cmdarg, plat->base + SDMMC_ARG);
 295
 296         /* Set SDMMC command parameters */
 297         writel(cmd_param, plat->base + SDMMC_CMD);
 298 }
 299
 300 static int stm32_sdmmc2_end_cmd(struct udevice *dev,
 301                                 struct mmc_cmd *cmd,
 302                                 struct stm32_sdmmc2_ctx *ctx)
 303 {
 304         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 305         u32 mask = SDMMC_STA_CTIMEOUT;
 306         u32 status;
 307         int ret;
 308
 309         if (cmd->resp_type & MMC_RSP_PRESENT) {
 310                 mask |= SDMMC_STA_CMDREND;
 311                 if (cmd->resp_type & MMC_RSP_CRC)
 312                         mask |= SDMMC_STA_CCRCFAIL;
 313         } else {
 314                 mask |= SDMMC_STA_CMDSENT;
 315         }
 316
 317         /* Polling status register */
 318         ret = readl_poll_timeout(plat->base + SDMMC_STA, status, status & mask,
 319                                  10000);
 320
 321         if (ret < 0) {
 322                 dev_dbg(dev, "timeout reading SDMMC_STA register\n");
 323                 ctx->dpsm_abort = true;
 324                 return ret;
 325         }
 326
 327         /* Check status */
 328         if (status & SDMMC_STA_CTIMEOUT) {
 329                 dev_dbg(dev, "error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
 330                         status, cmd->cmdidx);
 331                 ctx->dpsm_abort = true;
 332                 return -ETIMEDOUT;
 333         }
 334
 335         if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
 336                 dev_dbg(dev, "error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
 337                         status, cmd->cmdidx);
 338                 ctx->dpsm_abort = true;
 339                 return -EILSEQ;
 340         }
 341
 342         if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
 343                 cmd->response[0] = readl(plat->base + SDMMC_RESP1);
 344                 if (cmd->resp_type & MMC_RSP_136) {
 345                         cmd->response[1] = readl(plat->base + SDMMC_RESP2);
 346                         cmd->response[2] = readl(plat->base + SDMMC_RESP3);
 347                         cmd->response[3] = readl(plat->base + SDMMC_RESP4);
 348                 }
 349
 350                 /* Wait for BUSYD0END flag if busy status is detected */
 351                 if (cmd->resp_type & MMC_RSP_BUSY &&
 352                     status & SDMMC_STA_BUSYD0) {
 353                         mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
 354
 355                         /* Polling status register */
 356                         ret = readl_poll_timeout(plat->base + SDMMC_STA,
 357                                                  status, status & mask,
 358                                                  SDMMC_BUSYD0END_TIMEOUT_US);
 359
 360                         if (ret < 0) {
 361                                 dev_dbg(dev, "timeout reading SDMMC_STA\n");
 362                                 ctx->dpsm_abort = true;
 363                                 return ret;
 364                         }
 365
 366                         if (status & SDMMC_STA_DTIMEOUT) {
 367                                 dev_dbg(dev,
 368                                         "error SDMMC_STA_DTIMEOUT (0x%x)\n",
 369                                         status);
 370                                 ctx->dpsm_abort = true;
 371                                 return -ETIMEDOUT;
 372                         }
 373                 }
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int stm32_sdmmc2_end_data(struct udevice *dev,
 380                                  struct mmc_cmd *cmd,
 381                                  struct mmc_data *data,
 382                                  struct stm32_sdmmc2_ctx *ctx)
 383 {
 384         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 385         u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
 386                    SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
 387         u32 status;
 388
 389         if (data->flags & MMC_DATA_READ)
 390                 mask |= SDMMC_STA_RXOVERR;
 391         else
 392                 mask |= SDMMC_STA_TXUNDERR;
 393
 394         status = readl(plat->base + SDMMC_STA);
 395         while (!(status & mask))
 396                 status = readl(plat->base + SDMMC_STA);
 397
 398         /*
 399          * Need invalidate the dcache again to avoid any
 400          * cache-refill during the DMA operations (pre-fetching)
 401          */
 402         if (data->flags & MMC_DATA_READ)
 403                 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
 404
 405         if (status & SDMMC_STA_DCRCFAIL) {
 406                 dev_dbg(dev, "error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
 407                         status, cmd->cmdidx);
 408                 if (readl(plat->base + SDMMC_DCOUNT))
 409                         ctx->dpsm_abort = true;
 410                 return -EILSEQ;
 411         }
 412
 413         if (status & SDMMC_STA_DTIMEOUT) {
 414                 dev_dbg(dev, "error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
 415                         status, cmd->cmdidx);
 416                 ctx->dpsm_abort = true;
 417                 return -ETIMEDOUT;
 418         }
 419
 420         if (status & SDMMC_STA_TXUNDERR) {
 421                 dev_dbg(dev, "error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
 422                         status, cmd->cmdidx);
 423                 ctx->dpsm_abort = true;
 424                 return -EIO;
 425         }
 426
 427         if (status & SDMMC_STA_RXOVERR) {
 428                 dev_dbg(dev, "error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
 429                         status, cmd->cmdidx);
 430                 ctx->dpsm_abort = true;
 431                 return -EIO;
 432         }
 433
 434         if (status & SDMMC_STA_IDMATE) {
 435                 dev_dbg(dev, "error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
 436                         status, cmd->cmdidx);
 437                 ctx->dpsm_abort = true;
 438                 return -EIO;
 439         }
 440
 441         return 0;
 442 }
 443
 444 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 445                                  struct mmc_data *data)
 446 {
 447         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 448         struct stm32_sdmmc2_ctx ctx;
 449         u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
 450         int ret, retry = 3;
 451
 452         schedule();
 453
 454 retry_cmd:
 455         ctx.data_length = 0;
 456         ctx.dpsm_abort = false;
 457
 458         if (data) {
 459                 ctx.data_length = data->blocks * data->blocksize;
 460                 stm32_sdmmc2_start_data(dev, data, &ctx);
 461         }
 462
 463         stm32_sdmmc2_start_cmd(dev, cmd, cmdat, &ctx);
 464
 465         dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%p\n",
 466                 cmd->cmdidx, data ? ctx.data_length : 0, data);
 467
 468         ret = stm32_sdmmc2_end_cmd(dev, cmd, &ctx);
 469
 470         if (data && !ret)
 471                 ret = stm32_sdmmc2_end_data(dev, cmd, data, &ctx);
 472
 473         /* Clear flags */
 474         writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR);
 475         if (data)
 476                 writel(0x0, plat->base + SDMMC_IDMACTRL);
 477
 478         /*
 479          * To stop Data Path State Machine, a stop_transmission command
 480          * shall be send on cmd or data errors.
 481          */
 482         if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
 483                 struct mmc_cmd stop_cmd;
 484
 485                 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 486                 stop_cmd.cmdarg = 0;
 487                 stop_cmd.resp_type = MMC_RSP_R1b;
 488
 489                 dev_dbg(dev, "send STOP command to abort dpsm treatments\n");
 490
 491                 ctx.data_length = 0;
 492
 493                 stm32_sdmmc2_start_cmd(dev, &stop_cmd,
 494                                        SDMMC_CMD_CMDSTOP, &ctx);
 495                 stm32_sdmmc2_end_cmd(dev, &stop_cmd, &ctx);
 496
 497                 writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR);
 498         }
 499
 500         if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
 501                 dev_err(dev, "cmd %d failed, retrying ...\n", cmd->cmdidx);
 502                 retry--;
 503                 goto retry_cmd;
 504         }
 505
 506         dev_dbg(dev, "end for CMD %d, ret = %d\n", cmd->cmdidx, ret);
 507
 508         return ret;
 509 }
 510
 511 /*
 512  * Reset the SDMMC with the RCC.SDMMCxRST register bit.
 513  * This will reset the SDMMC to the reset state and the CPSM and DPSM
 514  * to the Idle state. SDMMC is disabled, Signals Hiz.
 515  */
 516 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_plat *plat)
 517 {
 518         if (reset_valid(&plat->reset_ctl)) {
 519                 /* Reset */
 520                 reset_assert(&plat->reset_ctl);
 521                 udelay(2);
 522                 reset_deassert(&plat->reset_ctl);
 523         }
 524
 525         /* init the needed SDMMC register after reset */
 526         writel(plat->pwr_reg_msk, plat->base + SDMMC_POWER);
 527 }
 528
 529 /*
 530  * Set the SDMMC in power-cycle state.
 531  * This will make that the SDMMC_D[7:0],
 532  * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
 533  * supplied through the signal lines.
 534  */
 535 static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_plat *plat)
 536 {
 537         if ((readl(plat->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
 538             SDMMC_POWER_PWRCTRL_CYCLE)
 539                 return;
 540
 541         stm32_sdmmc2_reset(plat);
 542 }
 543
 544 /*
 545  * set the SDMMC state Power-on: the card is clocked
 546  * manage the SDMMC state control:
 547  * Reset => Power-Cycle => Power-Off => Power
 548  *    PWRCTRL=10     PWCTRL=00    PWCTRL=11
 549  */
 550 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_plat *plat)
 551 {
 552         u32 pwrctrl =
 553                 readl(plat->base + SDMMC_POWER) &  SDMMC_POWER_PWRCTRL_MASK;
 554
 555         if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
 556                 return;
 557
 558         /* warning: same PWRCTRL value after reset and for power-off state
 559          * it is the reset state here = the only managed by the driver
 560          */
 561         if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
 562                 writel(SDMMC_POWER_PWRCTRL_CYCLE | plat->pwr_reg_msk,
 563                        plat->base + SDMMC_POWER);
 564         }
 565
 566         /*
 567          * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
 568          * switch to Power-Off state: SDMCC disable, signals drive 1
 569          */
 570         writel(SDMMC_POWER_PWRCTRL_OFF | plat->pwr_reg_msk,
 571                plat->base + SDMMC_POWER);
 572
 573         /* After the 1ms delay set the SDMMC to power-on */
 574         mdelay(1);
 575         writel(SDMMC_POWER_PWRCTRL_ON | plat->pwr_reg_msk,
 576                plat->base + SDMMC_POWER);
 577
 578         /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
 579
 580 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 581         if (plat->mmc.vqmmc_supply && !plat->vqmmc_enabled) {
 582                 if (regulator_set_enable_if_allowed(plat->mmc.vqmmc_supply, true))
 583                         dev_dbg(plat->mmc.dev, "failed to enable vqmmc-supply\n");
 584                 else
 585                         plat->vqmmc_enabled = true;
 586         }
 587 #endif
 588 }
 589
 590 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
 591 static int stm32_sdmmc2_set_ios(struct udevice *dev)
 592 {
 593         struct mmc *mmc = mmc_get_mmc_dev(dev);
 594         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 595         u32 desired = mmc->clock;
 596         u32 sys_clock = clk_get_rate(&plat->clk);
 597         u32 clk = 0;
 598
 599         dev_dbg(dev, "bus_with = %d, clock = %d\n",
 600                 mmc->bus_width, mmc->clock);
 601
 602         if (mmc->clk_disable)
 603                 stm32_sdmmc2_pwrcycle(plat);
 604         else
 605                 stm32_sdmmc2_pwron(plat);
 606
 607         /*
 608          * clk_div = 0 => command and data generated on SDMMCCLK falling edge
 609          * clk_div > 0 and NEGEDGE = 0 => command and data generated on
 610          * SDMMCCLK rising edge
 611          * clk_div > 0 and NEGEDGE = 1 => command and data generated on
 612          * SDMMCCLK falling edge
 613          */
 614         if (desired && (sys_clock > desired || mmc->ddr_mode ||
 615                         IS_RISING_EDGE(plat->clk_reg_msk))) {
 616                 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
 617                 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
 618                         clk = SDMMC_CLKCR_CLKDIV_MAX;
 619         }
 620
 621         if (mmc->ddr_mode)
 622                 clk |= SDMMC_CLKCR_DDR;
 623
 624         if (mmc->bus_width == 4)
 625                 clk |= SDMMC_CLKCR_WIDBUS_4;
 626         if (mmc->bus_width == 8)
 627                 clk |= SDMMC_CLKCR_WIDBUS_8;
 628
 629         writel(clk | plat->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
 630                plat->base + SDMMC_CLKCR);
 631
 632         return 0;
 633 }
 634
 635 static int stm32_sdmmc2_getcd(struct udevice *dev)
 636 {
 637         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 638
 639         dev_dbg(dev, "%s called\n", __func__);
 640
 641         if (dm_gpio_is_valid(&plat->cd_gpio))
 642                 return dm_gpio_get_value(&plat->cd_gpio);
 643
 644         return 1;
 645 }
 646
 647 static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
 648 {
 649         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 650
 651         writel(SDMMC_POWER_PWRCTRL_CYCLE | plat->pwr_reg_msk,
 652                plat->base + SDMMC_POWER);
 653
 654         return 0;
 655 }
 656
 657 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
 658         .send_cmd = stm32_sdmmc2_send_cmd,
 659         .set_ios = stm32_sdmmc2_set_ios,
 660         .get_cd = stm32_sdmmc2_getcd,
 661         .host_power_cycle = stm32_sdmmc2_host_power_cycle,
 662 };
 663
 664 static int stm32_sdmmc2_of_to_plat(struct udevice *dev)
 665 {
 666         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 667         struct mmc_config *cfg = &plat->cfg;
 668         int ret;
 669
 670         plat->base = dev_read_addr(dev);
 671         if (plat->base == FDT_ADDR_T_NONE)
 672                 return -EINVAL;
 673
 674         if (dev_read_bool(dev, "st,neg-edge"))
 675                 plat->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
 676         if (dev_read_bool(dev, "st,sig-dir"))
 677                 plat->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
 678         if (dev_read_bool(dev, "st,use-ckin"))
 679                 plat->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
 680
 681         cfg->f_min = 400000;
 682         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 683         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 684         cfg->name = "STM32 SD/MMC";
 685         cfg->host_caps = 0;
 686         cfg->f_max = 52000000;
 687         ret = mmc_of_parse(dev, cfg);
 688         if (ret)
 689                 return ret;
 690
 691         cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES);
 692
 693         ret = clk_get_by_index(dev, 0, &plat->clk);
 694         if (ret)
 695                 return ret;
 696
 697         ret = reset_get_by_index(dev, 0, &plat->reset_ctl);
 698         if (ret)
 699                 dev_dbg(dev, "No reset provided\n");
 700
 701         gpio_request_by_name(dev, "cd-gpios", 0, &plat->cd_gpio,
 702                              GPIOD_IS_IN);
 703
 704         return 0;
 705 }
 706
 707 static int stm32_sdmmc2_probe_level_translator(struct udevice *dev)
 708 {
 709         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 710         struct gpio_desc cmd_gpio;
 711         struct gpio_desc ck_gpio;
 712         struct gpio_desc ckin_gpio;
 713         int clk_hi, clk_lo, ret;
 714
 715         ret = gpio_request_by_name(dev, "st,cmd-gpios", 0, &cmd_gpio,
 716                                    GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 717         if (ret)
 718                 goto exit_cmd;
 719
 720         ret = gpio_request_by_name(dev, "st,ck-gpios", 0, &ck_gpio,
 721                                    GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 722         if (ret)
 723                 goto exit_ck;
 724
 725         ret = gpio_request_by_name(dev, "st,ckin-gpios", 0, &ckin_gpio,
 726                                    GPIOD_IS_IN);
 727         if (ret)
 728                 goto exit_ckin;
 729
 730         /* All GPIOs are valid, test whether level translator works */
 731
 732         /* Sample CKIN */
 733         clk_hi = !!dm_gpio_get_value(&ckin_gpio);
 734
 735         /* Set CK low */
 736         dm_gpio_set_value(&ck_gpio, 0);
 737
 738         /* Sample CKIN */
 739         clk_lo = !!dm_gpio_get_value(&ckin_gpio);
 740
 741         /* Tristate all */
 742         dm_gpio_set_dir_flags(&cmd_gpio, GPIOD_IS_IN);
 743         dm_gpio_set_dir_flags(&ck_gpio, GPIOD_IS_IN);
 744
 745         /* Level translator is present if CK signal is propagated to CKIN */
 746         if (!clk_hi || clk_lo)
 747                 plat->clk_reg_msk &= ~SDMMC_CLKCR_SELCLKRX_CKIN;
 748
 749         dm_gpio_free(dev, &ckin_gpio);
 750
 751 exit_ckin:
 752         dm_gpio_free(dev, &ck_gpio);
 753 exit_ck:
 754         dm_gpio_free(dev, &cmd_gpio);
 755 exit_cmd:
 756         pinctrl_select_state(dev, "default");
 757
 758         return 0;
 759 }
 760
 761 static int stm32_sdmmc2_probe(struct udevice *dev)
 762 {
 763         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 764         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 765         int ret;
 766
 767         ret = clk_enable(&plat->clk);
 768         if (ret)
 769                 return ret;
 770
 771         upriv->mmc = &plat->mmc;
 772
 773         if (plat->clk_reg_msk & SDMMC_CLKCR_SELCLKRX_CKIN)
 774                 stm32_sdmmc2_probe_level_translator(dev);
 775
 776         /* SDMMC init */
 777         stm32_sdmmc2_reset(plat);
 778
 779         return 0;
 780 }
 781
 782 static int stm32_sdmmc2_bind(struct udevice *dev)
 783 {
 784         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 785
 786         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 787 }
 788
 789 static const struct udevice_id stm32_sdmmc2_ids[] = {
 790         { .compatible = "st,stm32-sdmmc2" },
 791         { .compatible = "st,stm32mp25-sdmmc2" },
 792         { }
 793 };
 794
 795 U_BOOT_DRIVER(stm32_sdmmc2) = {
 796         .name = "stm32_sdmmc2",
 797         .id = UCLASS_MMC,
 798         .of_match = stm32_sdmmc2_ids,
 799         .ops = &stm32_sdmmc2_ops,
 800         .probe = stm32_sdmmc2_probe,
 801         .bind = stm32_sdmmc2_bind,
 802         .of_to_plat = stm32_sdmmc2_of_to_plat,
 803         .plat_auto      = sizeof(struct stm32_sdmmc2_plat),
 804 };