1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * NOTE: Please do not add new devicetree-reading functionality into this file.
6 * Add it to the ofnode API instead, since that is compatible with livetree.
11 #define LOG_CATEGORY LOGC_DT
15 #include <display_options.h>
26 #include <fdt_support.h>
29 #include <linux/libfdt.h>
31 #include <asm/global_data.h>
32 #include <asm/sections.h>
33 #include <dm/ofnode.h>
34 #include <dm/of_extra.h>
35 #include <linux/ctype.h>
36 #include <linux/lzo.h>
37 #include <linux/ioport.h>
39 DECLARE_GLOBAL_DATA_PTR;
42 * Here are the type we know about. One day we might allow drivers to
43 * register. For now we just put them here. The COMPAT macro allows us to
44 * turn this into a sparse list later, and keeps the ID with the name.
46 * NOTE: This list is basically a TODO list for things that need to be
47 * converted to driver model. So don't add new things here unless there is a
48 * good reason why driver-model conversion is infeasible. Examples include
49 * things which are used before driver model is available.
51 #define COMPAT(id, name) name
52 static const char * const compat_names[COMPAT_COUNT] = {
53 COMPAT(UNKNOWN, "<none>"),
54 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
55 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
56 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
57 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
58 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
59 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
60 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
61 COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
62 COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
63 COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
64 COMPAT(GENERIC_SPI_FLASH, "jedec,spi-nor"),
65 COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
66 COMPAT(INTEL_MICROCODE, "intel,microcode"),
67 COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
68 COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
69 COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
70 COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
71 COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
72 COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
73 COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
74 COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
75 COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
76 COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
77 COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
78 COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
79 COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
80 COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
81 COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
82 COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
83 COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
84 COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init")
87 static const char *const fdt_src_name[] = {
88 [FDTSRC_SEPARATE] = "separate",
90 [FDTSRC_BOARD] = "board",
91 [FDTSRC_EMBED] = "embed",
93 [FDTSRC_BLOBLIST] = "bloblist",
96 const char *fdtdec_get_srcname(void)
98 return fdt_src_name[gd->fdt_src];
101 const char *fdtdec_get_compatible(enum fdt_compat_id id)
103 /* We allow reading of the 'unknown' ID for testing purposes */
104 assert(id >= 0 && id < COMPAT_COUNT);
105 return compat_names[id];
108 fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
109 const char *prop_name, int index, int na,
110 int ns, fdt_size_t *sizep,
113 const fdt32_t *prop, *prop_end;
114 const fdt32_t *prop_addr, *prop_size, *prop_after_size;
118 debug("%s: %s: ", __func__, prop_name);
120 prop = fdt_getprop(blob, node, prop_name, &len);
122 debug("(not found)\n");
123 return FDT_ADDR_T_NONE;
125 prop_end = prop + (len / sizeof(*prop));
127 prop_addr = prop + (index * (na + ns));
128 prop_size = prop_addr + na;
129 prop_after_size = prop_size + ns;
130 if (prop_after_size > prop_end) {
131 debug("(not enough data: expected >= %d cells, got %d cells)\n",
132 (u32)(prop_after_size - prop), ((u32)(prop_end - prop)));
133 return FDT_ADDR_T_NONE;
136 #if CONFIG_IS_ENABLED(OF_TRANSLATE)
138 addr = fdt_translate_address(blob, node, prop_addr);
141 addr = fdtdec_get_number(prop_addr, na);
144 *sizep = fdtdec_get_number(prop_size, ns);
145 debug("addr=%08llx, size=%llx\n", (unsigned long long)addr,
146 (unsigned long long)*sizep);
148 debug("addr=%08llx\n", (unsigned long long)addr);
154 fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent,
155 int node, const char *prop_name,
156 int index, fdt_size_t *sizep,
161 debug("%s: ", __func__);
163 na = fdt_address_cells(blob, parent);
165 debug("(bad #address-cells)\n");
166 return FDT_ADDR_T_NONE;
169 ns = fdt_size_cells(blob, parent);
171 debug("(bad #size-cells)\n");
172 return FDT_ADDR_T_NONE;
175 debug("na=%d, ns=%d, ", na, ns);
177 return fdtdec_get_addr_size_fixed(blob, node, prop_name, index, na,
178 ns, sizep, translate);
181 fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node,
182 const char *prop_name, int index,
188 debug("%s: ", __func__);
190 parent = fdt_parent_offset(blob, node);
192 debug("(no parent found)\n");
193 return FDT_ADDR_T_NONE;
196 return fdtdec_get_addr_size_auto_parent(blob, parent, node, prop_name,
197 index, sizep, translate);
200 fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
201 const char *prop_name, fdt_size_t *sizep)
203 int ns = sizep ? (sizeof(fdt_size_t) / sizeof(fdt32_t)) : 0;
205 return fdtdec_get_addr_size_fixed(blob, node, prop_name, 0,
206 sizeof(fdt_addr_t) / sizeof(fdt32_t),
210 fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name)
212 return fdtdec_get_addr_size(blob, node, prop_name, NULL);
215 int fdtdec_get_pci_vendev(const void *blob, int node, u16 *vendor, u16 *device)
217 const char *list, *end;
220 list = fdt_getprop(blob, node, "compatible", &len);
227 if (len >= strlen("pciVVVV,DDDD")) {
228 char *s = strstr(list, "pci");
231 * check if the string is something like pciVVVV,DDDD.RR
232 * or just pciVVVV,DDDD
234 if (s && s[7] == ',' &&
235 (s[12] == '.' || s[12] == 0)) {
237 *vendor = simple_strtol(s, NULL, 16);
240 *device = simple_strtol(s, NULL, 16);
251 int fdtdec_get_pci_bar32(const struct udevice *dev, struct fdt_pci_addr *addr,
256 /* extract the bar number from fdt_pci_addr */
257 barnum = addr->phys_hi & 0xff;
258 if (barnum < PCI_BASE_ADDRESS_0 || barnum > PCI_CARDBUS_CIS)
261 barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
263 *bar = dm_pci_read_bar32(dev, barnum);
268 int fdtdec_get_pci_bus_range(const void *blob, int node,
269 struct fdt_resource *res)
274 values = fdt_getprop(blob, node, "bus-range", &len);
275 if (!values || len < sizeof(*values) * 2)
278 res->start = fdt32_to_cpu(*values++);
279 res->end = fdt32_to_cpu(*values);
284 uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
285 uint64_t default_val)
287 const unaligned_fdt64_t *cell64;
290 cell64 = fdt_getprop(blob, node, prop_name, &length);
291 if (!cell64 || length < sizeof(*cell64))
294 return fdt64_to_cpu(*cell64);
297 int fdtdec_get_is_enabled(const void *blob, int node)
302 * It should say "okay", so only allow that. Some fdts use "ok" but
303 * this is a bug. Please fix your device tree source file. See here
308 cell = fdt_getprop(blob, node, "status", NULL);
310 return strcmp(cell, "okay") == 0;
314 enum fdt_compat_id fdtdec_lookup(const void *blob, int node)
316 enum fdt_compat_id id;
318 /* Search our drivers */
319 for (id = COMPAT_UNKNOWN; id < COMPAT_COUNT; id++)
320 if (fdt_node_check_compatible(blob, node,
321 compat_names[id]) == 0)
323 return COMPAT_UNKNOWN;
326 int fdtdec_next_compatible(const void *blob, int node, enum fdt_compat_id id)
328 return fdt_node_offset_by_compatible(blob, node, compat_names[id]);
331 int fdtdec_next_compatible_subnode(const void *blob, int node,
332 enum fdt_compat_id id, int *depthp)
335 node = fdt_next_node(blob, node, depthp);
336 } while (*depthp > 1);
338 /* If this is a direct subnode, and compatible, return it */
339 if (*depthp == 1 && 0 == fdt_node_check_compatible(
340 blob, node, compat_names[id]))
343 return -FDT_ERR_NOTFOUND;
346 int fdtdec_next_alias(const void *blob, const char *name, enum fdt_compat_id id,
349 #define MAX_STR_LEN 20
350 char str[MAX_STR_LEN + 20];
353 /* snprintf() is not available */
354 assert(strlen(name) < MAX_STR_LEN);
355 sprintf(str, "%.*s%d", MAX_STR_LEN, name, *upto);
356 node = fdt_path_offset(blob, str);
359 err = fdt_node_check_compatible(blob, node, compat_names[id]);
363 return -FDT_ERR_NOTFOUND;
368 int fdtdec_find_aliases_for_id(const void *blob, const char *name,
369 enum fdt_compat_id id, int *node_list,
372 memset(node_list, '\0', sizeof(*node_list) * maxcount);
374 return fdtdec_add_aliases_for_id(blob, name, id, node_list, maxcount);
377 /* TODO: Can we tighten this code up a little? */
378 int fdtdec_add_aliases_for_id(const void *blob, const char *name,
379 enum fdt_compat_id id, int *node_list,
382 int name_len = strlen(name);
390 /* find the alias node if present */
391 alias_node = fdt_path_offset(blob, "/aliases");
394 * start with nothing, and we can assume that the root node can't
397 memset(nodes, '\0', sizeof(nodes));
399 /* First find all the compatible nodes */
400 for (node = count = 0; node >= 0 && count < maxcount;) {
401 node = fdtdec_next_compatible(blob, node, id);
403 nodes[count++] = node;
406 debug("%s: warning: maxcount exceeded with alias '%s'\n",
409 /* Now find all the aliases */
410 for (offset = fdt_first_property_offset(blob, alias_node);
412 offset = fdt_next_property_offset(blob, offset)) {
413 const struct fdt_property *prop;
419 prop = fdt_get_property_by_offset(blob, offset, NULL);
420 path = fdt_string(blob, fdt32_to_cpu(prop->nameoff));
421 if (prop->len && 0 == strncmp(path, name, name_len))
422 node = fdt_path_offset(blob, prop->data);
426 /* Get the alias number */
427 number = dectoul(path + name_len, NULL);
428 if (number < 0 || number >= maxcount) {
429 debug("%s: warning: alias '%s' is out of range\n",
434 /* Make sure the node we found is actually in our list! */
436 for (j = 0; j < count; j++)
437 if (nodes[j] == node) {
443 debug("%s: warning: alias '%s' points to a node "
444 "'%s' that is missing or is not compatible "
445 " with '%s'\n", __func__, path,
446 fdt_get_name(blob, node, NULL),
452 * Add this node to our list in the right place, and mark
455 if (fdtdec_get_is_enabled(blob, node)) {
456 if (node_list[number]) {
457 debug("%s: warning: alias '%s' requires that "
458 "a node be placed in the list in a "
459 "position which is already filled by "
460 "node '%s'\n", __func__, path,
461 fdt_get_name(blob, node, NULL));
464 node_list[number] = node;
465 if (number >= num_found)
466 num_found = number + 1;
471 /* Add any nodes not mentioned by an alias */
472 for (i = j = 0; i < maxcount; i++) {
474 for (; j < maxcount; j++)
476 fdtdec_get_is_enabled(blob, nodes[j]))
479 /* Have we run out of nodes to add? */
483 assert(!node_list[i]);
484 node_list[i] = nodes[j++];
493 int fdtdec_get_alias_seq(const void *blob, const char *base, int offset,
496 int base_len = strlen(base);
497 const char *find_name;
502 find_name = fdt_get_name(blob, offset, &find_namelen);
503 debug("Looking for '%s' at %d, name %s\n", base, offset, find_name);
505 aliases = fdt_path_offset(blob, "/aliases");
506 for (prop_offset = fdt_first_property_offset(blob, aliases);
508 prop_offset = fdt_next_property_offset(blob, prop_offset)) {
514 prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len);
515 debug(" - %s, %s\n", name, prop);
516 if (len < find_namelen || *prop != '/' || prop[len - 1] ||
517 strncmp(name, base, base_len))
520 slash = strrchr(prop, '/');
521 if (strcmp(slash + 1, find_name))
525 * Adding an extra check to distinguish DT nodes with
528 if (IS_ENABLED(CONFIG_PHANDLE_CHECK_SEQ)) {
529 if (fdt_get_phandle(blob, offset) !=
530 fdt_get_phandle(blob, fdt_path_offset(blob, prop)))
534 val = trailing_strtol(name);
537 debug("Found seq %d\n", *seqp);
542 debug("Not found\n");
546 int fdtdec_get_alias_highest_id(const void *blob, const char *base)
548 int base_len = strlen(base);
553 debug("Looking for highest alias id for '%s'\n", base);
555 aliases = fdt_path_offset(blob, "/aliases");
556 for (prop_offset = fdt_first_property_offset(blob, aliases);
558 prop_offset = fdt_next_property_offset(blob, prop_offset)) {
563 prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len);
564 debug(" - %s, %s\n", name, prop);
565 if (*prop != '/' || prop[len - 1] ||
566 strncmp(name, base, base_len))
569 val = trailing_strtol(name);
571 debug("Found seq %d\n", val);
579 const char *fdtdec_get_chosen_prop(const void *blob, const char *name)
585 chosen_node = fdt_path_offset(blob, "/chosen");
586 return fdt_getprop(blob, chosen_node, name, NULL);
589 int fdtdec_get_chosen_node(const void *blob, const char *name)
593 prop = fdtdec_get_chosen_prop(blob, name);
595 return -FDT_ERR_NOTFOUND;
596 return fdt_path_offset(blob, prop);
600 * fdtdec_prepare_fdt() - Check we have a valid fdt available to control U-Boot
602 * @blob: Blob to check
604 * If not, a message is printed to the console if the console is ready.
606 * Return: 0 if all ok, -ENOENT if not
608 static int fdtdec_prepare_fdt(const void *blob)
610 if (!blob || ((uintptr_t)blob & 3) || fdt_check_header(blob)) {
611 if (xpl_phase() <= PHASE_SPL) {
612 puts("Missing DTB\n");
614 printf("No valid device tree binary found at %p\n",
616 if (_DEBUG && blob) {
617 printf("fdt_blob=%p\n", blob);
618 print_buffer((ulong)blob, blob, 4, 32, 0);
627 int fdtdec_check_fdt(void)
630 * We must have an FDT, but we cannot panic() yet since the console
631 * is not ready. So for now, just assert(). Boards which need an early
632 * FDT (prior to console ready) will need to make their own
633 * arrangements and do their own checks.
635 assert(!fdtdec_prepare_fdt(gd->fdt_blob));
639 int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name)
644 debug("%s: %s\n", __func__, prop_name);
645 phandle = fdt_getprop(blob, node, prop_name, NULL);
647 return -FDT_ERR_NOTFOUND;
649 lookup = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*phandle));
654 * Look up a property in a node and check that it has a minimum length.
656 * @param blob FDT blob
657 * @param node node to examine
658 * @param prop_name name of property to find
659 * @param min_len minimum property length in bytes
660 * @param err 0 if ok, or -FDT_ERR_NOTFOUND if the property is not
661 found, or -FDT_ERR_BADLAYOUT if not enough data
662 * Return: pointer to cell, which is only valid if err == 0
664 static const void *get_prop_check_min_len(const void *blob, int node,
665 const char *prop_name, int min_len,
671 debug("%s: %s\n", __func__, prop_name);
672 cell = fdt_getprop(blob, node, prop_name, &len);
674 *err = -FDT_ERR_NOTFOUND;
675 else if (len < min_len)
676 *err = -FDT_ERR_BADLAYOUT;
682 int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
683 u32 *array, int count)
688 debug("%s: %s\n", __func__, prop_name);
689 cell = get_prop_check_min_len(blob, node, prop_name,
690 sizeof(u32) * count, &err);
694 for (i = 0; i < count; i++)
695 array[i] = fdt32_to_cpu(cell[i]);
700 int fdtdec_get_int_array_count(const void *blob, int node,
701 const char *prop_name, u32 *array, int count)
707 debug("%s: %s\n", __func__, prop_name);
708 cell = fdt_getprop(blob, node, prop_name, &len);
710 return -FDT_ERR_NOTFOUND;
711 elems = len / sizeof(u32);
714 for (i = 0; i < count; i++)
715 array[i] = fdt32_to_cpu(cell[i]);
720 const u32 *fdtdec_locate_array(const void *blob, int node,
721 const char *prop_name, int count)
726 cell = get_prop_check_min_len(blob, node, prop_name,
727 sizeof(u32) * count, &err);
728 return err ? NULL : cell;
731 int fdtdec_get_bool(const void *blob, int node, const char *prop_name)
736 debug("%s: %s\n", __func__, prop_name);
737 cell = fdt_getprop(blob, node, prop_name, &len);
741 int fdtdec_parse_phandle_with_args(const void *blob, int src_node,
742 const char *list_name,
743 const char *cells_name,
744 int cell_count, int index,
745 struct fdtdec_phandle_args *out_args)
747 const __be32 *list, *list_end;
748 int rc = 0, size, cur_index = 0;
753 /* Retrieve the phandle list property */
754 list = fdt_getprop(blob, src_node, list_name, &size);
757 list_end = list + size / sizeof(*list);
759 /* Loop over the phandles until all the requested entry is found */
760 while (list < list_end) {
765 * If phandle is 0, then it is an empty entry with no
766 * arguments. Skip forward to the next entry.
768 phandle = be32_to_cpup(list++);
771 * Find the provider node and parse the #*-cells
772 * property to determine the argument length.
774 * This is not needed if the cell count is hard-coded
775 * (i.e. cells_name not set, but cell_count is set),
776 * except when we're going to return the found node
779 if (cells_name || cur_index == index) {
780 node = fdt_node_offset_by_phandle(blob,
783 debug("%s: could not find phandle\n",
784 fdt_get_name(blob, src_node,
791 count = fdtdec_get_int(blob, node, cells_name,
794 debug("%s: could not get %s for %s\n",
795 fdt_get_name(blob, src_node,
798 fdt_get_name(blob, node,
807 * Make sure that the arguments actually fit in the
808 * remaining property data length
810 if (list + count > list_end) {
811 debug("%s: arguments longer than property\n",
812 fdt_get_name(blob, src_node, NULL));
818 * All of the error cases above bail out of the loop, so at
819 * this point, the parsing is successful. If the requested
820 * index matches, then fill the out_args structure and return,
821 * or return -ENOENT for an empty entry.
824 if (cur_index == index) {
831 if (count > MAX_PHANDLE_ARGS) {
832 debug("%s: too many arguments %d\n",
833 fdt_get_name(blob, src_node,
835 count = MAX_PHANDLE_ARGS;
837 out_args->node = node;
838 out_args->args_count = count;
839 for (i = 0; i < count; i++) {
841 be32_to_cpup(list++);
845 /* Found it! return success */
855 * Result will be one of:
856 * -ENOENT : index is for empty phandle
857 * -EINVAL : parsing error on data
858 * [1..n] : Number of phandle (count mode; when index = -1)
860 rc = index < 0 ? cur_index : -ENOENT;
865 int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
866 u8 *array, int count)
871 cell = get_prop_check_min_len(blob, node, prop_name, count, &err);
873 memcpy(array, cell, count);
877 const u8 *fdtdec_locate_byte_array(const void *blob, int node,
878 const char *prop_name, int count)
883 cell = get_prop_check_min_len(blob, node, prop_name, count, &err);
889 u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells)
894 number = (number << 32) | fdt32_to_cpu(*ptr++);
899 int fdt_get_resource(const void *fdt, int node, const char *property,
900 unsigned int index, struct fdt_resource *res)
902 const fdt32_t *ptr, *end;
903 int na, ns, len, parent;
906 parent = fdt_parent_offset(fdt, node);
910 na = fdt_address_cells(fdt, parent);
911 ns = fdt_size_cells(fdt, parent);
913 ptr = fdt_getprop(fdt, node, property, &len);
917 end = ptr + len / sizeof(*ptr);
919 while (ptr + na + ns <= end) {
921 if (CONFIG_IS_ENABLED(OF_TRANSLATE))
922 res->start = fdt_translate_address(fdt, node, ptr);
924 res->start = fdtdec_get_number(ptr, na);
926 res->end = res->start;
927 res->end += fdtdec_get_number(&ptr[na], ns) - 1;
935 return -FDT_ERR_NOTFOUND;
938 int fdt_get_named_resource(const void *fdt, int node, const char *property,
939 const char *prop_names, const char *name,
940 struct fdt_resource *res)
944 index = fdt_stringlist_search(fdt, node, prop_names, name);
948 return fdt_get_resource(fdt, node, property, index, res);
951 static int decode_timing_property(const void *blob, int node, const char *name,
952 struct timing_entry *result)
957 prop = fdt_getprop(blob, node, name, &length);
959 debug("%s: could not find property %s\n",
960 fdt_get_name(blob, node, NULL), name);
964 if (length == sizeof(u32)) {
965 result->typ = fdtdec_get_int(blob, node, name, 0);
966 result->min = result->typ;
967 result->max = result->typ;
969 ret = fdtdec_get_int_array(blob, node, name, &result->min, 3);
975 int fdtdec_decode_display_timing(const void *blob, int parent, int index,
976 struct display_timing *dt)
978 int i, node, timings_node;
982 timings_node = fdt_subnode_offset(blob, parent, "display-timings");
983 if (timings_node < 0)
986 for (i = 0, node = fdt_first_subnode(blob, timings_node);
987 node > 0 && i != index;
988 node = fdt_next_subnode(blob, node))
994 memset(dt, 0, sizeof(*dt));
996 ret |= decode_timing_property(blob, node, "hback-porch",
998 ret |= decode_timing_property(blob, node, "hfront-porch",
1000 ret |= decode_timing_property(blob, node, "hactive", &dt->hactive);
1001 ret |= decode_timing_property(blob, node, "hsync-len", &dt->hsync_len);
1002 ret |= decode_timing_property(blob, node, "vback-porch",
1004 ret |= decode_timing_property(blob, node, "vfront-porch",
1006 ret |= decode_timing_property(blob, node, "vactive", &dt->vactive);
1007 ret |= decode_timing_property(blob, node, "vsync-len", &dt->vsync_len);
1008 ret |= decode_timing_property(blob, node, "clock-frequency",
1012 val = fdtdec_get_int(blob, node, "vsync-active", -1);
1014 dt->flags |= val ? DISPLAY_FLAGS_VSYNC_HIGH :
1015 DISPLAY_FLAGS_VSYNC_LOW;
1017 val = fdtdec_get_int(blob, node, "hsync-active", -1);
1019 dt->flags |= val ? DISPLAY_FLAGS_HSYNC_HIGH :
1020 DISPLAY_FLAGS_HSYNC_LOW;
1022 val = fdtdec_get_int(blob, node, "de-active", -1);
1024 dt->flags |= val ? DISPLAY_FLAGS_DE_HIGH :
1025 DISPLAY_FLAGS_DE_LOW;
1027 val = fdtdec_get_int(blob, node, "pixelclk-active", -1);
1029 dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE :
1030 DISPLAY_FLAGS_PIXDATA_NEGEDGE;
1033 if (fdtdec_get_bool(blob, node, "interlaced"))
1034 dt->flags |= DISPLAY_FLAGS_INTERLACED;
1035 if (fdtdec_get_bool(blob, node, "doublescan"))
1036 dt->flags |= DISPLAY_FLAGS_DOUBLESCAN;
1037 if (fdtdec_get_bool(blob, node, "doubleclk"))
1038 dt->flags |= DISPLAY_FLAGS_DOUBLECLK;
1043 int fdtdec_setup_mem_size_base(void)
1047 struct resource res;
1049 mem = ofnode_path("/memory");
1050 if (!ofnode_valid(mem)) {
1051 debug("%s: Missing /memory node\n", __func__);
1055 ret = ofnode_read_resource(mem, 0, &res);
1057 debug("%s: Unable to decode first memory bank\n", __func__);
1061 gd->ram_size = (phys_size_t)(res.end - res.start + 1);
1062 gd->ram_base = (unsigned long)res.start;
1063 debug("%s: Initial DRAM size %llx\n", __func__,
1064 (unsigned long long)gd->ram_size);
1069 ofnode get_next_memory_node(ofnode mem)
1072 mem = ofnode_by_prop_value(mem, "device_type", "memory", 7);
1073 } while (!ofnode_is_enabled(mem));
1078 int fdtdec_setup_memory_banksize(void)
1080 int bank, ret, reg = 0;
1081 struct resource res;
1082 ofnode mem = ofnode_null();
1084 mem = get_next_memory_node(mem);
1085 if (!ofnode_valid(mem)) {
1086 debug("%s: Missing /memory node\n", __func__);
1090 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1091 ret = ofnode_read_resource(mem, reg++, &res);
1094 mem = get_next_memory_node(mem);
1095 if (!ofnode_valid(mem))
1098 ret = ofnode_read_resource(mem, reg++, &res);
1106 gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
1107 gd->bd->bi_dram[bank].size =
1108 (phys_size_t)(res.end - res.start + 1);
1110 debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
1112 (unsigned long long)gd->bd->bi_dram[bank].start,
1113 (unsigned long long)gd->bd->bi_dram[bank].size);
1119 int fdtdec_setup_mem_size_base_lowest(void)
1121 int bank, ret, reg = 0;
1122 struct resource res;
1125 ofnode mem = ofnode_null();
1127 gd->ram_base = (unsigned long)~0;
1129 mem = get_next_memory_node(mem);
1130 if (!ofnode_valid(mem)) {
1131 debug("%s: Missing /memory node\n", __func__);
1135 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1136 ret = ofnode_read_resource(mem, reg++, &res);
1139 mem = get_next_memory_node(mem);
1140 if (!ofnode_valid(mem))
1143 ret = ofnode_read_resource(mem, reg++, &res);
1151 base = (unsigned long)res.start;
1152 size = (phys_size_t)(res.end - res.start + 1);
1154 if (gd->ram_base > base && size) {
1155 gd->ram_base = base;
1156 gd->ram_size = size;
1157 debug("%s: Initial DRAM base %lx size %lx\n",
1158 __func__, base, (unsigned long)size);
1165 static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
1167 #if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
1168 CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO)
1169 size_t sz_out = CONFIG_VAL(MULTI_DTB_FIT_UNCOMPRESS_SZ);
1170 bool gzip = 0, lzo = 0;
1171 ulong sz_in = sz_src;
1175 if (CONFIG_IS_ENABLED(GZIP) && CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP))
1176 if (gzip_parse_header(src, sz_in) >= 0)
1178 if (CONFIG_IS_ENABLED(LZO) && CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO))
1179 if (!gzip && lzop_is_valid_header(src))
1185 if (CONFIG_IS_ENABLED(MULTI_DTB_FIT_DYN_ALLOC)) {
1186 dst = malloc(sz_out);
1188 puts("uncompress_blob: Unable to allocate memory\n");
1192 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT_USER_DEFINED_AREA)
1193 dst = (void *)CONFIG_VAL(MULTI_DTB_FIT_USER_DEF_ADDR);
1199 if (CONFIG_IS_ENABLED(GZIP) && gzip)
1200 rc = gunzip(dst, sz_out, (u8 *)src, &sz_in);
1201 else if (CONFIG_IS_ENABLED(LZO) && lzo)
1202 rc = lzop_decompress(src, sz_in, dst, &sz_out);
1207 /* not a valid compressed blob */
1208 puts("uncompress_blob: Unable to uncompress\n");
1209 if (CONFIG_IS_ENABLED(MULTI_DTB_FIT_DYN_ALLOC))
1215 *dstp = (void *)src;
1216 *dstp = (void *)src;
1222 * fdt_find_separate() - Find a devicetree at the end of the image
1224 * Return: pointer to FDT blob
1226 static void *fdt_find_separate(void)
1228 void *fdt_blob = NULL;
1230 if (IS_ENABLED(CONFIG_SANDBOX))
1233 #ifdef CONFIG_XPL_BUILD
1234 /* FDT is at end of BSS unless it is in a different memory region */
1235 if (CONFIG_IS_ENABLED(SEPARATE_BSS))
1236 fdt_blob = (ulong *)_image_binary_end;
1238 fdt_blob = (ulong *)__bss_end;
1240 /* FDT is at end of image */
1241 fdt_blob = (ulong *)_end;
1243 if (_DEBUG && !fdtdec_prepare_fdt(fdt_blob)) {
1245 const void *top = fdt_blob + fdt_totalsize(fdt_blob);
1248 * Perform a sanity check on the memory layout. If this fails,
1249 * it indicates that the device tree is positioned above the
1250 * global data pointer or the stack pointer. This should not
1253 * If this fails, check that SYS_INIT_SP_ADDR has enough space
1254 * below it for SYS_MALLOC_F_LEN and global_data, as well as the
1255 * stack, without overwriting the device tree or U-Boot itself.
1256 * Since the device tree is sitting at _end (the start of the
1257 * BSS region), we need the top of the device tree to be below
1258 * any memory allocated by board_init_f_alloc_reserve().
1260 if (top > (void *)gd || top > (void *)&stack_ptr) {
1261 printf("FDT %p gd %p\n", fdt_blob, gd);
1262 panic("FDT overlap");
1270 int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size)
1275 if (!is_valid_ethaddr(mac))
1278 path = fdt_get_alias(fdt, "ethernet");
1282 debug("ethernet alias found: %s\n", path);
1284 offset = fdt_path_offset(fdt, path);
1286 debug("ethernet alias points to absent node %s\n", path);
1290 err = fdt_setprop_inplace(fdt, offset, "local-mac-address", mac, size);
1294 debug("MAC address: %pM\n", mac);
1299 static int fdtdec_init_reserved_memory(void *blob)
1301 int na, ns, node, err;
1304 /* inherit #address-cells and #size-cells from the root node */
1305 na = fdt_address_cells(blob, 0);
1306 ns = fdt_size_cells(blob, 0);
1308 node = fdt_add_subnode(blob, 0, "reserved-memory");
1312 err = fdt_setprop(blob, node, "ranges", NULL, 0);
1316 value = cpu_to_fdt32(ns);
1318 err = fdt_setprop(blob, node, "#size-cells", &value, sizeof(value));
1322 value = cpu_to_fdt32(na);
1324 err = fdt_setprop(blob, node, "#address-cells", &value, sizeof(value));
1331 int fdtdec_add_reserved_memory(void *blob, const char *basename,
1332 const struct fdt_memory *carveout,
1333 const char **compatibles, unsigned int count,
1334 uint32_t *phandlep, unsigned long flags)
1336 fdt32_t cells[4] = {}, *ptr = cells;
1337 uint32_t upper, lower, phandle;
1338 int parent, node, na, ns, err;
1342 /* create an empty /reserved-memory node if one doesn't exist */
1343 parent = fdt_path_offset(blob, "/reserved-memory");
1345 parent = fdtdec_init_reserved_memory(blob);
1350 /* only 1 or 2 #address-cells and #size-cells are supported */
1351 na = fdt_address_cells(blob, parent);
1352 if (na < 1 || na > 2)
1353 return -FDT_ERR_BADNCELLS;
1355 ns = fdt_size_cells(blob, parent);
1356 if (ns < 1 || ns > 2)
1357 return -FDT_ERR_BADNCELLS;
1359 /* find a matching node and return the phandle to that */
1360 fdt_for_each_subnode(node, blob, parent) {
1361 const char *name = fdt_get_name(blob, node, NULL);
1365 addr = fdtdec_get_addr_size_fixed(blob, node, "reg", 0, na, ns,
1367 if (addr == FDT_ADDR_T_NONE) {
1368 debug("failed to read address/size for %s\n", name);
1372 if (addr == carveout->start && (addr + size - 1) ==
1375 *phandlep = fdt_get_phandle(blob, node);
1381 * Unpack the start address and generate the name of the new node
1382 * base on the basename and the unit-address.
1384 upper = upper_32_bits(carveout->start);
1385 lower = lower_32_bits(carveout->start);
1387 if (na > 1 && upper > 0)
1388 snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
1392 debug("address %08x:%08x exceeds addressable space\n",
1394 return -FDT_ERR_BADVALUE;
1397 snprintf(name, sizeof(name), "%s@%x", basename, lower);
1400 node = fdt_add_subnode(blob, parent, name);
1404 if (flags & FDTDEC_RESERVED_MEMORY_NO_MAP) {
1405 err = fdt_setprop(blob, node, "no-map", NULL, 0);
1411 err = fdt_generate_phandle(blob, &phandle);
1415 err = fdtdec_set_phandle(blob, node, phandle);
1420 /* store one or two address cells */
1422 *ptr++ = cpu_to_fdt32(upper);
1424 *ptr++ = cpu_to_fdt32(lower);
1426 /* store one or two size cells */
1427 size = carveout->end - carveout->start + 1;
1428 upper = upper_32_bits(size);
1429 lower = lower_32_bits(size);
1432 *ptr++ = cpu_to_fdt32(upper);
1434 *ptr++ = cpu_to_fdt32(lower);
1436 err = fdt_setprop(blob, node, "reg", cells, (na + ns) * sizeof(*cells));
1440 if (compatibles && count > 0) {
1441 size_t length = 0, len = 0;
1445 for (i = 0; i < count; i++)
1446 length += strlen(compatibles[i]) + 1;
1448 buffer = malloc(length);
1450 return -FDT_ERR_INTERNAL;
1452 for (i = 0; i < count; i++)
1453 len += strlcpy(buffer + len, compatibles[i],
1456 err = fdt_setprop(blob, node, "compatible", buffer, length);
1462 /* return the phandle for the new node for the caller to use */
1464 *phandlep = phandle;
1469 int fdtdec_get_carveout(const void *blob, const char *node,
1470 const char *prop_name, unsigned int index,
1471 struct fdt_memory *carveout, const char **name,
1472 const char ***compatiblesp, unsigned int *countp,
1473 unsigned long *flags)
1475 const fdt32_t *prop;
1480 offset = fdt_path_offset(blob, node);
1484 prop = fdt_getprop(blob, offset, prop_name, &len);
1486 debug("failed to get %s for %s\n", prop_name, node);
1487 return -FDT_ERR_NOTFOUND;
1490 if ((len % sizeof(phandle)) != 0) {
1491 debug("invalid phandle property\n");
1492 return -FDT_ERR_BADPHANDLE;
1495 if (len < (sizeof(phandle) * (index + 1))) {
1496 debug("invalid phandle index\n");
1497 return -FDT_ERR_NOTFOUND;
1500 phandle = fdt32_to_cpu(prop[index]);
1502 offset = fdt_node_offset_by_phandle(blob, phandle);
1504 debug("failed to find node for phandle %u\n", phandle);
1509 *name = fdt_get_name(blob, offset, NULL);
1512 const char **compatibles = NULL;
1513 const char *start, *end, *ptr;
1514 unsigned int count = 0;
1516 prop = fdt_getprop(blob, offset, "compatible", &len);
1520 start = ptr = (const char *)prop;
1524 ptr = strchrnul(ptr, '\0');
1529 compatibles = malloc(sizeof(ptr) * count);
1531 return -FDT_ERR_INTERNAL;
1537 compatibles[count] = ptr;
1538 ptr = strchrnul(ptr, '\0');
1544 *compatiblesp = compatibles;
1550 carveout->start = fdtdec_get_addr_size_auto_noparent(blob, offset,
1553 if (carveout->start == FDT_ADDR_T_NONE) {
1554 debug("failed to read address/size from \"reg\" property\n");
1555 return -FDT_ERR_NOTFOUND;
1558 carveout->end = carveout->start + size - 1;
1563 if (fdtdec_get_bool(blob, offset, "no-map"))
1564 *flags |= FDTDEC_RESERVED_MEMORY_NO_MAP;
1570 int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
1571 unsigned int index, const struct fdt_memory *carveout,
1572 const char *name, const char **compatibles,
1573 unsigned int count, unsigned long flags)
1576 int err, offset, len;
1580 err = fdtdec_add_reserved_memory(blob, name, carveout, compatibles,
1581 count, &phandle, flags);
1583 debug("failed to add reserved memory: %d\n", err);
1587 offset = fdt_path_offset(blob, node);
1589 debug("failed to find offset for node %s: %d\n", node, offset);
1593 value = cpu_to_fdt32(phandle);
1595 if (!fdt_getprop(blob, offset, prop_name, &len)) {
1596 if (len == -FDT_ERR_NOTFOUND)
1602 if ((index + 1) * sizeof(value) > len) {
1603 err = fdt_setprop_placeholder(blob, offset, prop_name,
1604 (index + 1) * sizeof(value),
1607 debug("failed to resize reserved memory property: %s\n",
1613 err = fdt_setprop_inplace_namelen_partial(blob, offset, prop_name,
1615 index * sizeof(value),
1616 &value, sizeof(value));
1618 debug("failed to update %s property for node %s: %s\n",
1619 prop_name, node, fdt_strerror(err));
1627 __weak int fdtdec_board_setup(const void *fdt_blob)
1633 * setup_multi_dtb_fit() - locate the correct dtb from a FIT
1635 * This supports the CONFIG_MULTI_DTB_FIT feature, looking for the dtb in a
1638 * It accepts the current value of gd->fdt_blob, which points to the FIT, then
1639 * updates that gd->fdt_blob, to point to the chosen dtb so that U-Boot uses the
1642 static void setup_multi_dtb_fit(void)
1647 * Try and uncompress the blob.
1648 * Unfortunately there is no way to know how big the input blob really
1649 * is. So let us set the maximum input size arbitrarily high. 16MB
1650 * ought to be more than enough for packed DTBs.
1652 if (uncompress_blob(gd->fdt_blob, 0x1000000, &blob) == 0)
1653 gd->fdt_blob = blob;
1656 * Check if blob is a FIT images containings DTBs.
1657 * If so, pick the most relevant
1659 blob = locate_dtb_in_fit(gd->fdt_blob);
1661 gd_set_multi_dtb_fit(gd->fdt_blob);
1662 gd->fdt_blob = blob;
1663 gd->fdt_src = FDTSRC_FIT;
1667 int fdtdec_setup(void)
1672 * If allowing a bloblist, check that first. There was discussion about
1673 * adding an OF_BLOBLIST Kconfig, but this was rejected.
1675 * The necessary test is whether the previous phase passed a bloblist,
1676 * not whether this phase creates one.
1678 if (CONFIG_IS_ENABLED(BLOBLIST) &&
1679 (xpl_prev_phase() != PHASE_TPL ||
1680 IS_ENABLED(CONFIG_TPL_BLOBLIST))) {
1681 ret = bloblist_maybe_init();
1683 gd->fdt_blob = bloblist_find(BLOBLISTT_CONTROL_FDT, 0);
1685 gd->fdt_src = FDTSRC_BLOBLIST;
1686 log_debug("Devicetree is in bloblist at %p\n",
1690 log_debug("No FDT found in bloblist\n");
1696 /* Otherwise, the devicetree is typically appended to U-Boot */
1698 if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
1699 gd->fdt_blob = fdt_find_separate();
1700 gd->fdt_src = FDTSRC_SEPARATE;
1701 } else { /* embed dtb in ELF file for testing / development */
1702 gd->fdt_blob = dtb_dt_embedded();
1703 gd->fdt_src = FDTSRC_EMBED;
1707 /* Allow the board to override the fdt address. */
1708 if (IS_ENABLED(CONFIG_OF_BOARD)) {
1711 blob = (void *)gd->fdt_blob;
1712 ret = board_fdt_blob_setup(&blob);
1717 gd->fdt_src = FDTSRC_BOARD;
1718 gd->fdt_blob = blob;
1722 /* Allow the early environment to override the fdt address */
1723 if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
1726 addr = env_get_hex("fdtcontroladdr", 0);
1728 gd->fdt_blob = map_sysmem(addr, 0);
1729 gd->fdt_src = FDTSRC_ENV;
1733 if (CONFIG_IS_ENABLED(MULTI_DTB_FIT))
1734 setup_multi_dtb_fit();
1736 ret = fdtdec_prepare_fdt(gd->fdt_blob);
1738 ret = fdtdec_board_setup(gd->fdt_blob);
1744 int fdtdec_resetup(int *rescan)
1749 * If the current DTB is part of a compressed FIT image,
1750 * try to locate the best match from the uncompressed
1751 * FIT image stillpresent there. Save the time and space
1752 * required to uncompress it again.
1754 if (gd_multi_dtb_fit()) {
1755 fdt_blob = locate_dtb_in_fit(gd_multi_dtb_fit());
1757 if (fdt_blob == gd->fdt_blob) {
1759 * The best match did not change. no need to tear down
1760 * the DM and rescan the fdt.
1767 gd->fdt_blob = fdt_blob;
1768 return fdtdec_prepare_fdt(fdt_blob);
1772 * If multi_dtb_fit is NULL, it means that blob appended to u-boot is
1773 * not a FIT image containings DTB, but a single DTB. There is no need
1774 * to teard down DM and rescan the DT in this case.
1780 int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
1781 phys_addr_t *basep, phys_size_t *sizep,
1784 int addr_cells, size_cells;
1785 const u32 *cell, *end;
1786 u64 total_size, size, addr;
1792 debug("%s: board_id=%d\n", __func__, board_id);
1795 node = fdt_path_offset(blob, area);
1797 debug("No %s node found\n", area);
1801 cell = fdt_getprop(blob, node, "reg", &len);
1803 debug("No reg property found\n");
1807 addr_cells = fdt_address_cells(blob, node);
1808 size_cells = fdt_size_cells(blob, node);
1810 /* Check the board id and mask */
1811 for (child = fdt_first_subnode(blob, node);
1813 child = fdt_next_subnode(blob, child)) {
1814 int match_mask, match_value;
1816 match_mask = fdtdec_get_int(blob, child, "match-mask", -1);
1817 match_value = fdtdec_get_int(blob, child, "match-value", -1);
1819 if (match_value >= 0 &&
1820 ((board_id & match_mask) == match_value)) {
1821 /* Found matching mask */
1822 debug("Found matching mask %d\n", match_mask);
1824 cell = fdt_getprop(blob, node, "reg", &len);
1826 debug("No memory-banks property found\n");
1832 /* Note: if no matching subnode was found we use the parent node */
1835 memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) *
1836 CONFIG_NR_DRAM_BANKS);
1839 auto_size = fdtdec_get_bool(blob, node, "auto-size");
1842 end = cell + len / 4 - addr_cells - size_cells;
1843 debug("cell at %p, end %p\n", cell, end);
1844 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1848 if (addr_cells == 2)
1849 addr += (u64)fdt32_to_cpu(*cell++) << 32UL;
1850 addr += fdt32_to_cpu(*cell++);
1852 bd->bi_dram[bank].start = addr;
1854 *basep = (phys_addr_t)addr;
1857 if (size_cells == 2)
1858 size += (u64)fdt32_to_cpu(*cell++) << 32UL;
1859 size += fdt32_to_cpu(*cell++);
1864 debug("Auto-sizing %llx, size %llx: ", addr, size);
1865 new_size = get_ram_size((long *)(uintptr_t)addr, size);
1866 if (new_size == size) {
1869 debug("sized to %llx\n", new_size);
1875 bd->bi_dram[bank].size = size;
1879 debug("Memory size %llu\n", total_size);
1881 *sizep = (phys_size_t)total_size;
1886 #endif /* !USE_HOSTCC */