drivers/mmc/mtk-sd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek SD/MMC Card Interface driver
   4  *
   5  * Copyright (C) 2018 MediaTek Inc.
   6  * Author: Weijie Gao <[email protected]>
   7  */
   8
   9 #include <clk.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <mmc.h>
  13 #include <errno.h>
  14 #include <malloc.h>
  15 #include <mapmem.h>
  16 #include <stdbool.h>
  17 #include <asm/gpio.h>
  18 #include <dm/device_compat.h>
  19 #include <dm/pinctrl.h>
  20 #include <linux/bitops.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/printk.h>
  24
  25 /* MSDC_CFG */
  26 #define MSDC_CFG_HS400_CK_MODE_EXT      BIT(22)
  27 #define MSDC_CFG_CKMOD_EXT_M            0x300000
  28 #define MSDC_CFG_CKMOD_EXT_S            20
  29 #define MSDC_CFG_CKDIV_EXT_M            0xfff00
  30 #define MSDC_CFG_CKDIV_EXT_S            8
  31 #define MSDC_CFG_HS400_CK_MODE          BIT(18)
  32 #define MSDC_CFG_CKMOD_M                0x30000
  33 #define MSDC_CFG_CKMOD_S                16
  34 #define MSDC_CFG_CKDIV_M                0xff00
  35 #define MSDC_CFG_CKDIV_S                8
  36 #define MSDC_CFG_CKSTB                  BIT(7)
  37 #define MSDC_CFG_PIO                    BIT(3)
  38 #define MSDC_CFG_RST                    BIT(2)
  39 #define MSDC_CFG_CKPDN                  BIT(1)
  40 #define MSDC_CFG_MODE                   BIT(0)
  41
  42 /* MSDC_IOCON */
  43 #define MSDC_IOCON_W_DSPL               BIT(8)
  44 #define MSDC_IOCON_DSPL                 BIT(2)
  45 #define MSDC_IOCON_RSPL                 BIT(1)
  46
  47 /* MSDC_PS */
  48 #define MSDC_PS_DAT0                    BIT(16)
  49 #define MSDC_PS_CDDBCE_M                0xf000
  50 #define MSDC_PS_CDDBCE_S                12
  51 #define MSDC_PS_CDSTS                   BIT(1)
  52 #define MSDC_PS_CDEN                    BIT(0)
  53
  54 /* #define MSDC_INT(EN) */
  55 #define MSDC_INT_ACMDRDY                BIT(3)
  56 #define MSDC_INT_ACMDTMO                BIT(4)
  57 #define MSDC_INT_ACMDCRCERR             BIT(5)
  58 #define MSDC_INT_CMDRDY                 BIT(8)
  59 #define MSDC_INT_CMDTMO                 BIT(9)
  60 #define MSDC_INT_RSPCRCERR              BIT(10)
  61 #define MSDC_INT_XFER_COMPL             BIT(12)
  62 #define MSDC_INT_DATTMO                 BIT(14)
  63 #define MSDC_INT_DATCRCERR              BIT(15)
  64
  65 /* MSDC_FIFOCS */
  66 #define MSDC_FIFOCS_CLR                 BIT(31)
  67 #define MSDC_FIFOCS_TXCNT_M             0xff0000
  68 #define MSDC_FIFOCS_TXCNT_S             16
  69 #define MSDC_FIFOCS_RXCNT_M             0xff
  70 #define MSDC_FIFOCS_RXCNT_S             0
  71
  72 /* #define SDC_CFG */
  73 #define SDC_CFG_DTOC_M                  0xff000000
  74 #define SDC_CFG_DTOC_S                  24
  75 #define SDC_CFG_SDIOIDE                 BIT(20)
  76 #define SDC_CFG_SDIO                    BIT(19)
  77 #define SDC_CFG_BUSWIDTH_M              0x30000
  78 #define SDC_CFG_BUSWIDTH_S              16
  79
  80 /* SDC_CMD */
  81 #define SDC_CMD_BLK_LEN_M               0xfff0000
  82 #define SDC_CMD_BLK_LEN_S               16
  83 #define SDC_CMD_STOP                    BIT(14)
  84 #define SDC_CMD_WR                      BIT(13)
  85 #define SDC_CMD_DTYPE_M                 0x1800
  86 #define SDC_CMD_DTYPE_S                 11
  87 #define SDC_CMD_RSPTYP_M                0x380
  88 #define SDC_CMD_RSPTYP_S                7
  89 #define SDC_CMD_CMD_M                   0x3f
  90 #define SDC_CMD_CMD_S                   0
  91
  92 /* SDC_STS */
  93 #define SDC_STS_CMDBUSY                 BIT(1)
  94 #define SDC_STS_SDCBUSY                 BIT(0)
  95
  96 /* SDC_ADV_CFG0 */
  97 #define SDC_RX_ENHANCE_EN               BIT(20)
  98
  99 /* PATCH_BIT0 */
 100 #define MSDC_INT_DAT_LATCH_CK_SEL_M     0x380
 101 #define MSDC_INT_DAT_LATCH_CK_SEL_S     7
 102
 103 /* PATCH_BIT1 */
 104 #define MSDC_PB1_STOP_DLY_M             0xf00
 105 #define MSDC_PB1_STOP_DLY_S             8
 106
 107 /* PATCH_BIT2 */
 108 #define MSDC_PB2_CRCSTSENSEL_M          0xe0000000
 109 #define MSDC_PB2_CRCSTSENSEL_S          29
 110 #define MSDC_PB2_CFGCRCSTS              BIT(28)
 111 #define MSDC_PB2_RESPSTSENSEL_M         0x70000
 112 #define MSDC_PB2_RESPSTSENSEL_S         16
 113 #define MSDC_PB2_CFGRESP                BIT(15)
 114 #define MSDC_PB2_RESPWAIT_M             0x0c
 115 #define MSDC_PB2_RESPWAIT_S             2
 116
 117 /* MSDC_PAD_CTRL0 */
 118 #define MSDC_PAD_CTRL0_CLKRDSEL_M       0xff000000
 119 #define MSDC_PAD_CTRL0_CLKRDSEL_S       24
 120 #define MSDC_PAD_CTRL0_CLKTDSEL         BIT(20)
 121 #define MSDC_PAD_CTRL0_CLKIES           BIT(19)
 122 #define MSDC_PAD_CTRL0_CLKSMT           BIT(18)
 123 #define MSDC_PAD_CTRL0_CLKPU            BIT(17)
 124 #define MSDC_PAD_CTRL0_CLKPD            BIT(16)
 125 #define MSDC_PAD_CTRL0_CLKSR            BIT(8)
 126 #define MSDC_PAD_CTRL0_CLKDRVP_M        0x70
 127 #define MSDC_PAD_CTRL0_CLKDRVP_S        4
 128 #define MSDC_PAD_CTRL0_CLKDRVN_M        0x7
 129 #define MSDC_PAD_CTRL0_CLKDRVN_S        0
 130
 131 /* MSDC_PAD_CTRL1 */
 132 #define MSDC_PAD_CTRL1_CMDRDSEL_M       0xff000000
 133 #define MSDC_PAD_CTRL1_CMDRDSEL_S       24
 134 #define MSDC_PAD_CTRL1_CMDTDSEL         BIT(20)
 135 #define MSDC_PAD_CTRL1_CMDIES           BIT(19)
 136 #define MSDC_PAD_CTRL1_CMDSMT           BIT(18)
 137 #define MSDC_PAD_CTRL1_CMDPU            BIT(17)
 138 #define MSDC_PAD_CTRL1_CMDPD            BIT(16)
 139 #define MSDC_PAD_CTRL1_CMDSR            BIT(8)
 140 #define MSDC_PAD_CTRL1_CMDDRVP_M        0x70
 141 #define MSDC_PAD_CTRL1_CMDDRVP_S        4
 142 #define MSDC_PAD_CTRL1_CMDDRVN_M        0x7
 143 #define MSDC_PAD_CTRL1_CMDDRVN_S        0
 144
 145 /* MSDC_PAD_CTRL2 */
 146 #define MSDC_PAD_CTRL2_DATRDSEL_M       0xff000000
 147 #define MSDC_PAD_CTRL2_DATRDSEL_S       24
 148 #define MSDC_PAD_CTRL2_DATTDSEL         BIT(20)
 149 #define MSDC_PAD_CTRL2_DATIES           BIT(19)
 150 #define MSDC_PAD_CTRL2_DATSMT           BIT(18)
 151 #define MSDC_PAD_CTRL2_DATPU            BIT(17)
 152 #define MSDC_PAD_CTRL2_DATPD            BIT(16)
 153 #define MSDC_PAD_CTRL2_DATSR            BIT(8)
 154 #define MSDC_PAD_CTRL2_DATDRVP_M        0x70
 155 #define MSDC_PAD_CTRL2_DATDRVP_S        4
 156 #define MSDC_PAD_CTRL2_DATDRVN_M        0x7
 157 #define MSDC_PAD_CTRL2_DATDRVN_S        0
 158
 159 /* PAD_TUNE */
 160 #define MSDC_PAD_TUNE_CLKTDLY_M         0xf8000000
 161 #define MSDC_PAD_TUNE_CLKTDLY_S         27
 162 #define MSDC_PAD_TUNE_CMDRRDLY_M        0x7c00000
 163 #define MSDC_PAD_TUNE_CMDRRDLY_S        22
 164 #define MSDC_PAD_TUNE_CMD_SEL           BIT(21)
 165 #define MSDC_PAD_TUNE_CMDRDLY_M         0x1f0000
 166 #define MSDC_PAD_TUNE_CMDRDLY_S         16
 167 #define MSDC_PAD_TUNE_RXDLYSEL          BIT(15)
 168 #define MSDC_PAD_TUNE_RD_SEL            BIT(13)
 169 #define MSDC_PAD_TUNE_DATRRDLY_M        0x1f00
 170 #define MSDC_PAD_TUNE_DATRRDLY_S        8
 171 #define MSDC_PAD_TUNE_DATWRDLY_M        0x1f
 172 #define MSDC_PAD_TUNE_DATWRDLY_S        0
 173
 174 #define PAD_CMD_TUNE_RX_DLY3            0x3E
 175 #define PAD_CMD_TUNE_RX_DLY3_S          1
 176
 177 /* PAD_TUNE0 */
 178 #define MSDC_PAD_TUNE0_DAT0RDDLY_M      0x1f000000
 179 #define MSDC_PAD_TUNE0_DAT0RDDLY_S      24
 180 #define MSDC_PAD_TUNE0_DAT1RDDLY_M      0x1f0000
 181 #define MSDC_PAD_TUNE0_DAT1RDDLY_S      16
 182 #define MSDC_PAD_TUNE0_DAT2RDDLY_M      0x1f00
 183 #define MSDC_PAD_TUNE0_DAT2RDDLY_S      8
 184 #define MSDC_PAD_TUNE0_DAT3RDDLY_M      0x1f
 185 #define MSDC_PAD_TUNE0_DAT3RDDLY_S      0
 186
 187 /* PAD_TUNE1 */
 188 #define MSDC_PAD_TUNE1_DAT4RDDLY_M      0x1f000000
 189 #define MSDC_PAD_TUNE1_DAT4RDDLY_S      24
 190 #define MSDC_PAD_TUNE1_DAT5RDDLY_M      0x1f0000
 191 #define MSDC_PAD_TUNE1_DAT5RDDLY_S      16
 192 #define MSDC_PAD_TUNE1_DAT6RDDLY_M      0x1f00
 193 #define MSDC_PAD_TUNE1_DAT6RDDLY_S      8
 194 #define MSDC_PAD_TUNE1_DAT7RDDLY_M      0x1f
 195 #define MSDC_PAD_TUNE1_DAT7RDDLY_S      0
 196
 197 /* EMMC50_CFG0 */
 198 #define EMMC50_CFG_CFCSTS_SEL           BIT(4)
 199
 200 /* SDC_FIFO_CFG */
 201 #define SDC_FIFO_CFG_WRVALIDSEL         BIT(24)
 202 #define SDC_FIFO_CFG_RDVALIDSEL         BIT(25)
 203
 204 /* EMMC_TOP_CONTROL mask */
 205 #define PAD_RXDLY_SEL                   BIT(0)
 206 #define DELAY_EN                        BIT(1)
 207 #define PAD_DAT_RD_RXDLY2               (0x1f << 2)
 208 #define PAD_DAT_RD_RXDLY                (0x1f << 7)
 209 #define PAD_DAT_RD_RXDLY_S              7
 210 #define PAD_DAT_RD_RXDLY2_SEL           BIT(12)
 211 #define PAD_DAT_RD_RXDLY_SEL            BIT(13)
 212 #define DATA_K_VALUE_SEL                BIT(14)
 213 #define SDC_RX_ENH_EN                   BIT(15)
 214
 215 /* EMMC_TOP_CMD mask */
 216 #define PAD_CMD_RXDLY2                  (0x1f << 0)
 217 #define PAD_CMD_RXDLY                   (0x1f << 5)
 218 #define PAD_CMD_RXDLY_S                 5
 219 #define PAD_CMD_RD_RXDLY2_SEL           BIT(10)
 220 #define PAD_CMD_RD_RXDLY_SEL            BIT(11)
 221 #define PAD_CMD_TX_DLY                  (0x1f << 12)
 222
 223 /* SDC_CFG_BUSWIDTH */
 224 #define MSDC_BUS_1BITS                  0x0
 225 #define MSDC_BUS_4BITS                  0x1
 226 #define MSDC_BUS_8BITS                  0x2
 227
 228 #define MSDC_FIFO_SIZE                  128
 229
 230 #define PAD_DELAY_MAX                   32
 231
 232 #define DEFAULT_CD_DEBOUNCE             8
 233
 234 #define SCLK_CYCLES_SHIFT               20
 235
 236 #define MIN_BUS_CLK                     200000
 237
 238 #define CMD_INTS_MASK   \
 239         (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
 240
 241 #define DATA_INTS_MASK  \
 242         (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
 243
 244 /* Register offset */
 245 struct mtk_sd_regs {
 246         u32 msdc_cfg;
 247         u32 msdc_iocon;
 248         u32 msdc_ps;
 249         u32 msdc_int;
 250         u32 msdc_inten;
 251         u32 msdc_fifocs;
 252         u32 msdc_txdata;
 253         u32 msdc_rxdata;
 254         u32 reserved0[4];
 255         u32 sdc_cfg;
 256         u32 sdc_cmd;
 257         u32 sdc_arg;
 258         u32 sdc_sts;
 259         u32 sdc_resp[4];
 260         u32 sdc_blk_num;
 261         u32 sdc_vol_chg;
 262         u32 sdc_csts;
 263         u32 sdc_csts_en;
 264         u32 sdc_datcrc_sts;
 265         u32 sdc_adv_cfg0;
 266         u32 reserved1[2];
 267         u32 emmc_cfg0;
 268         u32 emmc_cfg1;
 269         u32 emmc_sts;
 270         u32 emmc_iocon;
 271         u32 sd_acmd_resp;
 272         u32 sd_acmd19_trg;
 273         u32 sd_acmd19_sts;
 274         u32 dma_sa_high4bit;
 275         u32 dma_sa;
 276         u32 dma_ca;
 277         u32 dma_ctrl;
 278         u32 dma_cfg;
 279         u32 sw_dbg_sel;
 280         u32 sw_dbg_out;
 281         u32 dma_length;
 282         u32 reserved2;
 283         u32 patch_bit0;
 284         u32 patch_bit1;
 285         u32 patch_bit2;
 286         u32 reserved3;
 287         u32 dat0_tune_crc;
 288         u32 dat1_tune_crc;
 289         u32 dat2_tune_crc;
 290         u32 dat3_tune_crc;
 291         u32 cmd_tune_crc;
 292         u32 sdio_tune_wind;
 293         u32 reserved4[2];
 294         u32 pad_ctrl0;
 295         u32 pad_ctrl1;
 296         u32 pad_ctrl2;
 297         u32 pad_tune;
 298         u32 pad_tune0;
 299         u32 pad_tune1;
 300         u32 dat_rd_dly[4];
 301         u32 reserved5[2];
 302         u32 hw_dbg_sel;
 303         u32 main_ver;
 304         u32 eco_ver;
 305         u32 reserved6[27];
 306         u32 pad_ds_tune;
 307         u32 pad_cmd_tune;
 308         u32 reserved7[30];
 309         u32 emmc50_cfg0;
 310         u32 reserved8[7];
 311         u32 sdc_fifo_cfg;
 312 };
 313
 314 struct msdc_top_regs {
 315         u32 emmc_top_control;
 316         u32 emmc_top_cmd;
 317         u32 emmc50_pad_ctl0;
 318         u32 emmc50_pad_ds_tune;
 319         u32 emmc50_pad_dat0_tune;
 320         u32 emmc50_pad_dat1_tune;
 321         u32 emmc50_pad_dat2_tune;
 322         u32 emmc50_pad_dat3_tune;
 323         u32 emmc50_pad_dat4_tune;
 324         u32 emmc50_pad_dat5_tune;
 325         u32 emmc50_pad_dat6_tune;
 326         u32 emmc50_pad_dat7_tune;
 327 };
 328
 329 struct msdc_compatible {
 330         u8 clk_div_bits;
 331         bool pad_tune0;
 332         bool async_fifo;
 333         bool data_tune;
 334         bool busy_check;
 335         bool stop_clk_fix;
 336         bool enhance_rx;
 337         bool builtin_pad_ctrl;
 338         bool default_pad_dly;
 339 };
 340
 341 struct msdc_delay_phase {
 342         u8 maxlen;
 343         u8 start;
 344         u8 final_phase;
 345 };
 346
 347 struct msdc_plat {
 348         struct mmc_config cfg;
 349         struct mmc mmc;
 350 };
 351
 352 struct msdc_tune_para {
 353         u32 iocon;
 354         u32 pad_tune;
 355         u32 pad_cmd_tune;
 356 };
 357
 358 struct msdc_host {
 359         struct mtk_sd_regs *base;
 360         struct msdc_top_regs *top_base;
 361         struct mmc *mmc;
 362
 363         struct msdc_compatible *dev_comp;
 364
 365         struct clk src_clk;     /* for SD/MMC bus clock */
 366         struct clk src_clk_cg;  /* optional, MSDC source clock control gate */
 367         struct clk h_clk;       /* MSDC core clock */
 368
 369         u32 src_clk_freq;       /* source clock */
 370         u32 mclk;               /* mmc framework required bus clock */
 371         u32 sclk;               /* actual calculated bus clock */
 372
 373         /* operation timeout clocks */
 374         u32 timeout_ns;
 375         u32 timeout_clks;
 376
 377         /* tuning options */
 378         u32 hs400_ds_delay;
 379         u32 hs200_cmd_int_delay;
 380         u32 hs200_write_int_delay;
 381         u32 latch_ck;
 382         u32 r_smpl;             /* sample edge */
 383         bool hs400_mode;
 384
 385         /* whether to use gpio detection or built-in hw detection */
 386         bool builtin_cd;
 387         bool cd_active_high;
 388
 389         /* card detection / write protection GPIOs */
 390 #if CONFIG_IS_ENABLED(DM_GPIO)
 391         struct gpio_desc gpio_wp;
 392         struct gpio_desc gpio_cd;
 393 #endif
 394
 395         uint last_resp_type;
 396         uint last_data_write;
 397
 398         enum bus_mode timing;
 399
 400         struct msdc_tune_para def_tune_para;
 401         struct msdc_tune_para saved_tune_para;
 402 };
 403
 404 static void msdc_reset_hw(struct msdc_host *host)
 405 {
 406         u32 reg;
 407
 408         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
 409
 410         readl_poll_timeout(&host->base->msdc_cfg, reg,
 411                            !(reg & MSDC_CFG_RST), 1000000);
 412 }
 413
 414 static void msdc_fifo_clr(struct msdc_host *host)
 415 {
 416         u32 reg;
 417
 418         setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
 419
 420         readl_poll_timeout(&host->base->msdc_fifocs, reg,
 421                            !(reg & MSDC_FIFOCS_CLR), 1000000);
 422 }
 423
 424 static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
 425 {
 426         return (readl(&host->base->msdc_fifocs) &
 427                 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
 428 }
 429
 430 static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
 431 {
 432         return (readl(&host->base->msdc_fifocs) &
 433                 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
 434 }
 435
 436 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
 437 {
 438         u32 resp;
 439
 440         switch (cmd->resp_type) {
 441                 /* Actually, R1, R5, R6, R7 are the same */
 442         case MMC_RSP_R1:
 443                 resp = 0x1;
 444                 break;
 445         case MMC_RSP_R1b:
 446                 resp = 0x7;
 447                 break;
 448         case MMC_RSP_R2:
 449                 resp = 0x2;
 450                 break;
 451         case MMC_RSP_R3:
 452                 resp = 0x3;
 453                 break;
 454         case MMC_RSP_NONE:
 455         default:
 456                 resp = 0x0;
 457                 break;
 458         }
 459
 460         return resp;
 461 }
 462
 463 static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
 464                                     struct mmc_cmd *cmd,
 465                                     struct mmc_data *data)
 466 {
 467         u32 opcode = cmd->cmdidx;
 468         u32 resp_type = msdc_cmd_find_resp(host, cmd);
 469         uint blocksize = 0;
 470         u32 dtype = 0;
 471         u32 rawcmd = 0;
 472
 473         switch (opcode) {
 474         case MMC_CMD_WRITE_MULTIPLE_BLOCK:
 475         case MMC_CMD_READ_MULTIPLE_BLOCK:
 476                 dtype = 2;
 477                 break;
 478         case MMC_CMD_WRITE_SINGLE_BLOCK:
 479         case MMC_CMD_READ_SINGLE_BLOCK:
 480         case SD_CMD_APP_SEND_SCR:
 481         case MMC_CMD_SEND_TUNING_BLOCK:
 482         case MMC_CMD_SEND_TUNING_BLOCK_HS200:
 483                 dtype = 1;
 484                 break;
 485         case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
 486         case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
 487         case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
 488                 if (data)
 489                         dtype = 1;
 490         }
 491
 492         if (data) {
 493                 if (data->flags == MMC_DATA_WRITE)
 494                         rawcmd |= SDC_CMD_WR;
 495
 496                 if (data->blocks > 1)
 497                         dtype = 2;
 498
 499                 blocksize = data->blocksize;
 500         }
 501
 502         rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
 503                 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
 504                 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
 505                 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
 506
 507         if (opcode == MMC_CMD_STOP_TRANSMISSION)
 508                 rawcmd |= SDC_CMD_STOP;
 509
 510         return rawcmd;
 511 }
 512
 513 static int msdc_cmd_done(struct msdc_host *host, int events,
 514                          struct mmc_cmd *cmd)
 515 {
 516         u32 *rsp = cmd->response;
 517         int ret = 0;
 518
 519         if (cmd->resp_type & MMC_RSP_PRESENT) {
 520                 if (cmd->resp_type & MMC_RSP_136) {
 521                         rsp[0] = readl(&host->base->sdc_resp[3]);
 522                         rsp[1] = readl(&host->base->sdc_resp[2]);
 523                         rsp[2] = readl(&host->base->sdc_resp[1]);
 524                         rsp[3] = readl(&host->base->sdc_resp[0]);
 525                 } else {
 526                         rsp[0] = readl(&host->base->sdc_resp[0]);
 527                 }
 528         }
 529
 530         if (!(events & MSDC_INT_CMDRDY)) {
 531                 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
 532                     cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
 533                         /*
 534                          * should not clear fifo/interrupt as the tune data
 535                          * may have alreay come.
 536                          */
 537                         msdc_reset_hw(host);
 538
 539                 if (events & MSDC_INT_CMDTMO)
 540                         ret = -ETIMEDOUT;
 541                 else
 542                         ret = -EIO;
 543         }
 544
 545         return ret;
 546 }
 547
 548 static bool msdc_cmd_is_ready(struct msdc_host *host)
 549 {
 550         int ret;
 551         u32 reg;
 552
 553         /* The max busy time we can endure is 20ms */
 554         ret = readl_poll_timeout(&host->base->sdc_sts, reg,
 555                                  !(reg & SDC_STS_CMDBUSY), 20000);
 556
 557         if (ret) {
 558                 pr_err("CMD bus busy detected\n");
 559                 msdc_reset_hw(host);
 560                 return false;
 561         }
 562
 563         if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
 564                 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
 565                                          reg & MSDC_PS_DAT0, 1000000);
 566
 567                 if (ret) {
 568                         pr_err("Card stuck in programming state!\n");
 569                         msdc_reset_hw(host);
 570                         return false;
 571                 }
 572         }
 573
 574         return true;
 575 }
 576
 577 static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
 578                               struct mmc_data *data)
 579 {
 580         u32 rawcmd;
 581         u32 status;
 582         u32 blocks = 0;
 583         int ret;
 584
 585         if (!msdc_cmd_is_ready(host))
 586                 return -EIO;
 587
 588         if ((readl(&host->base->msdc_fifocs) &
 589             MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
 590             (readl(&host->base->msdc_fifocs) &
 591             MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
 592                 pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
 593                 msdc_reset_hw(host);
 594         }
 595
 596         msdc_fifo_clr(host);
 597
 598         host->last_resp_type = cmd->resp_type;
 599         host->last_data_write = 0;
 600
 601         rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
 602
 603         if (data)
 604                 blocks = data->blocks;
 605
 606         writel(CMD_INTS_MASK, &host->base->msdc_int);
 607         writel(DATA_INTS_MASK, &host->base->msdc_int);
 608         writel(blocks, &host->base->sdc_blk_num);
 609         writel(cmd->cmdarg, &host->base->sdc_arg);
 610         writel(rawcmd, &host->base->sdc_cmd);
 611
 612         ret = readl_poll_timeout(&host->base->msdc_int, status,
 613                                  status & CMD_INTS_MASK, 1000000);
 614
 615         if (ret)
 616                 status = MSDC_INT_CMDTMO;
 617
 618         return msdc_cmd_done(host, status, cmd);
 619 }
 620
 621 static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
 622 {
 623         u32 *wbuf;
 624
 625         while ((size_t)buf % 4) {
 626                 *buf++ = readb(&host->base->msdc_rxdata);
 627                 size--;
 628         }
 629
 630         wbuf = (u32 *)buf;
 631         while (size >= 4) {
 632                 *wbuf++ = readl(&host->base->msdc_rxdata);
 633                 size -= 4;
 634         }
 635
 636         buf = (u8 *)wbuf;
 637         while (size) {
 638                 *buf++ = readb(&host->base->msdc_rxdata);
 639                 size--;
 640         }
 641 }
 642
 643 static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
 644 {
 645         const u32 *wbuf;
 646
 647         while ((size_t)buf % 4) {
 648                 writeb(*buf++, &host->base->msdc_txdata);
 649                 size--;
 650         }
 651
 652         wbuf = (const u32 *)buf;
 653         while (size >= 4) {
 654                 writel(*wbuf++, &host->base->msdc_txdata);
 655                 size -= 4;
 656         }
 657
 658         buf = (const u8 *)wbuf;
 659         while (size) {
 660                 writeb(*buf++, &host->base->msdc_txdata);
 661                 size--;
 662         }
 663 }
 664
 665 static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
 666 {
 667         u32 status;
 668         u32 chksz;
 669         int ret = 0;
 670
 671         while (1) {
 672                 status = readl(&host->base->msdc_int);
 673                 writel(status, &host->base->msdc_int);
 674                 status &= DATA_INTS_MASK;
 675
 676                 if (status & MSDC_INT_DATCRCERR) {
 677                         ret = -EIO;
 678                         break;
 679                 }
 680
 681                 if (status & MSDC_INT_DATTMO) {
 682                         ret = -ETIMEDOUT;
 683                         break;
 684                 }
 685
 686                 chksz = min(size, (u32)MSDC_FIFO_SIZE);
 687
 688                 if (msdc_fifo_rx_bytes(host) >= chksz) {
 689                         msdc_fifo_read(host, ptr, chksz);
 690                         ptr += chksz;
 691                         size -= chksz;
 692                 }
 693
 694                 if (status & MSDC_INT_XFER_COMPL) {
 695                         if (size) {
 696                                 pr_err("data not fully read\n");
 697                                 ret = -EIO;
 698                         }
 699
 700                         break;
 701                 }
 702 }
 703
 704         return ret;
 705 }
 706
 707 static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
 708 {
 709         u32 status;
 710         u32 chksz;
 711         int ret = 0;
 712
 713         while (1) {
 714                 status = readl(&host->base->msdc_int);
 715                 writel(status, &host->base->msdc_int);
 716                 status &= DATA_INTS_MASK;
 717
 718                 if (status & MSDC_INT_DATCRCERR) {
 719                         ret = -EIO;
 720                         break;
 721                 }
 722
 723                 if (status & MSDC_INT_DATTMO) {
 724                         ret = -ETIMEDOUT;
 725                         break;
 726                 }
 727
 728                 if (status & MSDC_INT_XFER_COMPL) {
 729                         if (size) {
 730                                 pr_err("data not fully written\n");
 731                                 ret = -EIO;
 732                         }
 733
 734                         break;
 735                 }
 736
 737                 chksz = min(size, (u32)MSDC_FIFO_SIZE);
 738
 739                 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
 740                         msdc_fifo_write(host, ptr, chksz);
 741                         ptr += chksz;
 742                         size -= chksz;
 743                 }
 744         }
 745
 746         return ret;
 747 }
 748
 749 static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
 750 {
 751         u32 size;
 752         int ret;
 753
 754         if (data->flags == MMC_DATA_WRITE)
 755                 host->last_data_write = 1;
 756
 757         size = data->blocks * data->blocksize;
 758
 759         if (data->flags == MMC_DATA_WRITE)
 760                 ret = msdc_pio_write(host, (const u8 *)data->src, size);
 761         else
 762                 ret = msdc_pio_read(host, (u8 *)data->dest, size);
 763
 764         if (ret) {
 765                 msdc_reset_hw(host);
 766                 msdc_fifo_clr(host);
 767         }
 768
 769         return ret;
 770 }
 771
 772 static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 773                              struct mmc_data *data)
 774 {
 775         struct msdc_host *host = dev_get_priv(dev);
 776         int cmd_ret, data_ret;
 777
 778         cmd_ret = msdc_start_command(host, cmd, data);
 779         if (cmd_ret &&
 780             !(cmd_ret == -EIO &&
 781             (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 782             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
 783                 return cmd_ret;
 784
 785         if (data) {
 786                 data_ret = msdc_start_data(host, data);
 787                 if (cmd_ret)
 788                         return cmd_ret;
 789                 else
 790                         return data_ret;
 791         }
 792
 793         return 0;
 794 }
 795
 796 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
 797 {
 798         u32 timeout, clk_ns, shift = SCLK_CYCLES_SHIFT;
 799         u32 mode = 0;
 800
 801         host->timeout_ns = ns;
 802         host->timeout_clks = clks;
 803
 804         if (host->sclk == 0) {
 805                 timeout = 0;
 806         } else {
 807                 clk_ns = 1000000000UL / host->sclk;
 808                 timeout = (ns + clk_ns - 1) / clk_ns + clks;
 809                 /* unit is 1048576 sclk cycles */
 810                 timeout = (timeout + (0x1 << shift) - 1) >> shift;
 811                 if (host->dev_comp->clk_div_bits == 8)
 812                         mode = (readl(&host->base->msdc_cfg) &
 813                                 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
 814                 else
 815                         mode = (readl(&host->base->msdc_cfg) &
 816                                 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
 817                 /* DDR mode will double the clk cycles for data timeout */
 818                 timeout = mode >= 2 ? timeout * 2 : timeout;
 819                 timeout = timeout > 1 ? timeout - 1 : 0;
 820                 timeout = timeout > 255 ? 255 : timeout;
 821         }
 822
 823         clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
 824                         timeout << SDC_CFG_DTOC_S);
 825 }
 826
 827 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
 828 {
 829         u32 val = readl(&host->base->sdc_cfg);
 830
 831         val &= ~SDC_CFG_BUSWIDTH_M;
 832
 833         switch (width) {
 834         default:
 835         case 1:
 836                 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
 837                 break;
 838         case 4:
 839                 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
 840                 break;
 841         case 8:
 842                 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
 843                 break;
 844         }
 845
 846         writel(val, &host->base->sdc_cfg);
 847 }
 848
 849 static void msdc_set_mclk(struct udevice *dev,
 850                           struct msdc_host *host, enum bus_mode timing, u32 hz)
 851 {
 852         u32 mode;
 853         u32 div;
 854         u32 sclk;
 855         u32 reg;
 856
 857         if (!hz) {
 858                 host->mclk = 0;
 859                 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
 860                 return;
 861         }
 862
 863         if (host->dev_comp->clk_div_bits == 8)
 864                 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
 865         else
 866                 clrbits_le32(&host->base->msdc_cfg,
 867                              MSDC_CFG_HS400_CK_MODE_EXT);
 868
 869         if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
 870             timing == MMC_HS_400) {
 871                 if (timing == MMC_HS_400)
 872                         mode = 0x3;
 873                 else
 874                         mode = 0x2; /* ddr mode and use divisor */
 875
 876                 if (hz >= (host->src_clk_freq >> 2)) {
 877                         div = 0; /* mean div = 1/4 */
 878                         sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
 879                 } else {
 880                         div = (host->src_clk_freq + ((hz << 2) - 1)) /
 881                                (hz << 2);
 882                         sclk = (host->src_clk_freq >> 2) / div;
 883                         div = (div >> 1);
 884                 }
 885
 886                 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
 887                         if (host->dev_comp->clk_div_bits == 8)
 888                                 setbits_le32(&host->base->msdc_cfg,
 889                                              MSDC_CFG_HS400_CK_MODE);
 890                         else
 891                                 setbits_le32(&host->base->msdc_cfg,
 892                                              MSDC_CFG_HS400_CK_MODE_EXT);
 893
 894                         sclk = host->src_clk_freq >> 1;
 895                         div = 0; /* div is ignore when bit18 is set */
 896                 }
 897         } else if (hz >= host->src_clk_freq) {
 898                 mode = 0x1; /* no divisor */
 899                 div = 0;
 900                 sclk = host->src_clk_freq;
 901         } else {
 902                 mode = 0x0; /* use divisor */
 903                 if (hz >= (host->src_clk_freq >> 1)) {
 904                         div = 0; /* mean div = 1/2 */
 905                         sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
 906                 } else {
 907                         div = (host->src_clk_freq + ((hz << 2) - 1)) /
 908                                (hz << 2);
 909                         sclk = (host->src_clk_freq >> 2) / div;
 910                 }
 911         }
 912
 913         clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
 914
 915         if (host->dev_comp->clk_div_bits == 8) {
 916                 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
 917                 clrsetbits_le32(&host->base->msdc_cfg,
 918                                 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
 919                                 (mode << MSDC_CFG_CKMOD_S) |
 920                                 (div << MSDC_CFG_CKDIV_S));
 921         } else {
 922                 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
 923                                       MSDC_CFG_CKDIV_EXT_S));
 924                 clrsetbits_le32(&host->base->msdc_cfg,
 925                                 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
 926                                 (mode << MSDC_CFG_CKMOD_EXT_S) |
 927                                 (div << MSDC_CFG_CKDIV_EXT_S));
 928         }
 929
 930         readl_poll_timeout(&host->base->msdc_cfg, reg,
 931                            reg & MSDC_CFG_CKSTB, 1000000);
 932
 933         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
 934         host->sclk = sclk;
 935         host->mclk = hz;
 936         host->timing = timing;
 937
 938         /* needed because clk changed. */
 939         msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
 940
 941         /*
 942          * mmc_select_hs400() will drop to 50Mhz and High speed mode,
 943          * tune result of hs200/200Mhz is not suitable for 50Mhz
 944          */
 945         if (host->sclk <= 52000000) {
 946                 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
 947                 writel(host->def_tune_para.pad_tune,
 948                        &host->base->pad_tune);
 949         } else {
 950                 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
 951                 writel(host->saved_tune_para.pad_tune,
 952                        &host->base->pad_tune);
 953         }
 954
 955         dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
 956 }
 957
 958 static int msdc_ops_set_ios(struct udevice *dev)
 959 {
 960         struct msdc_plat *plat = dev_get_plat(dev);
 961         struct msdc_host *host = dev_get_priv(dev);
 962         struct mmc *mmc = &plat->mmc;
 963         uint clock = mmc->clock;
 964
 965         msdc_set_buswidth(host, mmc->bus_width);
 966
 967         if (mmc->clk_disable)
 968                 clock = 0;
 969         else if (clock < mmc->cfg->f_min)
 970                 clock = mmc->cfg->f_min;
 971
 972         if (host->mclk != clock || host->timing != mmc->selected_mode)
 973                 msdc_set_mclk(dev, host, mmc->selected_mode, clock);
 974
 975         return 0;
 976 }
 977
 978 static int msdc_ops_get_cd(struct udevice *dev)
 979 {
 980         struct msdc_host *host = dev_get_priv(dev);
 981         u32 val;
 982
 983         if (host->builtin_cd) {
 984                 val = readl(&host->base->msdc_ps);
 985                 val = !!(val & MSDC_PS_CDSTS);
 986
 987                 return !val ^ host->cd_active_high;
 988         }
 989
 990 #if CONFIG_IS_ENABLED(DM_GPIO)
 991         if (!host->gpio_cd.dev)
 992                 return 1;
 993
 994         return dm_gpio_get_value(&host->gpio_cd);
 995 #else
 996         return 1;
 997 #endif
 998 }
 999
1000 static int msdc_ops_get_wp(struct udevice *dev)
1001 {
1002 #if CONFIG_IS_ENABLED(DM_GPIO)
1003         struct msdc_host *host = dev_get_priv(dev);
1004
1005         if (!host->gpio_wp.dev)
1006                 return 0;
1007
1008         return !dm_gpio_get_value(&host->gpio_wp);
1009 #else
1010         return 0;
1011 #endif
1012 }
1013
1014 #ifdef MMC_SUPPORTS_TUNING
1015 static u32 test_delay_bit(u32 delay, u32 bit)
1016 {
1017         bit %= PAD_DELAY_MAX;
1018         return delay & (1 << bit);
1019 }
1020
1021 static int get_delay_len(u32 delay, u32 start_bit)
1022 {
1023         int i;
1024
1025         for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1026                 if (test_delay_bit(delay, start_bit + i) == 0)
1027                         return i;
1028         }
1029
1030         return PAD_DELAY_MAX - start_bit;
1031 }
1032
1033 static struct msdc_delay_phase get_best_delay(struct udevice *dev,
1034                                               struct msdc_host *host, u32 delay)
1035 {
1036         int start = 0, len = 0;
1037         int start_final = 0, len_final = 0;
1038         u8 final_phase = 0xff;
1039         struct msdc_delay_phase delay_phase = { 0, };
1040
1041         if (delay == 0) {
1042                 dev_err(dev, "phase error: [map:%x]\n", delay);
1043                 delay_phase.final_phase = final_phase;
1044                 return delay_phase;
1045         }
1046
1047         while (start < PAD_DELAY_MAX) {
1048                 len = get_delay_len(delay, start);
1049                 if (len_final < len) {
1050                         start_final = start;
1051                         len_final = len;
1052                 }
1053
1054                 start += len ? len : 1;
1055                 if (len >= 12 && start_final < 4)
1056                         break;
1057         }
1058
1059         /* The rule is to find the smallest delay cell */
1060         if (start_final == 0)
1061                 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1062         else
1063                 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1064
1065         dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1066                  delay, len_final, final_phase);
1067
1068         delay_phase.maxlen = len_final;
1069         delay_phase.start = start_final;
1070         delay_phase.final_phase = final_phase;
1071         return delay_phase;
1072 }
1073
1074 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1075 {
1076         void __iomem *tune_reg = &host->base->pad_tune;
1077
1078         if (host->dev_comp->pad_tune0)
1079                 tune_reg = &host->base->pad_tune0;
1080
1081         if (host->top_base)
1082                 clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
1083                                 value << PAD_CMD_RXDLY_S);
1084         else
1085                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1086                                 value << MSDC_PAD_TUNE_CMDRDLY_S);
1087 }
1088
1089 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1090 {
1091         void __iomem *tune_reg = &host->base->pad_tune;
1092
1093         if (host->dev_comp->pad_tune0)
1094                 tune_reg = &host->base->pad_tune0;
1095
1096         if (host->top_base)
1097                 clrsetbits_le32(&host->top_base->emmc_top_control,
1098                                 PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
1099         else
1100                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1101                                 value << MSDC_PAD_TUNE_DATRRDLY_S);
1102 }
1103
1104 static int hs400_tune_response(struct udevice *dev, u32 opcode)
1105 {
1106         struct msdc_plat *plat = dev_get_plat(dev);
1107         struct msdc_host *host = dev_get_priv(dev);
1108         struct mmc *mmc = &plat->mmc;
1109         u32 cmd_delay  = 0;
1110         struct msdc_delay_phase final_cmd_delay = { 0, };
1111         u8 final_delay;
1112         void __iomem *tune_reg = &host->base->pad_cmd_tune;
1113         int cmd_err;
1114         int i, j;
1115
1116         setbits_le32(&host->base->pad_cmd_tune, BIT(0));
1117
1118         if (mmc->selected_mode == MMC_HS_200 ||
1119             mmc->selected_mode == UHS_SDR104)
1120                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1121                                 host->hs200_cmd_int_delay <<
1122                                 MSDC_PAD_TUNE_CMDRRDLY_S);
1123
1124         if (host->r_smpl)
1125                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1126         else
1127                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1128
1129         for (i = 0; i < PAD_DELAY_MAX; i++) {
1130                 clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1131                                 i << PAD_CMD_TUNE_RX_DLY3_S);
1132
1133                 for (j = 0; j < 3; j++) {
1134                         mmc_send_tuning(mmc, opcode, &cmd_err);
1135                         if (!cmd_err) {
1136                                 cmd_delay |= (1 << i);
1137                         } else {
1138                                 cmd_delay &= ~(1 << i);
1139                                 break;
1140                         }
1141                 }
1142         }
1143
1144         final_cmd_delay = get_best_delay(dev, host, cmd_delay);
1145         clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1146                         final_cmd_delay.final_phase <<
1147                         PAD_CMD_TUNE_RX_DLY3_S);
1148         final_delay = final_cmd_delay.final_phase;
1149
1150         dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
1151         return final_delay == 0xff ? -EIO : 0;
1152 }
1153
1154 static int msdc_tune_response(struct udevice *dev, u32 opcode)
1155 {
1156         struct msdc_plat *plat = dev_get_plat(dev);
1157         struct msdc_host *host = dev_get_priv(dev);
1158         struct mmc *mmc = &plat->mmc;
1159         u32 rise_delay = 0, fall_delay = 0;
1160         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1161         struct msdc_delay_phase internal_delay_phase;
1162         u8 final_delay, final_maxlen;
1163         u32 internal_delay = 0;
1164         void __iomem *tune_reg = &host->base->pad_tune;
1165         int cmd_err;
1166         int i, j;
1167
1168         if (host->dev_comp->pad_tune0)
1169                 tune_reg = &host->base->pad_tune0;
1170
1171         if (mmc->selected_mode == MMC_HS_200 ||
1172             mmc->selected_mode == UHS_SDR104)
1173                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1174                                 host->hs200_cmd_int_delay <<
1175                                 MSDC_PAD_TUNE_CMDRRDLY_S);
1176
1177         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1178
1179         for (i = 0; i < PAD_DELAY_MAX; i++) {
1180                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1181                                 i << MSDC_PAD_TUNE_CMDRDLY_S);
1182
1183                 for (j = 0; j < 3; j++) {
1184                         mmc_send_tuning(mmc, opcode, &cmd_err);
1185                         if (!cmd_err) {
1186                                 rise_delay |= (1 << i);
1187                         } else {
1188                                 rise_delay &= ~(1 << i);
1189                                 break;
1190                         }
1191                 }
1192         }
1193
1194         final_rise_delay = get_best_delay(dev, host, rise_delay);
1195         /* if rising edge has enough margin, do not scan falling edge */
1196         if (final_rise_delay.maxlen >= 12 ||
1197             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1198                 goto skip_fall;
1199
1200         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1201         for (i = 0; i < PAD_DELAY_MAX; i++) {
1202                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1203                                 i << MSDC_PAD_TUNE_CMDRDLY_S);
1204
1205                 for (j = 0; j < 3; j++) {
1206                         mmc_send_tuning(mmc, opcode, &cmd_err);
1207                         if (!cmd_err) {
1208                                 fall_delay |= (1 << i);
1209                         } else {
1210                                 fall_delay &= ~(1 << i);
1211                                 break;
1212                         }
1213                 }
1214         }
1215
1216         final_fall_delay = get_best_delay(dev, host, fall_delay);
1217
1218 skip_fall:
1219         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1220         if (final_maxlen == final_rise_delay.maxlen) {
1221                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1222                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1223                                 final_rise_delay.final_phase <<
1224                                 MSDC_PAD_TUNE_CMDRDLY_S);
1225                 final_delay = final_rise_delay.final_phase;
1226         } else {
1227                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1228                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1229                                 final_fall_delay.final_phase <<
1230                                 MSDC_PAD_TUNE_CMDRDLY_S);
1231                 final_delay = final_fall_delay.final_phase;
1232         }
1233
1234         if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1235                 goto skip_internal;
1236
1237         for (i = 0; i < PAD_DELAY_MAX; i++) {
1238                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1239                                 i << MSDC_PAD_TUNE_CMDRRDLY_S);
1240
1241                 mmc_send_tuning(mmc, opcode, &cmd_err);
1242                 if (!cmd_err)
1243                         internal_delay |= (1 << i);
1244         }
1245
1246         dev_dbg(dev, "Final internal delay: 0x%x\n", internal_delay);
1247
1248         internal_delay_phase = get_best_delay(dev, host, internal_delay);
1249         clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1250                         internal_delay_phase.final_phase <<
1251                         MSDC_PAD_TUNE_CMDRRDLY_S);
1252
1253 skip_internal:
1254         dev_dbg(dev, "Final cmd pad delay: %x\n", final_delay);
1255         return final_delay == 0xff ? -EIO : 0;
1256 }
1257
1258 static int msdc_tune_data(struct udevice *dev, u32 opcode)
1259 {
1260         struct msdc_plat *plat = dev_get_plat(dev);
1261         struct msdc_host *host = dev_get_priv(dev);
1262         struct mmc *mmc = &plat->mmc;
1263         u32 rise_delay = 0, fall_delay = 0;
1264         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1265         u8 final_delay, final_maxlen;
1266         void __iomem *tune_reg = &host->base->pad_tune;
1267         int cmd_err;
1268         int i, ret;
1269
1270         if (host->dev_comp->pad_tune0)
1271                 tune_reg = &host->base->pad_tune0;
1272
1273         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1274         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1275
1276         for (i = 0; i < PAD_DELAY_MAX; i++) {
1277                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1278                                 i << MSDC_PAD_TUNE_DATRRDLY_S);
1279
1280                 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1281                 if (!ret) {
1282                         rise_delay |= (1 << i);
1283                 } else if (cmd_err) {
1284                         /* in this case, retune response is needed */
1285                         ret = msdc_tune_response(dev, opcode);
1286                         if (ret)
1287                                 break;
1288                 }
1289         }
1290
1291         final_rise_delay = get_best_delay(dev, host, rise_delay);
1292         if (final_rise_delay.maxlen >= 12 ||
1293             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1294                 goto skip_fall;
1295
1296         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1297         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1298
1299         for (i = 0; i < PAD_DELAY_MAX; i++) {
1300                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1301                                 i << MSDC_PAD_TUNE_DATRRDLY_S);
1302
1303                 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1304                 if (!ret) {
1305                         fall_delay |= (1 << i);
1306                 } else if (cmd_err) {
1307                         /* in this case, retune response is needed */
1308                         ret = msdc_tune_response(dev, opcode);
1309                         if (ret)
1310                                 break;
1311                 }
1312         }
1313
1314         final_fall_delay = get_best_delay(dev, host, fall_delay);
1315
1316 skip_fall:
1317         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1318         if (final_maxlen == final_rise_delay.maxlen) {
1319                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1320                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1321                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1322                                 final_rise_delay.final_phase <<
1323                                 MSDC_PAD_TUNE_DATRRDLY_S);
1324                 final_delay = final_rise_delay.final_phase;
1325         } else {
1326                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1327                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1328                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1329                                 final_fall_delay.final_phase <<
1330                                 MSDC_PAD_TUNE_DATRRDLY_S);
1331                 final_delay = final_fall_delay.final_phase;
1332         }
1333
1334         if (mmc->selected_mode == MMC_HS_200 ||
1335             mmc->selected_mode == UHS_SDR104)
1336                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
1337                                 host->hs200_write_int_delay <<
1338                                 MSDC_PAD_TUNE_DATWRDLY_S);
1339
1340         dev_dbg(dev, "Final data pad delay: %x\n", final_delay);
1341
1342         return final_delay == 0xff ? -EIO : 0;
1343 }
1344
1345 /*
1346  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
1347  * together, which can save the tuning time.
1348  */
1349 static int msdc_tune_together(struct udevice *dev, u32 opcode)
1350 {
1351         struct msdc_plat *plat = dev_get_plat(dev);
1352         struct msdc_host *host = dev_get_priv(dev);
1353         struct mmc *mmc = &plat->mmc;
1354         u32 rise_delay = 0, fall_delay = 0;
1355         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1356         u8 final_delay, final_maxlen;
1357         int i, ret;
1358
1359         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1360         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1361
1362         for (i = 0; i < PAD_DELAY_MAX; i++) {
1363                 msdc_set_cmd_delay(host, i);
1364                 msdc_set_data_delay(host, i);
1365                 ret = mmc_send_tuning(mmc, opcode, NULL);
1366                 if (!ret)
1367                         rise_delay |= (1 << i);
1368         }
1369
1370         final_rise_delay = get_best_delay(dev, host, rise_delay);
1371         if (final_rise_delay.maxlen >= 12 ||
1372             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1373                 goto skip_fall;
1374
1375         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1376         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1377
1378         for (i = 0; i < PAD_DELAY_MAX; i++) {
1379                 msdc_set_cmd_delay(host, i);
1380                 msdc_set_data_delay(host, i);
1381                 ret = mmc_send_tuning(mmc, opcode, NULL);
1382                 if (!ret)
1383                         fall_delay |= (1 << i);
1384         }
1385
1386         final_fall_delay = get_best_delay(dev, host, fall_delay);
1387
1388 skip_fall:
1389         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1390         if (final_maxlen == final_rise_delay.maxlen) {
1391                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1392                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1393                 final_delay = final_rise_delay.final_phase;
1394         } else {
1395                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1396                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1397                 final_delay = final_fall_delay.final_phase;
1398         }
1399
1400         msdc_set_cmd_delay(host, final_delay);
1401         msdc_set_data_delay(host, final_delay);
1402
1403         dev_info(dev, "Final pad delay: %x\n", final_delay);
1404         return final_delay == 0xff ? -EIO : 0;
1405 }
1406
1407 static int msdc_execute_tuning(struct udevice *dev, uint opcode)
1408 {
1409         struct msdc_plat *plat = dev_get_plat(dev);
1410         struct msdc_host *host = dev_get_priv(dev);
1411         struct mmc *mmc = &plat->mmc;
1412         int ret = 0;
1413
1414         if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
1415                 ret = msdc_tune_together(dev, opcode);
1416                 if (ret == -EIO) {
1417                         dev_err(dev, "Tune fail!\n");
1418                         return ret;
1419                 }
1420
1421                 if (mmc->selected_mode == MMC_HS_400) {
1422                         clrbits_le32(&host->base->msdc_iocon,
1423                                      MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1424                         clrsetbits_le32(&host->base->pad_tune,
1425                                         MSDC_PAD_TUNE_DATRRDLY_M, 0);
1426
1427                         writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1428                         /* for hs400 mode it must be set to 0 */
1429                         clrbits_le32(&host->base->patch_bit2,
1430                                      MSDC_PB2_CFGCRCSTS);
1431                         host->hs400_mode = true;
1432                 }
1433                 goto tune_done;
1434         }
1435
1436         if (mmc->selected_mode == MMC_HS_400)
1437                 ret = hs400_tune_response(dev, opcode);
1438         else
1439                 ret = msdc_tune_response(dev, opcode);
1440         if (ret == -EIO) {
1441                 dev_err(dev, "Tune response fail!\n");
1442                 return ret;
1443         }
1444
1445         if (mmc->selected_mode != MMC_HS_400) {
1446                 ret = msdc_tune_data(dev, opcode);
1447                 if (ret == -EIO) {
1448                         dev_err(dev, "Tune data fail!\n");
1449                         return ret;
1450                 }
1451         }
1452
1453 tune_done:
1454         host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1455         host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
1456         host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
1457
1458         return ret;
1459 }
1460 #endif
1461
1462 static void msdc_init_hw(struct msdc_host *host)
1463 {
1464         u32 val;
1465         void __iomem *tune_reg = &host->base->pad_tune;
1466         void __iomem *rd_dly0_reg = &host->base->pad_tune0;
1467         void __iomem *rd_dly1_reg = &host->base->pad_tune1;
1468
1469         if (host->dev_comp->pad_tune0) {
1470                 tune_reg = &host->base->pad_tune0;
1471                 rd_dly0_reg = &host->base->dat_rd_dly[0];
1472                 rd_dly1_reg = &host->base->dat_rd_dly[1];
1473         }
1474
1475         /* Configure to MMC/SD mode, clock free running */
1476         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1477
1478         /* Use PIO mode */
1479         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1480
1481         /* Reset */
1482         msdc_reset_hw(host);
1483
1484         /* Enable/disable hw card detection according to fdt option */
1485         if (host->builtin_cd)
1486                 clrsetbits_le32(&host->base->msdc_ps,
1487                         MSDC_PS_CDDBCE_M,
1488                         (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
1489                         MSDC_PS_CDEN);
1490         else
1491                 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1492
1493         /* Clear all interrupts */
1494         val = readl(&host->base->msdc_int);
1495         writel(val, &host->base->msdc_int);
1496
1497         /* Enable data & cmd interrupts */
1498         writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1499
1500         if (host->top_base) {
1501                 writel(0, &host->top_base->emmc_top_control);
1502                 writel(0, &host->top_base->emmc_top_cmd);
1503         } else {
1504                 writel(0, tune_reg);
1505         }
1506         writel(0, &host->base->msdc_iocon);
1507
1508         if (host->r_smpl)
1509                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1510         else
1511                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1512
1513         writel(0x403c0046, &host->base->patch_bit0);
1514         writel(0xffff4089, &host->base->patch_bit1);
1515
1516         if (host->dev_comp->stop_clk_fix) {
1517                 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1518                                 3 << MSDC_PB1_STOP_DLY_S);
1519                 clrbits_le32(&host->base->sdc_fifo_cfg,
1520                              SDC_FIFO_CFG_WRVALIDSEL);
1521                 clrbits_le32(&host->base->sdc_fifo_cfg,
1522                              SDC_FIFO_CFG_RDVALIDSEL);
1523         }
1524
1525         if (host->dev_comp->busy_check)
1526                 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1527
1528         setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1529
1530         if (host->dev_comp->async_fifo) {
1531                 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1532                                 3 << MSDC_PB2_RESPWAIT_S);
1533
1534                 if (host->dev_comp->enhance_rx) {
1535                         if (host->top_base)
1536                                 setbits_le32(&host->top_base->emmc_top_control,
1537                                              SDC_RX_ENH_EN);
1538                         else
1539                                 setbits_le32(&host->base->sdc_adv_cfg0,
1540                                              SDC_RX_ENHANCE_EN);
1541                 } else {
1542                         clrsetbits_le32(&host->base->patch_bit2,
1543                                         MSDC_PB2_RESPSTSENSEL_M,
1544                                         2 << MSDC_PB2_RESPSTSENSEL_S);
1545                         clrsetbits_le32(&host->base->patch_bit2,
1546                                         MSDC_PB2_CRCSTSENSEL_M,
1547                                         2 << MSDC_PB2_CRCSTSENSEL_S);
1548                 }
1549
1550                 /* use async fifo to avoid tune internal delay */
1551                 clrbits_le32(&host->base->patch_bit2,
1552                              MSDC_PB2_CFGRESP);
1553                 clrbits_le32(&host->base->patch_bit2,
1554                              MSDC_PB2_CFGCRCSTS);
1555         }
1556
1557         if (host->dev_comp->data_tune) {
1558                 if (host->top_base) {
1559                         setbits_le32(&host->top_base->emmc_top_control,
1560                                      PAD_DAT_RD_RXDLY_SEL);
1561                         clrbits_le32(&host->top_base->emmc_top_control,
1562                                      DATA_K_VALUE_SEL);
1563                         setbits_le32(&host->top_base->emmc_top_cmd,
1564                                      PAD_CMD_RD_RXDLY_SEL);
1565                 } else {
1566                         setbits_le32(tune_reg,
1567                                      MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1568                         clrsetbits_le32(&host->base->patch_bit0,
1569                                         MSDC_INT_DAT_LATCH_CK_SEL_M,
1570                                         host->latch_ck <<
1571                                         MSDC_INT_DAT_LATCH_CK_SEL_S);
1572                 }
1573         } else {
1574                 /* choose clock tune */
1575                 if (host->top_base)
1576                         setbits_le32(&host->top_base->emmc_top_control,
1577                                      PAD_RXDLY_SEL);
1578                 else
1579                         setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1580         }
1581
1582         if (host->dev_comp->builtin_pad_ctrl) {
1583                 /* Set pins driving strength */
1584                 writel(MSDC_PAD_CTRL0_CLKPD | MSDC_PAD_CTRL0_CLKSMT |
1585                        MSDC_PAD_CTRL0_CLKIES | (4 << MSDC_PAD_CTRL0_CLKDRVN_S) |
1586                        (4 << MSDC_PAD_CTRL0_CLKDRVP_S), &host->base->pad_ctrl0);
1587                 writel(MSDC_PAD_CTRL1_CMDPU | MSDC_PAD_CTRL1_CMDSMT |
1588                        MSDC_PAD_CTRL1_CMDIES | (4 << MSDC_PAD_CTRL1_CMDDRVN_S) |
1589                        (4 << MSDC_PAD_CTRL1_CMDDRVP_S), &host->base->pad_ctrl1);
1590                 writel(MSDC_PAD_CTRL2_DATPU | MSDC_PAD_CTRL2_DATSMT |
1591                        MSDC_PAD_CTRL2_DATIES | (4 << MSDC_PAD_CTRL2_DATDRVN_S) |
1592                        (4 << MSDC_PAD_CTRL2_DATDRVP_S), &host->base->pad_ctrl2);
1593         }
1594
1595         if (host->dev_comp->default_pad_dly) {
1596                 /* Default pad delay may be needed if tuning not enabled */
1597                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CLKTDLY_M |
1598                                 MSDC_PAD_TUNE_CMDRRDLY_M |
1599                                 MSDC_PAD_TUNE_CMDRDLY_M |
1600                                 MSDC_PAD_TUNE_DATRRDLY_M |
1601                                 MSDC_PAD_TUNE_DATWRDLY_M,
1602                                 (0x10 << MSDC_PAD_TUNE_CLKTDLY_S) |
1603                                 (0x10 << MSDC_PAD_TUNE_CMDRRDLY_S) |
1604                                 (0x10 << MSDC_PAD_TUNE_CMDRDLY_S) |
1605                                 (0x10 << MSDC_PAD_TUNE_DATRRDLY_S) |
1606                                 (0x10 << MSDC_PAD_TUNE_DATWRDLY_S));
1607
1608                 writel((0x10 << MSDC_PAD_TUNE0_DAT0RDDLY_S) |
1609                        (0x10 << MSDC_PAD_TUNE0_DAT1RDDLY_S) |
1610                        (0x10 << MSDC_PAD_TUNE0_DAT2RDDLY_S) |
1611                        (0x10 << MSDC_PAD_TUNE0_DAT3RDDLY_S),
1612                        rd_dly0_reg);
1613
1614                 writel((0x10 << MSDC_PAD_TUNE1_DAT4RDDLY_S) |
1615                        (0x10 << MSDC_PAD_TUNE1_DAT5RDDLY_S) |
1616                        (0x10 << MSDC_PAD_TUNE1_DAT6RDDLY_S) |
1617                        (0x10 << MSDC_PAD_TUNE1_DAT7RDDLY_S),
1618                        rd_dly1_reg);
1619         }
1620
1621         /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
1622         setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1623
1624         /* disable detecting SDIO device interrupt function */
1625         clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1626
1627         /* Configure to default data timeout */
1628         clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1629                         3 << SDC_CFG_DTOC_S);
1630
1631
1632         host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1633         host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1634 }
1635
1636 static void msdc_ungate_clock(struct msdc_host *host)
1637 {
1638         clk_enable(&host->src_clk);
1639         clk_enable(&host->h_clk);
1640         if (host->src_clk_cg.dev)
1641                 clk_enable(&host->src_clk_cg);
1642 }
1643
1644 static int msdc_drv_probe(struct udevice *dev)
1645 {
1646         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1647         struct msdc_plat *plat = dev_get_plat(dev);
1648         struct msdc_host *host = dev_get_priv(dev);
1649         struct mmc_config *cfg = &plat->cfg;
1650
1651         cfg->name = dev->name;
1652
1653         host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1654
1655         host->src_clk_freq = clk_get_rate(&host->src_clk);
1656
1657         if (host->dev_comp->clk_div_bits == 8)
1658                 cfg->f_min = host->src_clk_freq / (4 * 255);
1659         else
1660                 cfg->f_min = host->src_clk_freq / (4 * 4095);
1661
1662         if (cfg->f_min < MIN_BUS_CLK)
1663                 cfg->f_min = MIN_BUS_CLK;
1664
1665         if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq)
1666                 cfg->f_max = host->src_clk_freq;
1667
1668         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1669         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1670
1671         host->mmc = &plat->mmc;
1672         host->timeout_ns = 100000000;
1673         host->timeout_clks = 3 * (1 << SCLK_CYCLES_SHIFT);
1674
1675 #ifdef CONFIG_PINCTRL
1676         pinctrl_select_state(dev, "default");
1677 #endif
1678
1679         msdc_ungate_clock(host);
1680         msdc_init_hw(host);
1681
1682         upriv->mmc = &plat->mmc;
1683
1684         return 0;
1685 }
1686
1687 static int msdc_of_to_plat(struct udevice *dev)
1688 {
1689         struct msdc_plat *plat = dev_get_plat(dev);
1690         struct msdc_host *host = dev_get_priv(dev);
1691         struct mmc_config *cfg = &plat->cfg;
1692         fdt_addr_t base, top_base;
1693         int ret;
1694
1695         base = dev_read_addr(dev);
1696         if (base == FDT_ADDR_T_NONE)
1697                 return -EINVAL;
1698         host->base = map_sysmem(base, 0);
1699
1700         top_base = dev_read_addr_index(dev, 1);
1701         if (top_base == FDT_ADDR_T_NONE)
1702                 host->top_base = NULL;
1703         else
1704                 host->top_base = map_sysmem(top_base, 0);
1705
1706         ret = mmc_of_parse(dev, cfg);
1707         if (ret)
1708                 return ret;
1709
1710         ret = clk_get_by_name(dev, "source", &host->src_clk);
1711         if (ret < 0)
1712                 return ret;
1713
1714         ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1715         if (ret < 0)
1716                 return ret;
1717
1718         clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1719
1720 #if CONFIG_IS_ENABLED(DM_GPIO)
1721         gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1722         gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1723 #endif
1724
1725         host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1726         host->hs200_cmd_int_delay =
1727                         dev_read_u32_default(dev, "cmd_int_delay", 0);
1728         host->hs200_write_int_delay =
1729                         dev_read_u32_default(dev, "write_int_delay", 0);
1730         host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1731         host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1732         host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
1733         host->cd_active_high = dev_read_bool(dev, "cd-active-high");
1734
1735         return 0;
1736 }
1737
1738 static int msdc_drv_bind(struct udevice *dev)
1739 {
1740         struct msdc_plat *plat = dev_get_plat(dev);
1741
1742         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1743 }
1744
1745 static int msdc_ops_wait_dat0(struct udevice *dev, int state, int timeout_us)
1746 {
1747         struct msdc_host *host = dev_get_priv(dev);
1748         int ret;
1749         u32 reg;
1750
1751         ret = readl_poll_sleep_timeout(&host->base->msdc_ps, reg,
1752                                        !!(reg & MSDC_PS_DAT0) == !!state,
1753                                        1000, /* 1 ms */
1754                                        timeout_us);
1755
1756         return ret;
1757 }
1758
1759 static const struct dm_mmc_ops msdc_ops = {
1760         .send_cmd = msdc_ops_send_cmd,
1761         .set_ios = msdc_ops_set_ios,
1762         .get_cd = msdc_ops_get_cd,
1763         .get_wp = msdc_ops_get_wp,
1764 #ifdef MMC_SUPPORTS_TUNING
1765         .execute_tuning = msdc_execute_tuning,
1766 #endif
1767         .wait_dat0 = msdc_ops_wait_dat0,
1768 };
1769
1770 static const struct msdc_compatible mt7620_compat = {
1771         .clk_div_bits = 8,
1772         .pad_tune0 = false,
1773         .async_fifo = false,
1774         .data_tune = false,
1775         .busy_check = false,
1776         .stop_clk_fix = false,
1777         .enhance_rx = false,
1778         .builtin_pad_ctrl = true,
1779         .default_pad_dly = true,
1780 };
1781
1782 static const struct msdc_compatible mt7621_compat = {
1783         .clk_div_bits = 8,
1784         .pad_tune0 = false,
1785         .async_fifo = true,
1786         .data_tune = true,
1787         .busy_check = false,
1788         .stop_clk_fix = false,
1789         .enhance_rx = false,
1790         .builtin_pad_ctrl = true,
1791         .default_pad_dly = true,
1792 };
1793
1794 static const struct msdc_compatible mt7622_compat = {
1795         .clk_div_bits = 12,
1796         .pad_tune0 = true,
1797         .async_fifo = true,
1798         .data_tune = true,
1799         .busy_check = true,
1800         .stop_clk_fix = true,
1801 };
1802
1803 static const struct msdc_compatible mt7623_compat = {
1804         .clk_div_bits = 12,
1805         .pad_tune0 = true,
1806         .async_fifo = true,
1807         .data_tune = true,
1808         .busy_check = false,
1809         .stop_clk_fix = false,
1810         .enhance_rx = false
1811 };
1812
1813 static const struct msdc_compatible mt7986_compat = {
1814         .clk_div_bits = 12,
1815         .pad_tune0 = true,
1816         .async_fifo = true,
1817         .data_tune = true,
1818         .busy_check = true,
1819         .stop_clk_fix = true,
1820         .enhance_rx = true,
1821 };
1822
1823 static const struct msdc_compatible mt7981_compat = {
1824         .clk_div_bits = 12,
1825         .pad_tune0 = true,
1826         .async_fifo = true,
1827         .data_tune = true,
1828         .busy_check = true,
1829         .stop_clk_fix = true,
1830 };
1831
1832 static const struct msdc_compatible mt8512_compat = {
1833         .clk_div_bits = 12,
1834         .pad_tune0 = true,
1835         .async_fifo = true,
1836         .data_tune = true,
1837         .busy_check = true,
1838         .stop_clk_fix = true,
1839 };
1840
1841 static const struct msdc_compatible mt8516_compat = {
1842         .clk_div_bits = 12,
1843         .pad_tune0 = true,
1844         .async_fifo = true,
1845         .data_tune = true,
1846         .busy_check = true,
1847         .stop_clk_fix = true,
1848 };
1849
1850 static const struct msdc_compatible mt8183_compat = {
1851         .clk_div_bits = 12,
1852         .pad_tune0 = true,
1853         .async_fifo = true,
1854         .data_tune = true,
1855         .busy_check = true,
1856         .stop_clk_fix = true,
1857 };
1858
1859 static const struct udevice_id msdc_ids[] = {
1860         { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
1861         { .compatible = "mediatek,mt7621-mmc", .data = (ulong)&mt7621_compat },
1862         { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
1863         { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
1864         { .compatible = "mediatek,mt7986-mmc", .data = (ulong)&mt7986_compat },
1865         { .compatible = "mediatek,mt7981-mmc", .data = (ulong)&mt7981_compat },
1866         { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
1867         { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
1868         { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
1869         {}
1870 };
1871
1872 U_BOOT_DRIVER(mtk_sd_drv) = {
1873         .name = "mtk_sd",
1874         .id = UCLASS_MMC,
1875         .of_match = msdc_ids,
1876         .of_to_plat = msdc_of_to_plat,
1877         .bind = msdc_drv_bind,
1878         .probe = msdc_drv_probe,
1879         .ops = &msdc_ops,
1880         .plat_auto      = sizeof(struct msdc_plat),
1881         .priv_auto      = sizeof(struct msdc_host),
1882 };