2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
7 #define __CONFIG_SOCFPGA_COMMON_H__
9 /* Virtual target or real hardware */
10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
13 * High level configuration
15 #define CONFIG_DISPLAY_BOARDINFO_LATE
18 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
20 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
22 /* add target to build it automatically upon "make" */
23 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"
26 * Memory configurations
28 #define CONFIG_NR_DRAM_BANKS 1
29 #define PHYS_SDRAM_1 0x0
30 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
31 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
32 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
34 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
35 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
37 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
38 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
40 #define CONFIG_SYS_INIT_SP_OFFSET \
41 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
42 #define CONFIG_SYS_INIT_SP_ADDR \
43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
45 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
47 #define CONFIG_SYS_TEXT_BASE 0x08000040
49 #define CONFIG_SYS_TEXT_BASE 0x01000040
53 * U-Boot general configurations
55 #define CONFIG_SYS_LONGHELP
56 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
57 /* Print buffer size */
58 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
59 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
60 /* Boot argument buffer size */
61 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
62 #define CONFIG_CMDLINE_EDITING /* Command history etc */
64 #ifndef CONFIG_SYS_HOSTNAME
65 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
68 #define CONFIG_CMD_PXE
74 #define CONFIG_SYS_L2_PL310
75 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
78 * EPCS/EPCQx1 Serial Flash Controller
80 #ifdef CONFIG_ALTERA_SPI
81 #define CONFIG_SF_DEFAULT_SPEED 30000000
83 * The base address is configurable in QSys, each board must specify the
84 * base address based on it's particular FPGA configuration. Please note
85 * that the address here is incremented by 0x400 from the Base address
86 * selected in QSys, since the SPI registers are at offset +0x400.
87 * #define CONFIG_SYS_SPI_BASE 0xff240400
92 * Ethernet on SoC (EMAC)
94 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
95 #define CONFIG_DW_ALTDESCRIPTOR
102 #ifdef CONFIG_CMD_FPGA
103 #define CONFIG_FPGA_COUNT 1
109 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
110 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
111 #define CONFIG_SYS_TIMER_COUNTS_DOWN
112 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
113 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
114 #define CONFIG_SYS_TIMER_RATE 2400000
116 #define CONFIG_SYS_TIMER_RATE 25000000
122 #ifdef CONFIG_HW_WATCHDOG
123 #define CONFIG_DESIGNWARE_WATCHDOG
124 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
125 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
126 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000
132 #ifdef CONFIG_CMD_MMC
133 #define CONFIG_BOUNCE_BUFFER
135 /* using smaller max blk cnt to avoid flooding the limited stack we have */
136 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
142 #ifdef CONFIG_NAND_DENALI
143 #define CONFIG_SYS_MAX_NAND_DEVICE 1
144 #define CONFIG_SYS_NAND_ONFI_DETECTION
145 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
146 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
152 #define CONFIG_SYS_I2C
153 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
154 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
155 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
156 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
157 /* Using standard mode which the speed up to 100Kb/s */
158 #define CONFIG_SYS_I2C_SPEED 100000
159 #define CONFIG_SYS_I2C_SPEED1 100000
160 #define CONFIG_SYS_I2C_SPEED2 100000
161 #define CONFIG_SYS_I2C_SPEED3 100000
162 /* Address of device when used as slave */
163 #define CONFIG_SYS_I2C_SLAVE 0x02
164 #define CONFIG_SYS_I2C_SLAVE1 0x02
165 #define CONFIG_SYS_I2C_SLAVE2 0x02
166 #define CONFIG_SYS_I2C_SLAVE3 0x02
168 /* Clock supplied to I2C controller in unit of MHz */
169 unsigned int cm_get_l4_sp_clk_hz(void);
170 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
176 /* Enable multiple SPI NOR flash manufacturers */
177 #ifndef CONFIG_SPL_BUILD
178 #define CONFIG_SPI_FLASH_MTD
179 #define CONFIG_MTD_DEVICE
180 #define CONFIG_MTD_PARTITIONS
182 /* QSPI reference clock */
184 unsigned int cm_get_qspi_controller_clk_hz(void);
185 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
189 * Designware SPI support
195 #define CONFIG_SYS_NS16550_SERIAL
196 #define CONFIG_SYS_NS16550_REG_SIZE -4
197 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
198 #define CONFIG_SYS_NS16550_CLK 1000000
199 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
200 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
201 #define CONFIG_SYS_NS16550_CLK 100000000
202 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
203 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS
204 #define CONFIG_SYS_NS16550_CLK 50000000
206 #define CONFIG_CONS_INDEX 1
213 * USB Gadget (DFU, UMS)
215 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
216 #define CONFIG_USB_FUNCTION_MASS_STORAGE
218 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
219 #define DFU_DEFAULT_POLL_TIMEOUT 300
222 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
223 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
229 #if !defined(CONFIG_ENV_SIZE)
230 #define CONFIG_ENV_SIZE (8 * 1024)
233 /* Environment for SDMMC boot */
234 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
235 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
236 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */
239 /* Environment for QSPI boot */
240 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
241 #define CONFIG_ENV_OFFSET 0x00100000
242 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
246 * mtd partitioning for serial NOR flash
248 * device nor0 <ff705000.spi.0>, # parts = 6
249 * #: name size offset mask_flags
250 * 0: u-boot 0x00100000 0x00000000 0
251 * 1: env1 0x00040000 0x00100000 0
252 * 2: env2 0x00040000 0x00140000 0
253 * 3: UBI 0x03e80000 0x00180000 0
254 * 4: boot 0x00e80000 0x00180000 0
255 * 5: rootfs 0x01000000 0x01000000 0
262 * SRAM Memory layout:
264 * 0xFFFF_0000 ...... Start of SRAM
265 * 0xFFFF_xxxx ...... Top of stack (grows down)
266 * 0xFFFF_yyyy ...... Malloc area
267 * 0xFFFF_zzzz ...... Global Data
268 * 0xFFFF_FF00 ...... End of SRAM
270 #define CONFIG_SPL_FRAMEWORK
271 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
272 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
274 /* SPL SDMMC boot support */
275 #ifdef CONFIG_SPL_MMC_SUPPORT
276 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
277 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
278 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
281 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
282 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
286 /* SPL QSPI boot support */
287 #ifdef CONFIG_SPL_SPI_SUPPORT
288 #define CONFIG_SPL_SPI_LOAD
289 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
292 /* SPL NAND boot support */
293 #ifdef CONFIG_SPL_NAND_SUPPORT
294 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
295 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
301 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
303 /* Extra Environment */
304 #ifndef CONFIG_SPL_BUILD
305 #include <config_distro_defaults.h>
307 #ifdef CONFIG_CMD_PXE
308 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
310 #define BOOT_TARGET_DEVICES_PXE(func)
313 #ifdef CONFIG_CMD_MMC
314 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
316 #define BOOT_TARGET_DEVICES_MMC(func)
319 #define BOOT_TARGET_DEVICES(func) \
320 BOOT_TARGET_DEVICES_MMC(func) \
321 BOOT_TARGET_DEVICES_PXE(func) \
324 #include <config_distro_bootcmd.h>
326 #ifndef CONFIG_EXTRA_ENV_SETTINGS
327 #define CONFIG_EXTRA_ENV_SETTINGS \
328 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
329 "bootm_size=0xa000000\0" \
330 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
331 "fdt_addr_r=0x02000000\0" \
332 "scriptaddr=0x02100000\0" \
333 "pxefile_addr_r=0x02200000\0" \
334 "ramdisk_addr_r=0x02300000\0" \
340 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */