1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2019 Arcturus Networks, Inc.
4 * https://www.arcturusnetworks.com/products/ucp1020/
5 * based on include/configs/p1_p2_rdb_pc.h
6 * original copyright follows:
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
11 * QorIQ uCP1020-xx boards configuration file
16 #include <linux/stringify.h>
18 /*** Arcturus FirmWare Environment */
20 #define MAX_SERIAL_SIZE 15
21 #define MAX_HWADDR_SIZE 17
23 #define MAX_FWENV_ADDR 4
26 #define FWENV_SPI_FLASH 2
27 #define FWENV_NOR_FLASH 3
29 #define FWENV_TYPE FWENV_MMC
30 #define FWENV_TYPE FWENV_SPI_FLASH
32 #define FWENV_TYPE FWENV_NOR_FLASH
34 #if (FWENV_TYPE == FWENV_MMC)
35 #define FWENV_ADDR1 -1
36 #define FWENV_ADDR2 -1
37 #define FWENV_ADDR3 -1
38 #define FWENV_ADDR4 -1
42 #if (FWENV_TYPE == FWENV_SPI_FLASH)
43 #ifndef CONFIG_SF_DEFAULT_SPEED
44 #define CONFIG_SF_DEFAULT_SPEED 1000000
46 #ifndef CONFIG_SF_DEFAULT_MODE
47 #define CONFIG_SF_DEFAULT_MODE SPI_MODE0
49 #ifndef CONFIG_SF_DEFAULT_CS
50 #define CONFIG_SF_DEFAULT_CS 0
52 #ifndef CONFIG_SF_DEFAULT_BUS
53 #define CONFIG_SF_DEFAULT_BUS 0
55 #define FWENV_ADDR1 (0x200 - sizeof(smac))
56 #define FWENV_ADDR2 (0x400 - sizeof(smac))
57 #define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
58 #define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
59 #define EMPY_CHAR 0xff
62 #if (FWENV_TYPE == FWENV_NOR_FLASH)
63 #define FWENV_ADDR1 0xEC080000
64 #define FWENV_ADDR2 -1
65 #define FWENV_ADDR3 -1
66 #define FWENV_ADDR4 -1
67 #define EMPY_CHAR 0xff
69 /***********************************/
71 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
72 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
73 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
74 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
75 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
77 #if defined(CONFIG_TARTGET_UCP1020T1)
79 #define CONFIG_UCP1020_REV_1_3
81 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
85 #define CONFIG_HAS_ETH0
86 #define CONFIG_HAS_ETH1
87 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
88 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
89 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
90 #define CONFIG_IPADDR 10.80.41.229
91 #define CONFIG_SERVERIP 10.80.41.227
92 #define CONFIG_NETMASK 255.255.252.0
93 #define CONFIG_ETHPRIME "eTSEC3"
95 #define CONFIG_SYS_L2_SIZE (256 << 10)
99 #if defined(CONFIG_TARGET_UCP1020)
101 #define CONFIG_UCP1020
102 #define CONFIG_UCP1020_REV_1_3
104 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
108 #define CONFIG_HAS_ETH0
109 #define CONFIG_HAS_ETH1
110 #define CONFIG_HAS_ETH2
111 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
112 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
113 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
114 #define CONFIG_IPADDR 192.168.1.81
115 #define CONFIG_IPADDR1 192.168.1.82
116 #define CONFIG_IPADDR2 192.168.1.83
117 #define CONFIG_SERVERIP 192.168.1.80
118 #define CONFIG_GATEWAYIP 102.168.1.1
119 #define CONFIG_NETMASK 255.255.255.0
120 #define CONFIG_ETHPRIME "eTSEC1"
122 #define CONFIG_SYS_L2_SIZE (256 << 10)
127 #define CONFIG_RAMBOOT_SDCARD
128 #define CONFIG_SYS_RAMBOOT
129 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
132 #ifdef CONFIG_SPIFLASH
133 #define CONFIG_RAMBOOT_SPIFLASH
134 #define CONFIG_SYS_RAMBOOT
135 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
138 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
140 #ifndef CONFIG_RESET_VECTOR_ADDRESS
141 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
144 #ifndef CONFIG_SYS_MONITOR_BASE
145 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
148 #define CONFIG_SYS_SATA_MAX_DEVICE 2
151 #define CONFIG_SYS_CLK_FREQ 66666666
153 #define CONFIG_HWCONFIG
156 * These can be toggled for performance analysis, otherwise use default.
158 #define CONFIG_L2_CACHE
161 #define CONFIG_ENABLE_36BIT_PHYS
163 #define CONFIG_SYS_CCSRBAR 0xffe00000
164 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
166 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
168 #ifdef CONFIG_SPL_BUILD
169 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
173 #define CONFIG_SYS_SPD_BUS_NUM 1
175 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
176 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
177 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
178 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
179 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
181 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
183 /* Default settings for DDR3 */
184 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
185 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
186 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
187 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
188 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
189 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
191 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
192 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
193 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
194 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
196 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
197 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
198 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
199 #define CONFIG_SYS_DDR_RCW_1 0x00000000
200 #define CONFIG_SYS_DDR_RCW_2 0x00000000
201 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
202 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
203 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
204 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
206 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
207 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
208 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
209 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
210 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
211 #define CONFIG_SYS_DDR_MODE_1 0x40461520
212 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
213 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
218 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
219 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
220 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
221 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
223 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
224 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
225 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
229 * Local Bus Definitions
231 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
232 #define CONFIG_SYS_FLASH_BASE 0xec000000
234 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
236 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
239 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
241 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
242 #define CONFIG_SYS_FLASH_QUIET_TEST
243 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
245 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
247 #undef CONFIG_SYS_FLASH_CHECKSUM
248 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
249 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
251 #define CONFIG_SYS_FLASH_EMPTY_INFO
253 #define CONFIG_SYS_INIT_RAM_LOCK
254 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
255 /* Initial L1 address */
256 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
257 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
258 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
259 /* Size of used area in RAM */
260 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
262 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
263 GENERATED_GBL_DATA_SIZE)
264 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
266 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
267 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
269 #define CONFIG_SYS_PMC_BASE 0xff980000
270 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
271 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
273 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
274 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
277 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
278 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
279 #ifdef CONFIG_NAND_FSL_ELBC
280 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
281 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
284 /* Serial Port - controlled on board with jumper J8
288 #undef CONFIG_SERIAL_SOFTWARE_FIFO
289 #define CONFIG_SYS_NS16550_SERIAL
290 #define CONFIG_SYS_NS16550_REG_SIZE 1
291 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
292 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
293 #define CONFIG_NS16550_MIN_FUNCTIONS
296 #define CONFIG_SYS_BAUDRATE_TABLE \
297 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
299 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
300 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
303 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
304 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
306 #define CONFIG_RTC_DS1337
307 #define CONFIG_RTC_DS1337_NOOSC
308 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
309 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
310 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
311 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
313 #if defined(CONFIG_PCI)
316 * Memory space is mapped 1-1, but I/O space must start from 0.
319 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
320 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
321 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
322 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
323 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
324 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
325 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
326 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
327 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
328 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
330 /* controller 1, Slot 2, tgtid 1, Base address a000 */
331 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
332 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
333 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
334 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
335 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
336 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
337 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
338 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
339 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
341 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
342 #endif /* CONFIG_PCI */
347 #if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD)
348 #define CONFIG_FSL_FIXED_MMC_LOCATION
351 #define CONFIG_LOADS_ECHO /* echo on for serial download */
352 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
357 #define CONFIG_HAS_FSL_DR_USB
359 #if defined(CONFIG_HAS_FSL_DR_USB)
360 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
362 #ifdef CONFIG_USB_EHCI_HCD
363 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
364 #define CONFIG_USB_EHCI_FSL
368 #undef CONFIG_WATCHDOG /* watchdog disabled */
371 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
374 /* Misc Extra Settings */
375 #undef CONFIG_WATCHDOG /* watchdog disabled */
378 * Miscellaneous configurable options
380 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
381 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
384 * For booting Linux, the board info and command line data
385 * have to be in the first 64 MB of memory, since this is
386 * the maximum mapped by the Linux kernel during initialization.
388 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
389 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
391 #if defined(CONFIG_CMD_KGDB)
392 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
393 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
397 * Environment Configuration
400 #if defined(CONFIG_TSEC_ENET)
402 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
404 #error "UCP1020 module revision is not defined !!!"
407 #define CONFIG_BOOTP_SERVERIP
409 #define CONFIG_TSEC1_NAME "eTSEC1"
410 #define CONFIG_TSEC2_NAME "eTSEC2"
411 #define CONFIG_TSEC3_NAME "eTSEC3"
413 #define TSEC1_PHY_ADDR 4
414 #define TSEC2_PHY_ADDR 0
415 #define TSEC2_PHY_ADDR_SGMII 0x00
416 #define TSEC3_PHY_ADDR 6
418 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
419 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
420 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
422 #define TSEC1_PHYIDX 0
423 #define TSEC2_PHYIDX 0
424 #define TSEC3_PHYIDX 0
428 #define CONFIG_HOSTNAME "UCP1020"
429 #define CONFIG_ROOTPATH "/opt/nfsroot"
430 #define CONFIG_BOOTFILE "uImage"
431 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
433 #if defined(CONFIG_DONGLE)
435 #define CONFIG_EXTRA_ENV_SETTINGS \
436 "bootcmd=run prog_spi_mbrbootcramfs\0" \
437 "bootfile=uImage\0" \
438 "consoledev=ttyS0\0" \
439 "cramfsfile=image.cramfs\0" \
440 "dtbaddr=0x00c00000\0" \
441 "dtbfile=image.dtb\0" \
442 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
443 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
444 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
445 "fileaddr=0x01000000\0" \
446 "filesize=0x00080000\0" \
447 "flashmbr=sf probe 0; " \
448 "tftp $loadaddr $mbr; " \
449 "sf erase $mbr_offset +$filesize; " \
450 "sf write $loadaddr $mbr_offset $filesize\0" \
451 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
452 "protect off $nor_recoveryaddr +$filesize; " \
453 "erase $nor_recoveryaddr +$filesize; " \
454 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
455 "protect on $nor_recoveryaddr +$filesize\0 " \
456 "flashuboot=tftp $ubootaddr $ubootfile; " \
457 "protect off $nor_ubootaddr +$filesize; " \
458 "erase $nor_ubootaddr +$filesize; " \
459 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
460 "protect on $nor_ubootaddr +$filesize\0 " \
461 "flashworking=tftp $workingaddr $cramfsfile; " \
462 "protect off $nor_workingaddr +$filesize; " \
463 "erase $nor_workingaddr +$filesize; " \
464 "cp.b $workingaddr $nor_workingaddr $filesize; " \
465 "protect on $nor_workingaddr +$filesize\0 " \
466 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
467 "kerneladdr=0x01100000\0" \
468 "kernelfile=uImage\0" \
469 "loadaddr=0x01000000\0" \
470 "mbr=uCP1020d.mbr\0" \
471 "mbr_offset=0x00000000\0" \
472 "mmbr=uCP1020Quiet.mbr\0" \
474 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
476 "mmc write $loadaddr 1 1\0" \
477 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
478 "mmc erase 0x40 0x400; " \
479 "mmc write $loadaddr 0x40 0x400\0" \
481 "nor_recoveryaddr=0xEC0A0000\0" \
482 "nor_ubootaddr=0xEFF80000\0" \
483 "nor_workingaddr=0xECFA0000\0" \
484 "norbootrecovery=setenv bootargs $recoverybootargs" \
485 " console=$consoledev,$baudrate $othbootargs; " \
486 "run norloadrecovery; " \
487 "bootm $kerneladdr - $dtbaddr\0" \
488 "norbootworking=setenv bootargs $workingbootargs" \
489 " console=$consoledev,$baudrate $othbootargs; " \
490 "run norloadworking; " \
491 "bootm $kerneladdr - $dtbaddr\0" \
492 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
493 "setenv cramfsaddr $nor_recoveryaddr; " \
494 "cramfsload $dtbaddr $dtbfile; " \
495 "cramfsload $kerneladdr $kernelfile\0" \
496 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
497 "setenv cramfsaddr $nor_workingaddr; " \
498 "cramfsload $dtbaddr $dtbfile; " \
499 "cramfsload $kerneladdr $kernelfile\0" \
500 "prog_spi_mbr=run spi__mbr\0" \
501 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
502 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
503 "run spi__cramfs\0" \
504 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
505 " console=$consoledev,$baudrate $othbootargs; " \
506 "tftp $rootfsaddr $rootfsfile; " \
507 "tftp $loadaddr $kernelfile; " \
508 "tftp $dtbaddr $dtbfile; " \
509 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
510 "ramdisk_size=120000\0" \
511 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
512 "recoveryaddr=0x02F00000\0" \
513 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
514 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
515 "mw.l 0xffe0f008 0x00400000\0" \
516 "rootfsaddr=0x02F00000\0" \
517 "rootfsfile=rootfs.ext2.gz.uboot\0" \
518 "rootpath=/opt/nfsroot\0" \
519 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
520 "protect off 0xeC000000 +$filesize; " \
521 "erase 0xEC000000 +$filesize; " \
522 "cp.b $loadaddr 0xEC000000 $filesize; " \
523 "cmp.b $loadaddr 0xEC000000 $filesize; " \
524 "protect on 0xeC000000 +$filesize\0" \
525 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
526 "protect off 0xeFF80000 +$filesize; " \
527 "erase 0xEFF80000 +$filesize; " \
528 "cp.b $loadaddr 0xEFF80000 $filesize; " \
529 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
530 "protect on 0xeFF80000 +$filesize\0" \
531 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
532 "sf probe 0; sf erase 0x8000 +$filesize; " \
533 "sf write $loadaddr 0x8000 $filesize\0" \
534 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
535 "protect off 0xec0a0000 +$filesize; " \
536 "erase 0xeC0A0000 +$filesize; " \
537 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
538 "protect on 0xec0a0000 +$filesize\0" \
539 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
540 "sf probe 1; sf erase 0 +$filesize; " \
541 "sf write $loadaddr 0 $filesize\0" \
542 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
543 "sf probe 0; sf erase 0 +$filesize; " \
544 "sf write $loadaddr 0 $filesize\0" \
545 "tftpflash=tftpboot $loadaddr $uboot; " \
546 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
547 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
548 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
549 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
550 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
551 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
552 "ubootaddr=0x01000000\0" \
553 "ubootfile=u-boot.bin\0" \
554 "ubootd=u-boot4dongle.bin\0" \
555 "upgrade=run flashworking\0" \
556 "usb_phy_type=ulpi\0 " \
557 "workingaddr=0x02F00000\0" \
558 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
562 #if defined(CONFIG_UCP1020T1)
564 #define CONFIG_EXTRA_ENV_SETTINGS \
565 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
566 "bootfile=uImage\0" \
567 "consoledev=ttyS0\0" \
568 "cramfsfile=image.cramfs\0" \
569 "dtbaddr=0x00c00000\0" \
570 "dtbfile=image.dtb\0" \
571 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
572 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
573 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
574 "fileaddr=0x01000000\0" \
575 "filesize=0x00080000\0" \
576 "flashmbr=sf probe 0; " \
577 "tftp $loadaddr $mbr; " \
578 "sf erase $mbr_offset +$filesize; " \
579 "sf write $loadaddr $mbr_offset $filesize\0" \
580 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
581 "protect off $nor_recoveryaddr +$filesize; " \
582 "erase $nor_recoveryaddr +$filesize; " \
583 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
584 "protect on $nor_recoveryaddr +$filesize\0 " \
585 "flashuboot=tftp $ubootaddr $ubootfile; " \
586 "protect off $nor_ubootaddr +$filesize; " \
587 "erase $nor_ubootaddr +$filesize; " \
588 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
589 "protect on $nor_ubootaddr +$filesize\0 " \
590 "flashworking=tftp $workingaddr $cramfsfile; " \
591 "protect off $nor_workingaddr +$filesize; " \
592 "erase $nor_workingaddr +$filesize; " \
593 "cp.b $workingaddr $nor_workingaddr $filesize; " \
594 "protect on $nor_workingaddr +$filesize\0 " \
595 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
596 "kerneladdr=0x01100000\0" \
597 "kernelfile=uImage\0" \
598 "loadaddr=0x01000000\0" \
599 "mbr=uCP1020.mbr\0" \
600 "mbr_offset=0x00000000\0" \
602 "nor_recoveryaddr=0xEC0A0000\0" \
603 "nor_ubootaddr=0xEFF80000\0" \
604 "nor_workingaddr=0xECFA0000\0" \
605 "norbootrecovery=setenv bootargs $recoverybootargs" \
606 " console=$consoledev,$baudrate $othbootargs; " \
607 "run norloadrecovery; " \
608 "bootm $kerneladdr - $dtbaddr\0" \
609 "norbootworking=setenv bootargs $workingbootargs" \
610 " console=$consoledev,$baudrate $othbootargs; " \
611 "run norloadworking; " \
612 "bootm $kerneladdr - $dtbaddr\0" \
613 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
614 "setenv cramfsaddr $nor_recoveryaddr; " \
615 "cramfsload $dtbaddr $dtbfile; " \
616 "cramfsload $kerneladdr $kernelfile\0" \
617 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
618 "setenv cramfsaddr $nor_workingaddr; " \
619 "cramfsload $dtbaddr $dtbfile; " \
620 "cramfsload $kerneladdr $kernelfile\0" \
621 "othbootargs=quiet\0" \
622 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
623 " console=$consoledev,$baudrate $othbootargs; " \
624 "tftp $rootfsaddr $rootfsfile; " \
625 "tftp $loadaddr $kernelfile; " \
626 "tftp $dtbaddr $dtbfile; " \
627 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
628 "ramdisk_size=120000\0" \
629 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
630 "recoveryaddr=0x02F00000\0" \
631 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
632 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
633 "mw.l 0xffe0f008 0x00400000\0" \
634 "rootfsaddr=0x02F00000\0" \
635 "rootfsfile=rootfs.ext2.gz.uboot\0" \
636 "rootpath=/opt/nfsroot\0" \
638 "tftpflash=tftpboot $loadaddr $uboot; " \
639 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
640 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
641 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
642 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
643 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
644 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
645 "ubootaddr=0x01000000\0" \
646 "ubootfile=u-boot.bin\0" \
647 "upgrade=run flashworking\0" \
648 "workingaddr=0x02F00000\0" \
649 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
651 #else /* For Arcturus Modules */
653 #define CONFIG_EXTRA_ENV_SETTINGS \
654 "bootcmd=run norkernel\0" \
655 "bootfile=uImage\0" \
656 "consoledev=ttyS0\0" \
657 "dtbaddr=0x00c00000\0" \
658 "dtbfile=image.dtb\0" \
659 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
660 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
661 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
662 "fileaddr=0x01000000\0" \
663 "filesize=0x00080000\0" \
664 "flashmbr=sf probe 0; " \
665 "tftp $loadaddr $mbr; " \
666 "sf erase $mbr_offset +$filesize; " \
667 "sf write $loadaddr $mbr_offset $filesize\0" \
668 "flashuboot=tftp $loadaddr $ubootfile; " \
669 "protect off $nor_ubootaddr0 +$filesize; " \
670 "erase $nor_ubootaddr0 +$filesize; " \
671 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
672 "protect on $nor_ubootaddr0 +$filesize; " \
673 "protect off $nor_ubootaddr1 +$filesize; " \
674 "erase $nor_ubootaddr1 +$filesize; " \
675 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
676 "protect on $nor_ubootaddr1 +$filesize\0 " \
677 "format0=protect off $part0base +$part0size; " \
678 "erase $part0base +$part0size\0" \
679 "format1=protect off $part1base +$part1size; " \
680 "erase $part1base +$part1size\0" \
681 "format2=protect off $part2base +$part2size; " \
682 "erase $part2base +$part2size\0" \
683 "format3=protect off $part3base +$part3size; " \
684 "erase $part3base +$part3size\0" \
685 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
686 "kerneladdr=0x01100000\0" \
687 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
688 "kernelfile=uImage\0" \
689 "loadaddr=0x01000000\0" \
690 "mbr=uCP1020.mbr\0" \
691 "mbr_offset=0x00000000\0" \
693 "nor_ubootaddr0=0xEC000000\0" \
694 "nor_ubootaddr1=0xEFF80000\0" \
695 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
696 "run norkernelload; " \
697 "bootm $kerneladdr - $dtbaddr\0" \
698 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
699 "setenv cramfsaddr $part0base; " \
700 "cramfsload $dtbaddr $dtbfile; " \
701 "cramfsload $kerneladdr $kernelfile\0" \
702 "part0base=0xEC100000\0" \
703 "part0size=0x00700000\0" \
704 "part1base=0xEC800000\0" \
705 "part1size=0x02000000\0" \
706 "part2base=0xEE800000\0" \
707 "part2size=0x00800000\0" \
708 "part3base=0xEF000000\0" \
709 "part3size=0x00F80000\0" \
710 "partENVbase=0xEC080000\0" \
711 "partENVsize=0x00080000\0" \
712 "program0=tftp part0-000000.bin; " \
713 "protect off $part0base +$filesize; " \
714 "erase $part0base +$filesize; " \
715 "cp.b $loadaddr $part0base $filesize; " \
716 "echo Verifying...; " \
717 "cmp.b $loadaddr $part0base $filesize\0" \
718 "program1=tftp part1-000000.bin; " \
719 "protect off $part1base +$filesize; " \
720 "erase $part1base +$filesize; " \
721 "cp.b $loadaddr $part1base $filesize; " \
722 "echo Verifying...; " \
723 "cmp.b $loadaddr $part1base $filesize\0" \
724 "program2=tftp part2-000000.bin; " \
725 "protect off $part2base +$filesize; " \
726 "erase $part2base +$filesize; " \
727 "cp.b $loadaddr $part2base $filesize; " \
728 "echo Verifying...; " \
729 "cmp.b $loadaddr $part2base $filesize\0" \
730 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
731 " console=$consoledev,$baudrate $othbootargs; " \
732 "tftp $rootfsaddr $rootfsfile; " \
733 "tftp $loadaddr $kernelfile; " \
734 "tftp $dtbaddr $dtbfile; " \
735 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
736 "ramdisk_size=120000\0" \
737 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
738 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
739 "mw.l 0xffe0f008 0x00400000\0" \
740 "rootfsaddr=0x02F00000\0" \
741 "rootfsfile=rootfs.ext2.gz.uboot\0" \
742 "rootpath=/opt/nfsroot\0" \
743 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
744 "sf probe 0; sf erase 0 +$filesize; " \
745 "sf write $loadaddr 0 $filesize\0" \
746 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
747 "protect off 0xeC000000 +$filesize; " \
748 "erase 0xEC000000 +$filesize; " \
749 "cp.b $loadaddr 0xEC000000 $filesize; " \
750 "cmp.b $loadaddr 0xEC000000 $filesize; " \
751 "protect on 0xeC000000 +$filesize\0" \
752 "tftpflash=tftpboot $loadaddr $uboot; " \
753 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
754 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
755 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
756 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
757 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
758 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
759 "ubootfile=u-boot.bin\0" \
760 "upgrade=run flashuboot\0" \
761 "usb_phy_type=ulpi\0 " \
763 "setenv bootargs root=/dev/nfs rw " \
764 "nfsroot=$serverip:$rootpath " \
765 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
766 "console=$consoledev,$baudrate $othbootargs;" \
767 "tftp $loadaddr $bootfile;" \
768 "tftp $fdtaddr $fdtfile;" \
769 "bootm $loadaddr - $fdtaddr\0" \
771 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
772 "console=$consoledev,$baudrate $othbootargs;" \
774 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
775 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
776 "bootm $loadaddr - $fdtaddr\0" \
778 "setenv bootargs root=/dev/ram rw " \
779 "console=$consoledev,$baudrate $othbootargs " \
780 "ramdisk_size=$ramdisk_size;" \
782 "fatload usb 0:2 $loadaddr $bootfile;" \
783 "fatload usb 0:2 $fdtaddr $fdtfile;" \
784 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
785 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
787 "setenv bootargs root=/dev/ram rw " \
788 "console=$consoledev,$baudrate $othbootargs " \
789 "ramdisk_size=$ramdisk_size;" \
791 "ext2load usb 0:4 $loadaddr $bootfile;" \
792 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
793 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
794 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
796 "setenv bootargs root=/dev/$jffs2nor rw " \
797 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
798 "bootm $norbootaddr - $norfdtaddr\0 " \
800 "setenv bootargs root=/dev/ram rw " \
801 "console=$consoledev,$baudrate $othbootargs " \
802 "ramdisk_size=$ramdisk_size;" \
803 "tftp $ramdiskaddr $ramdiskfile;" \
804 "tftp $loadaddr $bootfile;" \
805 "tftp $fdtaddr $fdtfile;" \
806 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
811 #endif /* __CONFIG_H */