include/configs/kmvect1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <[email protected]>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <[email protected]>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <[email protected]>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, [email protected].
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 /* This needs to be set prior to including km83xx-common.h */
  24
  25 #define CONFIG_HOSTNAME         "kmvect1"
  26 #define CONFIG_KM_BOARD_NAME   "kmvect1"
  27 /* at end of uboot partition, before env */
  28 #define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
  29
  30 /*
  31  * High Level Configuration Options
  32  */
  33 #define CONFIG_E300             1       /* E300 family */
  34 #define CONFIG_QE               1       /* Has QE */
  35
  36 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  37
  38 /* include common defines/options for all 83xx Keymile boards */
  39 #include "km83xx-common.h"
  40
  41 /* QE microcode/firmware address */
  42 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  43 /* between the u-boot partition and env */
  44 #ifndef CONFIG_SYS_QE_FW_ADDR
  45 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
  46 #endif
  47
  48 /*
  49  * System IO Config
  50  */
  51 /* 0x14000180 SICR_1 */
  52 #define CONFIG_SYS_SICRL (0                     \
  53                 | SICR_1_UART1_UART1RTS         \
  54                 | SICR_1_I2C_CKSTOP             \
  55                 | SICR_1_IRQ_A_IRQ              \
  56                 | SICR_1_IRQ_B_IRQ              \
  57                 | SICR_1_GPIO_A_GPIO            \
  58                 | SICR_1_GPIO_B_GPIO            \
  59                 | SICR_1_GPIO_C_GPIO            \
  60                 | SICR_1_GPIO_D_GPIO            \
  61                 | SICR_1_GPIO_E_GPIO            \
  62                 | SICR_1_GPIO_F_GPIO            \
  63                 | SICR_1_USB_A_UART2S           \
  64                 | SICR_1_USB_B_UART2RTS         \
  65                 | SICR_1_FEC1_FEC1              \
  66                 | SICR_1_FEC2_FEC2              \
  67                 )
  68
  69 /* 0x00080400 SICR_2 */
  70 #define CONFIG_SYS_SICRH (0                     \
  71                 | SICR_2_FEC3_FEC3              \
  72                 | SICR_2_HDLC1_A_HDLC1          \
  73                 | SICR_2_ELBC_A_LA              \
  74                 | SICR_2_ELBC_B_LCLK            \
  75                 | SICR_2_HDLC2_A_HDLC2          \
  76                 | SICR_2_USB_D_GPIO             \
  77                 | SICR_2_PCI_PCI                \
  78                 | SICR_2_HDLC1_B_HDLC1          \
  79                 | SICR_2_HDLC1_C_HDLC1          \
  80                 | SICR_2_HDLC2_B_GPIO           \
  81                 | SICR_2_HDLC2_C_HDLC2          \
  82                 | SICR_2_QUIESCE_B              \
  83                 )
  84
  85 /* GPR_1 */
  86 #define CONFIG_SYS_GPR1  0x50008060
  87
  88 #define CONFIG_SYS_GP1DIR 0x00000000
  89 #define CONFIG_SYS_GP1ODR 0x00000000
  90 #define CONFIG_SYS_GP2DIR 0xFF000000
  91 #define CONFIG_SYS_GP2ODR 0x00000000
  92
  93 /*
  94  * Hardware Reset Configuration Word
  95  */
  96 #define CONFIG_SYS_HRCW_LOW (\
  97         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
  98         HRCWL_DDR_TO_SCB_CLK_2X1 | \
  99         HRCWL_CSB_TO_CLKIN_2X1 | \
 100         HRCWL_CORE_TO_CSB_2X1 | \
 101         HRCWL_CE_PLL_VCO_DIV_2 | \
 102         HRCWL_CE_TO_PLL_1X3)
 103
 104 #define CONFIG_SYS_HRCW_HIGH (\
 105         HRCWH_PCI_AGENT | \
 106         HRCWH_PCI_ARBITER_DISABLE | \
 107         HRCWH_CORE_ENABLE | \
 108         HRCWH_FROM_0X00000100 | \
 109         HRCWH_BOOTSEQ_DISABLE | \
 110         HRCWH_SW_WATCHDOG_DISABLE | \
 111         HRCWH_ROM_LOC_LOCAL_16BIT | \
 112         HRCWH_BIG_ENDIAN | \
 113         HRCWH_LALE_NORMAL)
 114
 115 #define CONFIG_SYS_DDRCDR (\
 116         DDRCDR_EN | \
 117         DDRCDR_PZ_MAXZ | \
 118         DDRCDR_NZ_MAXZ | \
 119         DDRCDR_M_ODR)
 120
 121 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 122 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 123                                          SDRAM_CFG_32_BE | \
 124                                          SDRAM_CFG_SREN | \
 125                                          SDRAM_CFG_HSE)
 126
 127 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 128 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 129 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 130                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 131
 132 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 133                                          CSCONFIG_ODT_RD_NEVER | \
 134                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 135                                          CSCONFIG_ROW_BIT_13 | \
 136                                          CSCONFIG_COL_BIT_10)
 137
 138 #define CONFIG_SYS_DDR_MODE     0x47860242
 139 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 140
 141 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 142                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 143                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 144                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 145                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 146                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 147                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 148                                  (0 << TIMING_CFG0_RWT_SHIFT))
 149
 150 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 151                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 152                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 153                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 154                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 155                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 156                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 157                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 158
 159 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 160                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 161                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 162                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 163                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 164                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 165                                  (5 << TIMING_CFG2_CPO_SHIFT))
 166
 167 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 168
 169 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 170 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 171
 172 /* EEprom support */
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 174
 175 /*
 176  * Local Bus Configuration & Clock Setup
 177  */
 178 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 179 #define CONFIG_SYS_LCRR_EADC    0x00010000
 180 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 181
 182 #define CONFIG_SYS_LBC_LBCR     0x00000000
 183
 184 /*
 185  * MMU Setup
 186  */
 187 #define CONFIG_SYS_IBAT7L       (0)
 188 #define CONFIG_SYS_IBAT7U       (0)
 189 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 190 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 191
 192 #define CONFIG_SYS_APP1_BASE            0xA0000000
 193 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 194 #define CONFIG_SYS_APP2_BASE            0xB0000000
 195 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 196
 197 /* EEprom support */
 198 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 199
 200 /*
 201  * Init Local Bus Memory Controller:
 202  *
 203  * Bank Bus     Machine PortSz  Size  Device
 204  * ---- ---     ------- ------  -----  ------
 205  *  2   Local   UPMA    16 bit  256MB APP1
 206  *  3   Local   GPCM    16 bit  256MB APP2
 207  *
 208  */
 209
 210 /*
 211  * APP1 on the local bus CS2
 212  */
 213 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
 214 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 215
 216 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 217                                  BR_PS_16 | \
 218                                  BR_MS_UPMA | \
 219                                  BR_V)
 220 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
 221
 222 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 223                                  BR_PS_16 | \
 224                                  BR_V)
 225
 226 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 227                                  OR_GPCM_CSNT | \
 228                                  OR_GPCM_ACS_DIV4 | \
 229                                  OR_GPCM_SCY_3 | \
 230                                  OR_GPCM_TRLX_SET)
 231
 232 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 233                          0x0000c000 | \
 234                          MxMR_WLFx_2X)
 235
 236 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 237 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 238
 239 /*
 240  * MMU Setup
 241  */
 242 /* APP1:  icache cacheable, but dcache-inhibit and guarded */
 243 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 244                                  BATL_MEMCOHERENCE)
 245 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
 246                                  BATU_VS | BATU_VP)
 247 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 248                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 249 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 250 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 251                                  BATL_MEMCOHERENCE)
 252 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
 253                                  BATU_VS | BATU_VP)
 254 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 255                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 256 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 257
 258 /*
 259  * QE UEC ethernet configuration
 260  */
 261 #define CONFIG_MV88E6352_SWITCH
 262 #define CONFIG_KM_MVEXTSW_ADDR          0x10
 263
 264 /* ethernet port connected to simple switch 88e6122 (UEC0) */
 265 #define CONFIG_UEC_ETH1
 266 #define CONFIG_SYS_UEC1_UCC_NUM         0       /* UCC1 */
 267 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 268 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 269
 270 #define CONFIG_FIXED_PHY                0xFFFFFFFF
 271 #define CONFIG_SYS_FIXED_PHY_ADDR       0x1E    /* unused address */
 272 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 273                 {devnum, speed, duplex}
 274 #define CONFIG_SYS_FIXED_PHY_PORTS \
 275                 CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
 276
 277 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 278 #define CONFIG_SYS_UEC1_PHY_ADDR        CONFIG_SYS_FIXED_PHY_ADDR
 279 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 280 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 281
 282 /* ethernet port connected to piggy (UEC2) */
 283 #define CONFIG_HAS_ETH1
 284 #define CONFIG_UEC_ETH2
 285 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 286 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 287 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 288 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 289 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 290 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 291 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 292
 293 #endif /* __CONFIG_H */