include/configs/ls1046ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor
   4  */
   5
   6 #ifndef __LS1046ARDB_H__
   7 #define __LS1046ARDB_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #define CONFIG_SYS_CLK_FREQ             100000000
  12 #define CONFIG_DDR_CLK_FREQ             100000000
  13
  14 #define CONFIG_LAYERSCAPE_NS_ACCESS
  15 #define CONFIG_MISC_INIT_R
  16
  17 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  18 /* Physical Memory Map */
  19 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  20
  21 #define CONFIG_DDR_SPD
  22 #define SPD_EEPROM_ADDRESS              0x51
  23 #define CONFIG_SYS_SPD_BUS_NUM          0
  24
  25 #define CONFIG_DDR_ECC
  26 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  27 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  28 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  29 #ifndef CONFIG_SPL
  30 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  31 #endif
  32
  33 #ifdef CONFIG_SD_BOOT
  34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
  35 #ifdef CONFIG_EMMC_BOOT
  36 #define CONFIG_SYS_FSL_PBL_RCW \
  37         board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
  38 #else
  39 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
  40 #endif
  41 #elif defined(CONFIG_QSPI_BOOT)
  42 #define CONFIG_SYS_FSL_PBL_RCW \
  43         board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
  44 #define CONFIG_SYS_FSL_PBL_PBI \
  45         board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
  46 #define CONFIG_SYS_UBOOT_BASE           0x40100000
  47 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  48 #endif
  49
  50 #ifndef SPL_NO_IFC
  51 /* IFC */
  52 #define CONFIG_FSL_IFC
  53 /*
  54  * NAND Flash Definitions
  55  */
  56 #define CONFIG_NAND_FSL_IFC
  57 #endif
  58
  59 #define CONFIG_SYS_NAND_BASE            0x7e800000
  60 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  61
  62 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  63 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  64                                 | CSPR_PORT_SIZE_8      \
  65                                 | CSPR_MSEL_NAND        \
  66                                 | CSPR_V)
  67 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  68 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  69                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  70                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
  71                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  72                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  73                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  74                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  75
  76 #define CONFIG_SYS_NAND_ONFI_DETECTION
  77
  78 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  79                                         FTIM0_NAND_TWP(0x18)   | \
  80                                         FTIM0_NAND_TWCHT(0x7) | \
  81                                         FTIM0_NAND_TWH(0xa))
  82 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  83                                         FTIM1_NAND_TWBE(0x39)  | \
  84                                         FTIM1_NAND_TRR(0xe)   | \
  85                                         FTIM1_NAND_TRP(0x18))
  86 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  87                                         FTIM2_NAND_TREH(0xa) | \
  88                                         FTIM2_NAND_TWHRE(0x1e))
  89 #define CONFIG_SYS_NAND_FTIM3           0x0
  90
  91 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  92 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  93 #define CONFIG_MTD_NAND_VERIFY_WRITE
  94
  95 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
  96
  97 /*
  98  * CPLD
  99  */
 100 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 101 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 102
 103 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 104 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 105                                         CSPR_PORT_SIZE_8 | \
 106                                         CSPR_MSEL_GPCM | \
 107                                         CSPR_V)
 108 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 109 #define CONFIG_SYS_CPLD_CSOR            CSOR_NOR_ADM_SHIFT(16)
 110
 111 /* CPLD Timing parameters for IFC GPCM */
 112 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
 113                                         FTIM0_GPCM_TEADC(0x0e) | \
 114                                         FTIM0_GPCM_TEAHC(0x0e))
 115 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 116                                         FTIM1_GPCM_TRAD(0x3f))
 117 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 118                                         FTIM2_GPCM_TCH(0xf) | \
 119                                         FTIM2_GPCM_TWP(0x3E))
 120 #define CONFIG_SYS_CPLD_FTIM3           0x0
 121
 122 /* IFC Timing Params */
 123 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 124 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 125 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 126 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 127 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 128 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 129 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 130 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 131
 132 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 133 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 134 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 135 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 136 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 137 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 138 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 139 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 140
 141 /* EEPROM */
 142 #define CONFIG_ID_EEPROM
 143 #define CONFIG_SYS_I2C_EEPROM_NXID
 144 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 145 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 146 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 147 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 148 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 149 #define I2C_RETIMER_ADDR                        0x18
 150
 151 /* PMIC */
 152 #define CONFIG_POWER
 153 #ifdef CONFIG_POWER
 154 #define CONFIG_POWER_I2C
 155 #endif
 156
 157 /*
 158  * Environment
 159  */
 160 #ifndef SPL_NO_ENV
 161 #define CONFIG_ENV_OVERWRITE
 162 #endif
 163
 164 #if defined(CONFIG_SD_BOOT)
 165 #define CONFIG_SYS_MMC_ENV_DEV          0
 166 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
 167 #define CONFIG_ENV_SIZE                 0x2000
 168 #else
 169 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 170 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
 171 #define CONFIG_ENV_SECT_SIZE            0x40000         /* 256KB */
 172 #endif
 173
 174 #define AQR105_IRQ_MASK                 0x80000000
 175 /* FMan */
 176 #ifndef SPL_NO_FMAN
 177
 178 #ifdef CONFIG_NET
 179 #define CONFIG_PHY_REALTEK
 180 #endif
 181
 182 #ifdef CONFIG_SYS_DPAA_FMAN
 183 #define CONFIG_FMAN_ENET
 184 #define CONFIG_PHY_AQUANTIA
 185 #define CONFIG_PHYLIB_10G
 186 #define RGMII_PHY1_ADDR                 0x1
 187 #define RGMII_PHY2_ADDR                 0x2
 188
 189 #define SGMII_PHY1_ADDR                 0x3
 190 #define SGMII_PHY2_ADDR                 0x4
 191
 192 #define FM1_10GEC1_PHY_ADDR             0x0
 193
 194 #define FDT_SEQ_MACADDR_FROM_ENV
 195
 196 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 197 #endif
 198
 199 #endif
 200
 201 /* QSPI device */
 202 #ifndef SPL_NO_QSPI
 203 #ifdef CONFIG_FSL_QSPI
 204 #define CONFIG_SPI_FLASH_SPANSION
 205 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
 206 #define FSL_QSPI_FLASH_NUM              2
 207 #endif
 208 #endif
 209
 210 #ifndef SPL_NO_MISC
 211 #undef CONFIG_BOOTCOMMAND
 212 #if defined(CONFIG_QSPI_BOOT)
 213 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "     \
 214                            "env exists secureboot && esbc_halt;;"
 215 #elif defined(CONFIG_SD_BOOT)
 216 #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "        \
 217                            "env exists secureboot && esbc_halt;"
 218 #endif
 219 #endif
 220
 221 #include <asm/fsl_secure_boot.h>
 222
 223 #endif /* __LS1046ARDB_H__ */