arch/arm/dts/cn9131-db-B.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018-2021 Marvell International Ltd.
   4  */
   5
   6 #include "cn9130-db-B.dts"
   7 #include "cn9131-db.dtsi"
   8
   9 / {
  10         model = "Marvell CN9131 development board (CP NAND) setup(B)";
  11         compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
  12                      "marvell,armada-ap806";
  13 };
  14
  15 &cp1_comphy {
  16         /* Serdes Configuration:
  17          *      Lane 0: PCIe0 (x2)
  18          *      Lane 1: PCIe0 (x2)
  19          *      Lane 2: SFI (port 0)
  20          *      Lane 3: USB1
  21          *      Lane 4: SGMII (port 1)
  22          *      Lane 5: SATA1
  23          */
  24         phy0 {
  25                 phy-type = <COMPHY_TYPE_PEX0>;
  26         };
  27         phy1 {
  28                 phy-type = <COMPHY_TYPE_PEX0>;
  29         };
  30         phy2 {
  31                 phy-type = <COMPHY_TYPE_SFI0>;
  32                 phy-speed = <COMPHY_SPEED_10_3125G>;
  33         };
  34         phy3 {
  35                 phy-type = <COMPHY_TYPE_USB3_HOST1>;
  36         };
  37         phy4 {
  38                 phy-type = <COMPHY_TYPE_SGMII1>;
  39                 phy-speed = <COMPHY_SPEED_1_25G>;
  40         };
  41         phy5 {
  42                 phy-type = <COMPHY_TYPE_SATA1>;
  43         };
  44 };
  45
  46 &cp1_ethernet {
  47         status = "okay";
  48 };
  49
  50 /* 3310 RJ45 CON55 */
  51 &cp1_eth0 {
  52         status = "okay";
  53         phy-mode = "sfi"; /* lane-2 */
  54         phy = <&sfi_phy8>; /* required by 3310 fw download */
  55 };
  56
  57 /* CON50 */
  58 &cp1_eth1 {
  59         status = "okay";
  60         phy-mode = "sgmii"; /* lane-4 */
  61         marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>;
  62 };
  63
  64 &cp1_xmdio {
  65         status = "okay";
  66         sfi_phy8: ethernet-phy@8 {
  67                 reg = <8>;
  68         };
  69 };