cpu/bf561/cache.S

   1 #define ASSEMBLY
   2 #include <asm/linkage.h>
   3 #include <config.h>
   4 #include <asm/blackfin.h>
   5
   6 .text
   7 .align 2
   8 ENTRY(_blackfin_icache_flush_range)
   9         R2 = -32;
  10         R2 = R0 & R2;
  11         P0 = R2;
  12         P1 = R1;
  13         CSYNC;
  14         1:
  15         IFLUSH[P0++];
  16         CC = P0 < P1(iu);
  17         IF CC JUMP 1b(bp);
  18         IFLUSH[P0];
  19         SSYNC;
  20         RTS;
  21
  22 ENTRY(_blackfin_dcache_flush_range)
  23         R2 = -32;
  24         R2 = R0 & R2;
  25         P0 = R2;
  26         P1 = R1;
  27         CSYNC;
  28 1:
  29         FLUSH[P0++];
  30         CC = P0 < P1(iu);
  31         IF CC JUMP 1b(bp);
  32         FLUSH[P0];
  33         SSYNC;
  34         RTS;
  35
  36 ENTRY(_icache_invalidate)
  37 ENTRY(_invalidate_entire_icache)
  38         [--SP] = (R7:5);
  39
  40         P0.L = (IMEM_CONTROL & 0xFFFF);
  41         P0.H = (IMEM_CONTROL >> 16);
  42         R7 =[P0];
  43
  44         /*
  45          * Clear the IMC bit , All valid bits in the instruction
  46          * cache are set to the invalid state
  47          */
  48         BITCLR(R7, IMC_P);
  49         CLI R6;
  50         /* SSYNC required before invalidating cache. */
  51         SSYNC;
  52         .align 8;
  53         [P0] = R7;
  54         SSYNC;
  55         STI R6;
  56
  57         /* Configures the instruction cache agian */
  58         R6 = (IMC | ENICPLB);
  59         R7 = R7 | R6;
  60
  61         CLI R6;
  62         SSYNC;
  63         .align 8;
  64         [P0] = R7;
  65         SSYNC;
  66         STI R6;
  67
  68         (R7:5) =[SP++];
  69         RTS;
  70
  71 /*
  72  * Invalidate the Entire Data cache by
  73  * clearing DMC[1:0] bits
  74  */
  75 ENTRY(_invalidate_entire_dcache)
  76 ENTRY(_dcache_invalidate)
  77         [--SP] = (R7:6);
  78
  79         P0.L = (DMEM_CONTROL & 0xFFFF);
  80         P0.H = (DMEM_CONTROL >> 16);
  81         R7 =[P0];
  82
  83         /*
  84          * Clear the DMC[1:0] bits, All valid bits in the data
  85          * cache are set to the invalid state
  86          */
  87         BITCLR(R7, DMC0_P);
  88         BITCLR(R7, DMC1_P);
  89         CLI R6;
  90         SSYNC;
  91         .align 8;
  92         [P0] = R7;
  93         SSYNC;
  94         STI R6;
  95         /* Configures the data cache again */
  96
  97         R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
  98         R7 = R7 | R6;
  99
 100         CLI R6;
 101         SSYNC;
 102         .align 8;
 103         [P0] = R7;
 104         SSYNC;
 105         STI R6;
 106
 107         (R7:6) =[SP++];
 108         RTS;
 109
 110 ENTRY(_blackfin_dcache_invalidate_range)
 111         R2 = -32;
 112         R2 = R0 & R2;
 113         P0 = R2;
 114         P1 = R1;
 115         CSYNC;
 116 1:
 117         FLUSHINV[P0++];
 118         CC = P0 < P1(iu);
 119         IF CC JUMP 1b(bp);
 120
 121         /*
 122          * If the data crosses a cache line, then we'll be pointing to
 123          * the last cache line, but won't have flushed/invalidated it yet, so do
 124          * one more.
 125          */
 126         FLUSHINV[P0];
 127         SSYNC;
 128         RTS;