arch/arm/dts/rk3328.dtsi

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/clock/rk3328-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12
  13 / {
  14         compatible = "rockchip,rk3328";
  15
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 mmc0 = &emmc;
  29                 mmc1 = &sdmmc;
  30                 mmc2 = &sdmmc_ext;
  31         };
  32
  33         cpus {
  34                 #address-cells = <2>;
  35                 #size-cells = <0>;
  36
  37                 cpu0: cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         reg = <0x0 0x0>;
  41                         enable-method = "psci";
  42 //                      clocks = <&cru ARMCLK>;
  43                         operating-points-v2 = <&cpu0_opp_table>;
  44                 };
  45                 cpu1: cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a53", "arm,armv8";
  48                         reg = <0x0 0x1>;
  49                         enable-method = "psci";
  50                 };
  51                 cpu2: cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0x0 0x2>;
  55                         enable-method = "psci";
  56                 };
  57                 cpu3: cpu@3 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a53", "arm,armv8";
  60                         reg = <0x0 0x3>;
  61                         enable-method = "psci";
  62                 };
  63         };
  64
  65         cpu0_opp_table: opp_table0 {
  66                 compatible = "operating-points-v2";
  67                 opp-shared;
  68
  69                 opp@408000000 {
  70                         opp-hz = /bits/ 64 <408000000>;
  71                         opp-microvolt = <950000>;
  72                         clock-latency-ns = <40000>;
  73                         opp-suspend;
  74                 };
  75                 opp@600000000 {
  76                         opp-hz = /bits/ 64 <600000000>;
  77                         opp-microvolt = <950000>;
  78                         clock-latency-ns = <40000>;
  79                 };
  80                 opp@816000000 {
  81                         opp-hz = /bits/ 64 <816000000>;
  82                         opp-microvolt = <1000000>;
  83                         clock-latency-ns = <40000>;
  84                 };
  85                 opp@1008000000 {
  86                         opp-hz = /bits/ 64 <1008000000>;
  87                         opp-microvolt = <1100000>;
  88                         clock-latency-ns = <40000>;
  89                 };
  90                 opp@1200000000 {
  91                         opp-hz = /bits/ 64 <1200000000>;
  92                         opp-microvolt = <1225000>;
  93                         clock-latency-ns = <40000>;
  94                 };
  95                 opp@1296000000 {
  96                         opp-hz = /bits/ 64 <1296000000>;
  97                         opp-microvolt = <1300000>;
  98                         clock-latency-ns = <40000>;
  99                 };
 100         };
 101
 102         arm-pmu {
 103                 compatible = "arm,cortex-a53-pmu";
 104                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 107                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 108                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 109         };
 110
 111         psci {
 112                 compatible = "arm,psci-1.0";
 113                 method = "smc";
 114         };
 115
 116         timer {
 117                 compatible = "arm,armv8-timer";
 118                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 119                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 120                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 121                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 122         };
 123
 124         xin24m: xin24m {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <24000000>;
 128                 clock-output-names = "xin24m";
 129         };
 130
 131         i2s0: i2s@ff000000 {
 132                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 133                 reg = <0x0 0xff000000 0x0 0x1000>;
 134                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 135                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 136                 clock-names = "i2s_clk", "i2s_hclk";
 137                 dmas = <&dmac 11>, <&dmac 12>;
 138                 #dma-cells = <2>;
 139                 dma-names = "tx", "rx";
 140                 status = "disabled";
 141         };
 142
 143         i2s1: i2s@ff010000 {
 144                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 145                 reg = <0x0 0xff010000 0x0 0x1000>;
 146                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 147                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 148                 clock-names = "i2s_clk", "i2s_hclk";
 149                 dmas = <&dmac 14>, <&dmac 15>;
 150                 #dma-cells = <2>;
 151                 dma-names = "tx", "rx";
 152                 status = "disabled";
 153         };
 154
 155         i2s2: i2s@ff020000 {
 156                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 157                 reg = <0x0 0xff020000 0x0 0x1000>;
 158                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 159                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 160                 clock-names = "i2s_clk", "i2s_hclk";
 161                 dmas = <&dmac 0>, <&dmac 1>;
 162                 #dma-cells = <2>;
 163                 dma-names = "tx", "rx";
 164                 pinctrl-names = "default", "sleep";
 165                 pinctrl-0 = <&i2s2m0_mclk
 166                              &i2s2m0_sclk
 167                              &i2s2m0_lrcktx
 168                              &i2s2m0_lrckrx
 169                              &i2s2m0_sdo
 170                              &i2s2m0_sdi>;
 171                 pinctrl-1 = <&i2s2m0_sleep>;
 172                 status = "disabled";
 173         };
 174
 175         spdif: spdif@ff030000 {
 176                 compatible = "rockchip,rk3328-spdif";
 177                 reg = <0x0 0xff030000 0x0 0x1000>;
 178                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 180                 clock-names = "mclk", "hclk";
 181                 dmas = <&dmac 10>;
 182                 #dma-cells = <1>;
 183                 dma-names = "tx";
 184                 pinctrl-names = "default";
 185                 pinctrl-0 = <&spdifm2_tx>;
 186                 status = "disabled";
 187         };
 188
 189         grf: syscon@ff100000 {
 190                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 191                 reg = <0x0 0xff100000 0x0 0x1000>;
 192                 #address-cells = <1>;
 193                 #size-cells = <1>;
 194
 195                 io_domains: io-domains {
 196                         compatible = "rockchip,rk3328-io-voltage-domain";
 197                         status = "disabled";
 198                 };
 199         };
 200
 201         uart0: serial@ff110000 {
 202                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 203                 reg = <0x0 0xff110000 0x0 0x100>;
 204                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 205                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 206                 clock-names = "baudclk", "apb_pclk";
 207                 reg-shift = <2>;
 208                 reg-io-width = <4>;
 209                 dmas = <&dmac 2>, <&dmac 3>;
 210                 #dma-cells = <2>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 213                 status = "disabled";
 214         };
 215
 216         uart1: serial@ff120000 {
 217                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 218                 reg = <0x0 0xff120000 0x0 0x100>;
 219                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 221                 clock-names = "sclk_uart", "pclk_uart";
 222                 reg-shift = <2>;
 223                 reg-io-width = <4>;
 224                 dmas = <&dmac 4>, <&dmac 5>;
 225                 #dma-cells = <2>;
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 228                 status = "disabled";
 229         };
 230
 231         uart2: serial@ff130000 {
 232                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 233                 reg = <0x0 0xff130000 0x0 0x100>;
 234                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 235                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 236                 clock-names = "baudclk", "apb_pclk";
 237                 clock-frequency = <24000000>;
 238                 reg-shift = <2>;
 239                 reg-io-width = <4>;
 240                 dmas = <&dmac 6>, <&dmac 7>;
 241                 #dma-cells = <2>;
 242                 pinctrl-names = "default";
 243                 pinctrl-0 = <&uart2m1_xfer>;
 244                 status = "disabled";
 245         };
 246
 247         pmu: power-management@ff140000 {
 248                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 249                 reg = <0x0 0xff140000 0x0 0x1000>;
 250         };
 251
 252         i2c0: i2c@ff150000 {
 253                 compatible = "rockchip,rk3328-i2c";
 254                 reg = <0x0 0xff150000 0x0 0x1000>;
 255                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 259                 clock-names = "i2c", "pclk";
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&i2c0_xfer>;
 262                 status = "disabled";
 263         };
 264
 265         i2c1: i2c@ff160000 {
 266                 compatible = "rockchip,rk3328-i2c";
 267                 reg = <0x0 0xff160000 0x0 0x1000>;
 268                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 272                 clock-names = "i2c", "pclk";
 273                 pinctrl-names = "default";
 274                 pinctrl-0 = <&i2c1_xfer>;
 275                 status = "disabled";
 276         };
 277
 278         i2c2: i2c@ff170000 {
 279                 compatible = "rockchip,rk3328-i2c";
 280                 reg = <0x0 0xff170000 0x0 0x1000>;
 281                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 282                 #address-cells = <1>;
 283                 #size-cells = <0>;
 284                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 285                 clock-names = "i2c", "pclk";
 286                 pinctrl-names = "default";
 287                 pinctrl-0 = <&i2c2_xfer>;
 288                 status = "disabled";
 289         };
 290
 291         i2c3: i2c@ff180000 {
 292                 compatible = "rockchip,rk3328-i2c";
 293                 reg = <0x0 0xff180000 0x0 0x1000>;
 294                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 298                 clock-names = "i2c", "pclk";
 299                 pinctrl-names = "default";
 300                 pinctrl-0 = <&i2c3_xfer>;
 301                 status = "disabled";
 302         };
 303
 304         spi0: spi@ff190000 {
 305                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 306                 reg = <0x0 0xff190000 0x0 0x1000>;
 307                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 311                 clock-names = "spiclk", "apb_pclk";
 312                 dmas = <&dmac 8>, <&dmac 9>;
 313                 #dma-cells = <2>;
 314                 dma-names = "tx", "rx";
 315                 pinctrl-names = "default";
 316                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 317                 status = "disabled";
 318         };
 319
 320         wdt: watchdog@ff1a0000 {
 321                 compatible = "snps,dw-wdt";
 322                 reg = <0x0 0xff1a0000 0x0 0x100>;
 323                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 324                 status = "disabled";
 325         };
 326
 327         amba {
 328                 compatible = "simple-bus";
 329                 #address-cells = <2>;
 330                 #size-cells = <2>;
 331                 ranges;
 332
 333                 dmac: dmac@ff1f0000 {
 334                         compatible = "arm,pl330", "arm,primecell";
 335                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 336                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 337                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 338                         clocks = <&cru ACLK_DMAC>;
 339                         clock-names = "apb_pclk";
 340                         #dma-cells = <1>;
 341                 };
 342         };
 343
 344         saradc: saradc@ff280000 {
 345                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 346                 reg = <0x0 0xff280000 0x0 0x100>;
 347                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 348                 #io-channel-cells = <1>;
 349                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 350                 clock-names = "saradc", "apb_pclk";
 351                 resets = <&cru SRST_SARADC_P>;
 352                 reset-names = "saradc-apb";
 353                 status = "disabled";
 354         };
 355
 356         cru: clock-controller@ff440000 {
 357                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 358                 reg = <0x0 0xff440000 0x0 0x1000>;
 359                 rockchip,grf = <&grf>;
 360                 #clock-cells = <1>;
 361                 #reset-cells = <1>;
 362                 assigned-clocks =
 363                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 364                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 365                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 366                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 367                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 368                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 369                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 370                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 371                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 372                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 373                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 374                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 375                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 376                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 377                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 378                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 379                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 380                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 381                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 382                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 383                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 384                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 385                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 386                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 387                 assigned-clock-parents =
 388                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 389                         <&cru PLL_GPLL>, <&xin24m>,
 390                         <&xin24m>, <&xin24m>;
 391                 assigned-clock-rates =
 392                         <0>, <61440000>,
 393                         <0>, <24000000>,
 394                         <24000000>, <24000000>,
 395                         <15000000>, <15000000>,
 396                         <100000000>, <100000000>,
 397                         <100000000>, <100000000>,
 398                         <50000000>, <100000000>,
 399                         <100000000>, <100000000>,
 400                         <50000000>, <50000000>,
 401                         <50000000>, <50000000>,
 402                         <24000000>, <600000000>,
 403                         <491520000>, <1200000000>,
 404                         <150000000>, <75000000>,
 405                         <75000000>, <150000000>,
 406                         <75000000>, <75000000>,
 407                         <300000000>, <100000000>,
 408                         <300000000>, <200000000>,
 409                         <400000000>, <500000000>,
 410                         <200000000>, <300000000>,
 411                         <300000000>, <250000000>,
 412                         <200000000>, <100000000>,
 413                         <24000000>, <100000000>,
 414                         <150000000>, <50000000>,
 415                         <32768>, <32768>;
 416         };
 417
 418         sdmmc: rksdmmc@ff500000 {
 419                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 420                 reg = <0x0 0xff500000 0x0 0x4000>;
 421                 clock-freq-min-max = <400000 150000000>;
 422                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 423                 clock-names = "biu", "ciu";
 424                 fifo-depth = <0x100>;
 425                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 426                 status = "disabled";
 427         };
 428
 429         sdio: dwmmc@ff510000 {
 430                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 431                 reg = <0x0 0xff510000 0x0 0x4000>;
 432                 clock-freq-min-max = <400000 150000000>;
 433                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 434                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 435                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 436                 fifo-depth = <0x100>;
 437                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 438                 status = "disabled";
 439         };
 440
 441         emmc: rksdmmc@ff520000 {
 442                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 443                 reg = <0x0 0xff520000 0x0 0x4000>;
 444                 clock-freq-min-max = <400000 150000000>;
 445                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 446                 clock-names = "biu", "ciu";
 447                 fifo-depth = <0x100>;
 448                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 449                 status = "disabled";
 450         };
 451
 452         usb_host0_ehci: usb@ff5c0000 {
 453                 compatible = "generic-ehci";
 454                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 455                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 456                 status = "disabled";
 457         };
 458
 459         usb_host0_ohci: usb@ff5d0000 {
 460                 compatible = "generic-ohci";
 461                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 462                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 463                 status = "disabled";
 464         };
 465
 466         sdmmc_ext: rksdmmc@ff5f0000 {
 467                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 468                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 469                 clock-freq-min-max = <400000 150000000>;
 470                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 471                 clock-names = "biu", "ciu";
 472                 fifo-depth = <0x100>;
 473                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 474                 status = "disabled";
 475         };
 476
 477         usb_host0_xhci: usb@ff600000 {
 478                 compatible = "rockchip,rk3328-xhci";
 479                 reg = <0x0 0xff600000 0x0 0x100000>;
 480                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 481                 snps,dis-enblslpm-quirk;
 482                 snps,phyif-utmi-bits = <16>;
 483                 snps,dis-u2-freeclk-exists-quirk;
 484                 snps,dis-u2-susphy-quirk;
 485                 status = "disabled";
 486         };
 487
 488         gic: interrupt-controller@ffb70000 {
 489                 compatible = "arm,gic-400";
 490                 #interrupt-cells = <3>;
 491                 #address-cells = <0>;
 492                 interrupt-controller;
 493                 reg = <0x0 0xff811000 0 0x1000>,
 494                       <0x0 0xff812000 0 0x2000>,
 495                       <0x0 0xff814000 0 0x2000>,
 496                       <0x0 0xff816000 0 0x2000>;
 497                 interrupts = <GIC_PPI 9
 498                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 499         };
 500
 501         pinctrl: pinctrl {
 502                 compatible = "rockchip,rk3328-pinctrl";
 503                 rockchip,grf = <&grf>;
 504                 #address-cells = <2>;
 505                 #size-cells = <2>;
 506                 ranges;
 507
 508                 gpio0: gpio0@ff210000 {
 509                         compatible = "rockchip,gpio-bank";
 510                         reg = <0x0 0xff210000 0x0 0x100>;
 511                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 512                         clocks = <&cru PCLK_GPIO0>;
 513
 514                         gpio-controller;
 515                         #gpio-cells = <2>;
 516
 517                         interrupt-controller;
 518                         #interrupt-cells = <2>;
 519                 };
 520
 521                 gpio1: gpio1@ff220000 {
 522                         compatible = "rockchip,gpio-bank";
 523                         reg = <0x0 0xff220000 0x0 0x100>;
 524                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&cru PCLK_GPIO1>;
 526
 527                         gpio-controller;
 528                         #gpio-cells = <2>;
 529
 530                         interrupt-controller;
 531                         #interrupt-cells = <2>;
 532                 };
 533
 534                 gpio2: gpio2@ff230000 {
 535                         compatible = "rockchip,gpio-bank";
 536                         reg = <0x0 0xff230000 0x0 0x100>;
 537                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&cru PCLK_GPIO2>;
 539
 540                         gpio-controller;
 541                         #gpio-cells = <2>;
 542
 543                         interrupt-controller;
 544                         #interrupt-cells = <2>;
 545                 };
 546
 547                 gpio3: gpio3@ff240000 {
 548                         compatible = "rockchip,gpio-bank";
 549                         reg = <0x0 0xff240000 0x0 0x100>;
 550                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 551                         clocks = <&cru PCLK_GPIO3>;
 552
 553                         gpio-controller;
 554                         #gpio-cells = <2>;
 555
 556                         interrupt-controller;
 557                         #interrupt-cells = <2>;
 558                 };
 559
 560                 pcfg_pull_up: pcfg-pull-up {
 561                         bias-pull-up;
 562                 };
 563
 564                 pcfg_pull_down: pcfg-pull-down {
 565                         bias-pull-down;
 566                 };
 567
 568                 pcfg_pull_none: pcfg-pull-none {
 569                         bias-disable;
 570                 };
 571
 572                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 573                         bias-disable;
 574                         drive-strength = <2>;
 575                 };
 576
 577                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 578                         bias-pull-up;
 579                         drive-strength = <2>;
 580                 };
 581
 582                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 583                         bias-pull-up;
 584                         drive-strength = <4>;
 585                 };
 586
 587                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 588                         bias-disable;
 589                         drive-strength = <4>;
 590                 };
 591
 592                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 593                         bias-pull-down;
 594                         drive-strength = <4>;
 595                 };
 596
 597                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 598                         bias-disable;
 599                         drive-strength = <8>;
 600                 };
 601
 602                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 603                         bias-pull-up;
 604                         drive-strength = <8>;
 605                 };
 606
 607                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 608                         bias-disable;
 609                         drive-strength = <12>;
 610                 };
 611
 612                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 613                         bias-pull-up;
 614                         drive-strength = <12>;
 615                 };
 616
 617                 pcfg_output_high: pcfg-output-high {
 618                         output-high;
 619                 };
 620
 621                 pcfg_output_low: pcfg-output-low {
 622                         output-low;
 623                 };
 624
 625                 pcfg_input_high: pcfg-input-high {
 626                         bias-pull-up;
 627                         input-enable;
 628                 };
 629
 630                 pcfg_input: pcfg-input {
 631                         input-enable;
 632                 };
 633
 634                 i2c0 {
 635                         i2c0_xfer: i2c0-xfer {
 636                                 rockchip,pins =
 637                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 638                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 639                         };
 640                 };
 641
 642                 i2c1 {
 643                         i2c1_xfer: i2c1-xfer {
 644                                 rockchip,pins =
 645                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 646                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 647                         };
 648                 };
 649
 650                 i2c2 {
 651                         i2c2_xfer: i2c2-xfer {
 652                                 rockchip,pins =
 653                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 654                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 655                         };
 656                 };
 657
 658                 i2c3 {
 659                         i2c3_xfer: i2c3-xfer {
 660                                 rockchip,pins =
 661                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 662                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 663                         };
 664                         i2c3_gpio: i2c3-gpio {
 665                                 rockchip,pins =
 666                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 667                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 668                         };
 669                 };
 670
 671                 hdmi_i2c {
 672                         hdmii2c_xfer: hdmii2c-xfer {
 673                                 rockchip,pins =
 674                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 675                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 676                         };
 677                 };
 678
 679                 uart0 {
 680                         uart0_xfer: uart0-xfer {
 681                                 rockchip,pins =
 682                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 683                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 684                         };
 685
 686                         uart0_cts: uart0-cts {
 687                                 rockchip,pins =
 688                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 689                         };
 690
 691                         uart0_rts: uart0-rts {
 692                                 rockchip,pins =
 693                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 694                         };
 695
 696                         uart0_rts_gpio: uart0-rts-gpio {
 697                                 rockchip,pins =
 698                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 699                         };
 700                 };
 701
 702                 uart1 {
 703                         uart1_xfer: uart1-xfer {
 704                                 rockchip,pins =
 705                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 706                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 707                         };
 708
 709                         uart1_cts: uart1-cts {
 710                                 rockchip,pins =
 711                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 712                         };
 713
 714                         uart1_rts: uart1-rts {
 715                                 rockchip,pins =
 716                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 717                         };
 718
 719                         uart1_rts_gpio: uart1-rts-gpio {
 720                                 rockchip,pins =
 721                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 722                         };
 723                 };
 724
 725                 uart2-0 {
 726                         uart2m0_xfer: uart2m0-xfer {
 727                                 rockchip,pins =
 728                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 729                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 730                         };
 731                 };
 732
 733                 uart2-1 {
 734                         uart2m1_xfer: uart2m1-xfer {
 735                                 rockchip,pins =
 736                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 737                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 738                         };
 739                 };
 740
 741                 spi0-0 {
 742                         spi0m0_clk: spi0m0-clk {
 743                                 rockchip,pins =
 744                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 745                         };
 746
 747                         spi0m0_cs0: spi0m0-cs0 {
 748                                 rockchip,pins =
 749                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 750                         };
 751
 752                         spi0m0_tx: spi0m0-tx {
 753                                 rockchip,pins =
 754                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 755                         };
 756
 757                         spi0m0_rx: spi0m0-rx {
 758                                 rockchip,pins =
 759                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 760                         };
 761
 762                         spi0m0_cs1: spi0m0-cs1 {
 763                                 rockchip,pins =
 764                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 765                         };
 766                 };
 767
 768                 spi0-1 {
 769                         spi0m1_clk: spi0m1-clk {
 770                                 rockchip,pins =
 771                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
 772                         };
 773
 774                         spi0m1_cs0: spi0m1-cs0 {
 775                                 rockchip,pins =
 776                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
 777                         };
 778
 779                         spi0m1_tx: spi0m1-tx {
 780                                 rockchip,pins =
 781                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
 782                         };
 783
 784                         spi0m1_rx: spi0m1-rx {
 785                                 rockchip,pins =
 786                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
 787                         };
 788
 789                         spi0m1_cs1: spi0m1-cs1 {
 790                                 rockchip,pins =
 791                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
 792                         };
 793                 };
 794
 795                 spi0-2 {
 796                         spi0m2_clk: spi0m2-clk {
 797                                 rockchip,pins =
 798                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
 799                         };
 800
 801                         spi0m2_cs0: spi0m2-cs0 {
 802                                 rockchip,pins =
 803                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
 804                         };
 805
 806                         spi0m2_tx: spi0m2-tx {
 807                                 rockchip,pins =
 808                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
 809                         };
 810
 811                         spi0m2_rx: spi0m2-rx {
 812                                 rockchip,pins =
 813                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
 814                         };
 815                 };
 816
 817                 i2s1 {
 818                         i2s1_mclk: i2s1-mclk {
 819                                 rockchip,pins =
 820                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
 821                         };
 822
 823                         i2s1_sclk: i2s1-sclk {
 824                                 rockchip,pins =
 825                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 826                         };
 827
 828                         i2s1_lrckrx: i2s1-lrckrx {
 829                                 rockchip,pins =
 830                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
 831                         };
 832
 833                         i2s1_lrcktx: i2s1-lrcktx {
 834                                 rockchip,pins =
 835                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 836                         };
 837
 838                         i2s1_sdi: i2s1-sdi {
 839                                 rockchip,pins =
 840                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 841                         };
 842
 843                         i2s1_sdo: i2s1-sdo {
 844                                 rockchip,pins =
 845                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
 846                         };
 847
 848                         i2s1_sdio1: i2s1-sdio1 {
 849                                 rockchip,pins =
 850                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
 851                         };
 852
 853                         i2s1_sdio2: i2s1-sdio2 {
 854                                 rockchip,pins =
 855                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
 856                         };
 857
 858                         i2s1_sdio3: i2s1-sdio3 {
 859                                 rockchip,pins =
 860                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
 861                         };
 862
 863                         i2s1_sleep: i2s1-sleep {
 864                                 rockchip,pins =
 865                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
 866                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
 867                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
 868                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
 869                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
 870                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
 871                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
 872                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
 873                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
 874                         };
 875                 };
 876
 877                 i2s2-0 {
 878                         i2s2m0_mclk: i2s2m0-mclk {
 879                                 rockchip,pins =
 880                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 881                         };
 882
 883                         i2s2m0_sclk: i2s2m0-sclk {
 884                                 rockchip,pins =
 885                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
 886                         };
 887
 888                         i2s2m0_lrckrx: i2s2m0-lrckrx {
 889                                 rockchip,pins =
 890                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
 891                         };
 892
 893                         i2s2m0_lrcktx: i2s2m0-lrcktx {
 894                                 rockchip,pins =
 895                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
 896                         };
 897
 898                         i2s2m0_sdi: i2s2m0-sdi {
 899                                 rockchip,pins =
 900                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
 901                         };
 902
 903                         i2s2m0_sdo: i2s2m0-sdo {
 904                                 rockchip,pins =
 905                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
 906                         };
 907
 908                         i2s2m0_sleep: i2s2m0-sleep {
 909                                 rockchip,pins =
 910                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 911                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
 912                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
 913                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
 914                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
 915                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
 916                         };
 917                 };
 918
 919                 i2s2-1 {
 920                         i2s2m1_mclk: i2s2m1-mclk {
 921                                 rockchip,pins =
 922                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 923                         };
 924
 925                         i2s2m1_sclk: i2s2m1-sclk {
 926                                 rockchip,pins =
 927                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
 928                         };
 929
 930                         i2s2m1_lrckrx: i2sm1-lrckrx {
 931                                 rockchip,pins =
 932                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
 933                         };
 934
 935                         i2s2m1_lrcktx: i2s2m1-lrcktx {
 936                                 rockchip,pins =
 937                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
 938                         };
 939
 940                         i2s2m1_sdi: i2s2m1-sdi {
 941                                 rockchip,pins =
 942                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
 943                         };
 944
 945                         i2s2m1_sdo: i2s2m1-sdo {
 946                                 rockchip,pins =
 947                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
 948                         };
 949
 950                         i2s2m1_sleep: i2s2m1-sleep {
 951                                 rockchip,pins =
 952                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 953                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
 954                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
 955                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
 956                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
 957                         };
 958                 };
 959
 960                 spdif-0 {
 961                         spdifm0_tx: spdifm0-tx {
 962                                 rockchip,pins =
 963                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
 964                         };
 965                 };
 966
 967                 spdif-1 {
 968                         spdifm1_tx: spdifm1-tx {
 969                                 rockchip,pins =
 970                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 971                         };
 972                 };
 973
 974                 spdif-2 {
 975                         spdifm2_tx: spdifm2-tx {
 976                                 rockchip,pins =
 977                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
 978                         };
 979                 };
 980
 981                 sdmmc0-0 {
 982                         sdmmc0m0_pwren: sdmmc0m0-pwren {
 983                                 rockchip,pins =
 984                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
 985                         };
 986
 987                         sdmmc0m0_gpio: sdmmc0m0-gpio {
 988                                 rockchip,pins =
 989                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
 990                         };
 991                 };
 992
 993                 sdmmc0-1 {
 994                         sdmmc0m1_pwren: sdmmc0m1-pwren {
 995                                 rockchip,pins =
 996                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
 997                         };
 998
 999                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1000                                 rockchip,pins =
1001                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1002                         };
1003                 };
1004
1005                 sdmmc0 {
1006                         sdmmc0_clk: sdmmc0-clk {
1007                                 rockchip,pins =
1008                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1009                         };
1010
1011                         sdmmc0_cmd: sdmmc0-cmd {
1012                                 rockchip,pins =
1013                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1014                         };
1015
1016                         sdmmc0_dectn: sdmmc0-dectn {
1017                                 rockchip,pins =
1018                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1019                         };
1020
1021                         sdmmc0_wrprt: sdmmc0-wrprt {
1022                                 rockchip,pins =
1023                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1024                         };
1025
1026                         sdmmc0_bus1: sdmmc0-bus1 {
1027                                 rockchip,pins =
1028                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1029                         };
1030
1031                         sdmmc0_bus4: sdmmc0-bus4 {
1032                                 rockchip,pins =
1033                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1034                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1035                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1036                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1037                         };
1038
1039                         sdmmc0_gpio: sdmmc0-gpio {
1040                                 rockchip,pins =
1041                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1042                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1043                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1044                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1045                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1046                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1047                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1048                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1049                         };
1050                 };
1051
1052                 sdmmc0ext {
1053                         sdmmc0ext_clk: sdmmc0ext-clk {
1054                                 rockchip,pins =
1055                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1056                         };
1057
1058                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1059                                 rockchip,pins =
1060                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1061                         };
1062
1063                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1064                                 rockchip,pins =
1065                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1066                         };
1067
1068                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1069                                 rockchip,pins =
1070                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1071                         };
1072
1073                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1074                                 rockchip,pins =
1075                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1076                         };
1077
1078                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1079                                 rockchip,pins =
1080                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1081                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1082                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1083                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1084                         };
1085
1086                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1087                                 rockchip,pins =
1088                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1089                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1090                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1091                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1092                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1093                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1094                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1095                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1096                         };
1097                 };
1098
1099                 sdmmc1 {
1100                         sdmmc1_clk: sdmmc1-clk {
1101                                 rockchip,pins =
1102                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1103                         };
1104
1105                         sdmmc1_cmd: sdmmc1-cmd {
1106                                 rockchip,pins =
1107                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1108                         };
1109
1110                         sdmmc1_pwren: sdmmc1-pwren {
1111                                 rockchip,pins =
1112                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1113                         };
1114
1115                         sdmmc1_wrprt: sdmmc1-wrprt {
1116                                 rockchip,pins =
1117                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1118                         };
1119
1120                         sdmmc1_dectn: sdmmc1-dectn {
1121                                 rockchip,pins =
1122                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1123                         };
1124
1125                         sdmmc1_bus1: sdmmc1-bus1 {
1126                                 rockchip,pins =
1127                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1128                         };
1129
1130                         sdmmc1_bus4: sdmmc1-bus4 {
1131                                 rockchip,pins =
1132                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1133                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1134                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1135                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1136                         };
1137
1138                         sdmmc1_gpio: sdmmc1-gpio {
1139                                 rockchip,pins =
1140                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1141                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1142                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1143                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1144                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1145                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1146                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1147                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1148                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1149                         };
1150                 };
1151
1152                 emmc {
1153                         emmc_clk: emmc-clk {
1154                                 rockchip,pins =
1155                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1156                         };
1157
1158                         emmc_cmd: emmc-cmd {
1159                                 rockchip,pins =
1160                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1161                         };
1162
1163                         emmc_pwren: emmc-pwren {
1164                                 rockchip,pins =
1165                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1166                         };
1167
1168                         emmc_rstnout: emmc-rstnout {
1169                                 rockchip,pins =
1170                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1171                         };
1172
1173                         emmc_bus1: emmc-bus1 {
1174                                 rockchip,pins =
1175                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1176                         };
1177
1178                         emmc_bus4: emmc-bus4 {
1179                                 rockchip,pins =
1180                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1181                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1182                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1183                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1184                         };
1185
1186                         emmc_bus8: emmc-bus8 {
1187                                 rockchip,pins =
1188                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1189                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1190                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1191                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1192                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1193                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1194                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1195                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1196                         };
1197                 };
1198
1199                 pwm0 {
1200                         pwm0_pin: pwm0-pin {
1201                                 rockchip,pins =
1202                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1203                         };
1204                 };
1205
1206                 pwm1 {
1207                         pwm1_pin: pwm1-pin {
1208                                 rockchip,pins =
1209                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1210                         };
1211                 };
1212
1213                 pwm2 {
1214                         pwm2_pin: pwm2-pin {
1215                                 rockchip,pins =
1216                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1217                         };
1218                 };
1219
1220                 pwmir {
1221                         pwmir_pin: pwmir-pin {
1222                                 rockchip,pins =
1223                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1224                         };
1225                 };
1226
1227                 gmac-0 {
1228                         rgmiim0_pins: rgmiim0-pins {
1229                                 rockchip,pins =
1230                                         /* mac_txclk */
1231                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1232                                         /* mac_rxclk */
1233                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1234                                         /* mac_mdio */
1235                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1236                                         /* mac_txen */
1237                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1238                                         /* mac_clk */
1239                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1240                                         /* mac_rxdv */
1241                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1242                                         /* mac_mdc */
1243                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1244                                         /* mac_rxd1 */
1245                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1246                                         /* mac_rxd0 */
1247                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1248                                         /* mac_txd1 */
1249                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1250                                         /* mac_txd0 */
1251                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1252                                         /* mac_rxd3 */
1253                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1254                                         /* mac_rxd2 */
1255                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1256                                         /* mac_txd3 */
1257                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1258                                         /* mac_txd2 */
1259                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1260                         };
1261
1262                         rmiim0_pins: rmiim0-pins {
1263                                 rockchip,pins =
1264                                         /* mac_mdio */
1265                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1266                                         /* mac_txen */
1267                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1268                                         /* mac_clk */
1269                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1270                                         /* mac_rxer */
1271                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1272                                         /* mac_rxdv */
1273                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1274                                         /* mac_mdc */
1275                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1276                                         /* mac_rxd1 */
1277                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1278                                         /* mac_rxd0 */
1279                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1280                                         /* mac_txd1 */
1281                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1282                                         /* mac_txd0 */
1283                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1284                         };
1285                 };
1286
1287                 gmac-1 {
1288                         rgmiim1_pins: rgmiim1-pins {
1289                                 rockchip,pins =
1290                                         /* mac_txclk */
1291                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1292                                         /* mac_rxclk */
1293                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1294                                         /* mac_mdio */
1295                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1296                                         /* mac_txen */
1297                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1298                                         /* mac_clk */
1299                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1300                                         /* mac_rxdv */
1301                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1302                                         /* mac_mdc */
1303                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1304                                         /* mac_rxd1 */
1305                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1306                                         /* mac_rxd0 */
1307                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1308                                         /* mac_txd1 */
1309                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1310                                         /* mac_txd0 */
1311                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1312                                         /* mac_rxd3 */
1313                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1314                                         /* mac_rxd2 */
1315                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1316                                         /* mac_txd3 */
1317                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1318                                         /* mac_txd2 */
1319                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1320
1321                                         /* mac_txclk */
1322                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1323                                         /* mac_txen */
1324                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1325                                         /* mac_clk */
1326                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1327                                         /* mac_txd1 */
1328                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1329                                         /* mac_txd0 */
1330                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1331                                         /* mac_txd3 */
1332                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1333                                         /* mac_txd2 */
1334                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1335                         };
1336
1337                         rmiim1_pins: rmiim1-pins {
1338                                 rockchip,pins =
1339                                         /* mac_mdio */
1340                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1341                                         /* mac_txen */
1342                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1343                                         /* mac_clk */
1344                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1345                                         /* mac_rxer */
1346                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1347                                         /* mac_rxdv */
1348                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1349                                         /* mac_mdc */
1350                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1351                                         /* mac_rxd1 */
1352                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1353                                         /* mac_rxd0 */
1354                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1355                                         /* mac_txd1 */
1356                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1357                                         /* mac_txd0 */
1358                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1359
1360                                         /* mac_mdio */
1361                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1362                                         /* mac_txen */
1363                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1364                                         /* mac_clk */
1365                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1366                                         /* mac_mdc */
1367                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1368                                         /* mac_txd1 */
1369                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1370                                         /* mac_txd0 */
1371                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1372                         };
1373                 };
1374
1375                 gmac2phy {
1376                         fephyled_speed100: fephyled-speed100 {
1377                                 rockchip,pins =
1378                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1379                         };
1380
1381                         fephyled_speed10: fephyled-speed10 {
1382                                 rockchip,pins =
1383                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1384                         };
1385
1386                         fephyled_duplex: fephyled-duplex {
1387                                 rockchip,pins =
1388                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1389                         };
1390
1391                         fephyled_rxm0: fephyled-rxm0 {
1392                                 rockchip,pins =
1393                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1394                         };
1395
1396                         fephyled_txm0: fephyled-txm0 {
1397                                 rockchip,pins =
1398                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1399                         };
1400
1401                         fephyled_linkm0: fephyled-linkm0 {
1402                                 rockchip,pins =
1403                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1404                         };
1405
1406                         fephyled_rxm1: fephyled-rxm1 {
1407                                 rockchip,pins =
1408                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1409                         };
1410
1411                         fephyled_txm1: fephyled-txm1 {
1412                                 rockchip,pins =
1413                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1414                         };
1415
1416                         fephyled_linkm1: fephyled-linkm1 {
1417                                 rockchip,pins =
1418                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1419                         };
1420                 };
1421
1422                 tsadc_pin {
1423                         tsadc_int: tsadc-int {
1424                                 rockchip,pins =
1425                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1426                         };
1427                         tsadc_gpio: tsadc-gpio {
1428                                 rockchip,pins =
1429                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1430                         };
1431                 };
1432
1433                 hdmi_pin {
1434                         hdmi_cec: hdmi-cec {
1435                                 rockchip,pins =
1436                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1437                         };
1438
1439                         hdmi_hpd: hdmi-hpd {
1440                                 rockchip,pins =
1441                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1442                         };
1443                 };
1444
1445                 cif-0 {
1446                         dvp_d2d9_m0:dvp-d2d9-m0 {
1447                                 rockchip,pins =
1448                                         /* cif_d0 */
1449                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1450                                         /* cif_d1 */
1451                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1452                                         /* cif_d2 */
1453                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1454                                         /* cif_d3 */
1455                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1456                                         /* cif_d4 */
1457                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1458                                         /* cif_d5m0 */
1459                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1460                                         /* cif_d6m0 */
1461                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1462                                         /* cif_d7m0 */
1463                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1464                                         /* cif_href */
1465                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1466                                         /* cif_vsync */
1467                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1468                                         /* cif_clkoutm0 */
1469                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1470                                         /* cif_clkin */
1471                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1472                         };
1473                 };
1474
1475                 cif-1 {
1476                         dvp_d2d9_m1:dvp-d2d9-m1 {
1477                                 rockchip,pins =
1478                                         /* cif_d0 */
1479                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1480                                         /* cif_d1 */
1481                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1482                                         /* cif_d2 */
1483                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1484                                         /* cif_d3 */
1485                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1486                                         /* cif_d4 */
1487                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1488                                         /* cif_d5m1 */
1489                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1490                                         /* cif_d6m1 */
1491                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1492                                         /* cif_d7m1 */
1493                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1494                                         /* cif_href */
1495                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1496                                         /* cif_vsync */
1497                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1498                                         /* cif_clkoutm1 */
1499                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1500                                         /* cif_clkin */
1501                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1502                         };
1503                 };
1504         };
1505 };