drivers/ram/rockchip/sdram_rk3328.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
   4  */
   5 #include <common.h>
   6 #include <clk.h>
   7 #include <debug_uart.h>
   8 #include <dm.h>
   9 #include <dt-structs.h>
  10 #include <init.h>
  11 #include <ram.h>
  12 #include <regmap.h>
  13 #include <syscon.h>
  14 #include <asm/io.h>
  15 #include <asm/arch-rockchip/clock.h>
  16 #include <asm/arch-rockchip/cru_rk3328.h>
  17 #include <asm/arch-rockchip/grf_rk3328.h>
  18 #include <asm/arch-rockchip/sdram.h>
  19 #include <asm/arch-rockchip/sdram_rk3328.h>
  20 #include <asm/arch-rockchip/uart.h>
  21
  22 struct dram_info {
  23 #ifdef CONFIG_TPL_BUILD
  24         struct ddr_pctl_regs *pctl;
  25         struct ddr_phy_regs *phy;
  26         struct clk ddr_clk;
  27         struct rk3328_cru *cru;
  28         struct msch_regs *msch;
  29         struct rk3328_ddr_grf_regs *ddr_grf;
  30 #endif
  31         struct ram_info info;
  32         struct rk3328_grf_regs *grf;
  33 };
  34
  35 #ifdef CONFIG_TPL_BUILD
  36
  37 struct rk3328_sdram_channel sdram_ch;
  38
  39 struct rockchip_dmc_plat {
  40 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  41         struct dtd_rockchip_rk3328_dmc dtplat;
  42 #else
  43         struct rk3328_sdram_params sdram_params;
  44 #endif
  45         struct regmap *map;
  46 };
  47
  48 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  49 static int conv_of_platdata(struct udevice *dev)
  50 {
  51         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
  52         struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
  53         int ret;
  54
  55         ret = regmap_init_mem_platdata(dev, dtplat->reg,
  56                                        ARRAY_SIZE(dtplat->reg) / 2,
  57                                        &plat->map);
  58         if (ret)
  59                 return ret;
  60
  61         return 0;
  62 }
  63 #endif
  64
  65 static void rkclk_ddr_reset(struct dram_info *dram,
  66                             u32 ctl_srstn, u32 ctl_psrstn,
  67                             u32 phy_srstn, u32 phy_psrstn)
  68 {
  69         writel(ddrctrl_srstn_req(ctl_srstn) | ddrctrl_psrstn_req(ctl_psrstn) |
  70                 ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn),
  71                 &dram->cru->softrst_con[5]);
  72         writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]);
  73 }
  74
  75 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz)
  76 {
  77         unsigned int refdiv, postdiv1, postdiv2, fbdiv;
  78         int delay = 1000;
  79         u32 mhz = hz / MHZ;
  80
  81         refdiv = 1;
  82         if (mhz <= 300) {
  83                 postdiv1 = 4;
  84                 postdiv2 = 2;
  85         } else if (mhz <= 400) {
  86                 postdiv1 = 6;
  87                 postdiv2 = 1;
  88         } else if (mhz <= 600) {
  89                 postdiv1 = 4;
  90                 postdiv2 = 1;
  91         } else if (mhz <= 800) {
  92                 postdiv1 = 3;
  93                 postdiv2 = 1;
  94         } else if (mhz <= 1600) {
  95                 postdiv1 = 2;
  96                 postdiv2 = 1;
  97         } else {
  98                 postdiv1 = 1;
  99                 postdiv2 = 1;
 100         }
 101         fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24;
 102
 103         writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con);
 104         writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]);
 105         writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
 106                &dram->cru->dpll_con[1]);
 107
 108         while (delay > 0) {
 109                 udelay(1);
 110                 if (LOCK(readl(&dram->cru->dpll_con[1])))
 111                         break;
 112                 delay--;
 113         }
 114
 115         writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con);
 116 }
 117
 118 static void rkclk_configure_ddr(struct dram_info *dram,
 119                                 struct rk3328_sdram_params *sdram_params)
 120 {
 121         void __iomem *phy_base = dram->phy;
 122
 123         /* choose DPLL for ddr clk source */
 124         clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7);
 125
 126         /* for inno ddr phy need 2*freq */
 127         rkclk_set_dpll(dram,  sdram_params->base.ddr_freq * MHZ * 2);
 128 }
 129
 130 /* return ddrconfig value
 131  *       (-1), find ddrconfig fail
 132  *       other, the ddrconfig value
 133  * only support cs0_row >= cs1_row
 134  */
 135 static u32 calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
 136 {
 137         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 138         u32 cs, bw, die_bw, col, row, bank;
 139         u32 cs1_row;
 140         u32 i, tmp;
 141         u32 ddrconf = -1;
 142
 143         cs = cap_info->rank;
 144         bw = cap_info->bw;
 145         die_bw = cap_info->dbw;
 146         col = cap_info->col;
 147         row = cap_info->cs0_row;
 148         cs1_row = cap_info->cs1_row;
 149         bank = cap_info->bk;
 150
 151         if (sdram_params->base.dramtype == DDR4) {
 152                 /* when DDR_TEST, CS always at MSB position for easy test */
 153                 if (cs == 2 && row == cs1_row) {
 154                         /* include 2cs cap both 2^n  or both (2^n - 2^(n-2)) */
 155                         tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) |
 156                               die_bw;
 157                         for (i = 17; i < 21; i++) {
 158                                 if (((tmp & 0x7) ==
 159                                      (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
 160                                     ((tmp & 0x3c) <=
 161                                      (ddr4_cfg_2_rbc[i - 10] & 0x3c))) {
 162                                         ddrconf = i;
 163                                         goto out;
 164                                 }
 165                         }
 166                 }
 167
 168                 tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw;
 169                 for (i = 10; i < 17; i++) {
 170                         if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
 171                             ((tmp & 0x3c) <= (ddr4_cfg_2_rbc[i - 10] & 0x3c)) &&
 172                             ((tmp & 0x40) <= (ddr4_cfg_2_rbc[i - 10] & 0x40))) {
 173                                 ddrconf = i;
 174                                 goto out;
 175                         }
 176                 }
 177         } else {
 178                 if (bank == 2) {
 179                         ddrconf = 8;
 180                         goto out;
 181                 }
 182
 183                 /* when DDR_TEST, CS always at MSB position for easy test */
 184                 if (cs == 2 && row == cs1_row) {
 185                         /* include 2cs cap both 2^n  or both (2^n - 2^(n-2)) */
 186                         for (i = 5; i < 8; i++) {
 187                                 if ((bw + col - 11) == (ddr_cfg_2_rbc[i] &
 188                                                         0x3)) {
 189                                         ddrconf = i;
 190                                         goto out;
 191                                 }
 192                         }
 193                 }
 194
 195                 tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0);
 196                 for (i = 0; i < 5; i++)
 197                         if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) &&
 198                             ((tmp & 0x30) <= (ddr_cfg_2_rbc[i] & 0x30))) {
 199                                 ddrconf = i;
 200                                 goto out;
 201                         }
 202         }
 203
 204 out:
 205         if (ddrconf > 20)
 206                 printf("calculate ddrconfig error\n");
 207
 208         return ddrconf;
 209 }
 210
 211 /*******
 212  * calculate controller dram address map, and setting to register.
 213  * argument sdram_ch.ddrconf must be right value before
 214  * call this function.
 215  *******/
 216 static void set_ctl_address_map(struct dram_info *dram,
 217                                 struct rk3328_sdram_params *sdram_params)
 218 {
 219         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 220         void __iomem *pctl_base = dram->pctl;
 221
 222         sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
 223                           &addrmap[cap_info->ddrconfig][0], 9 * 4);
 224         if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4)
 225                 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
 226         if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1)
 227                 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
 228
 229         if (cap_info->rank == 1)
 230                 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);
 231 }
 232
 233 static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
 234 {
 235         void __iomem *pctl_base = dram->pctl;
 236         u32 dis_auto_zq = 0;
 237         u32 pwrctl;
 238         u32 ret;
 239
 240         /* disable auto low-power */
 241         pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
 242         writel(0, pctl_base + DDR_PCTL2_PWRCTL);
 243
 244         dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl);
 245
 246         ret = phy_data_training(dram->phy, cs, dramtype);
 247
 248         pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq);
 249
 250         /* restore auto low-power */
 251         writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
 252
 253         return ret;
 254 }
 255
 256 static void rx_deskew_switch_adjust(struct dram_info *dram)
 257 {
 258         u32 i, deskew_val;
 259         u32 gate_val = 0;
 260         void __iomem *phy_base = dram->phy;
 261
 262         for (i = 0; i < 4; i++)
 263                 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
 264
 265         deskew_val = (gate_val >> 3) + 1;
 266         deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val;
 267         clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2);
 268         clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4,
 269                         (deskew_val & 0x1c) << 2);
 270 }
 271
 272 static void tx_deskew_switch_adjust(struct dram_info *dram)
 273 {
 274         void __iomem *phy_base = dram->phy;
 275
 276         clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1);
 277 }
 278
 279 static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
 280 {
 281         writel(ddrconfig, &dram->msch->ddrconf);
 282 }
 283
 284 static void sdram_msch_config(struct msch_regs *msch,
 285                               struct sdram_msch_timings *noc_timings)
 286 {
 287         writel(noc_timings->ddrtiming.d32, &msch->ddrtiming);
 288
 289         writel(noc_timings->ddrmode.d32, &msch->ddrmode);
 290         writel(noc_timings->readlatency, &msch->readlatency);
 291
 292         writel(noc_timings->activate.d32, &msch->activate);
 293         writel(noc_timings->devtodev.d32, &msch->devtodev);
 294         writel(noc_timings->ddr4timing.d32, &msch->ddr4_timing);
 295         writel(noc_timings->agingx0, &msch->aging0);
 296         writel(noc_timings->agingx0, &msch->aging1);
 297         writel(noc_timings->agingx0, &msch->aging2);
 298         writel(noc_timings->agingx0, &msch->aging3);
 299         writel(noc_timings->agingx0, &msch->aging4);
 300         writel(noc_timings->agingx0, &msch->aging5);
 301 }
 302
 303 static void dram_all_config(struct dram_info *dram,
 304                             struct rk3328_sdram_params *sdram_params)
 305 {
 306         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 307         u32 sys_reg2 = 0;
 308         u32 sys_reg3 = 0;
 309
 310         set_ddrconfig(dram, cap_info->ddrconfig);
 311         sdram_org_config(cap_info, &sdram_params->base, &sys_reg2,
 312                          &sys_reg3, 0);
 313         writel(sys_reg2, &dram->grf->os_reg[2]);
 314         writel(sys_reg3, &dram->grf->os_reg[3]);
 315
 316         sdram_msch_config(dram->msch, &sdram_ch.noc_timings);
 317 }
 318
 319 static void enable_low_power(struct dram_info *dram,
 320                              struct rk3328_sdram_params *sdram_params)
 321 {
 322         void __iomem *pctl_base = dram->pctl;
 323
 324         /* enable upctl2 axi clock auto gating */
 325         writel(0x00800000, &dram->ddr_grf->ddr_grf_con[0]);
 326         writel(0x20012001, &dram->ddr_grf->ddr_grf_con[2]);
 327         /* enable upctl2 core clock auto gating */
 328         writel(0x001e001a, &dram->ddr_grf->ddr_grf_con[2]);
 329         /* enable sr, pd */
 330         if (PD_IDLE == 0)
 331                 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
 332         else
 333                 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
 334         if (SR_IDLE == 0)
 335                 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL,      1);
 336         else
 337                 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
 338         setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3));
 339 }
 340
 341 static int sdram_init(struct dram_info *dram,
 342                       struct rk3328_sdram_params *sdram_params, u32 pre_init)
 343 {
 344         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 345         void __iomem *pctl_base = dram->pctl;
 346
 347         rkclk_ddr_reset(dram, 1, 1, 1, 1);
 348         udelay(10);
 349         /*
 350          * dereset ddr phy psrstn to config pll,
 351          * if using phy pll psrstn must be dereset
 352          * before config pll
 353          */
 354         rkclk_ddr_reset(dram, 1, 1, 1, 0);
 355         rkclk_configure_ddr(dram, sdram_params);
 356
 357         /* release phy srst to provide clk to ctrl */
 358         rkclk_ddr_reset(dram, 1, 1, 0, 0);
 359         udelay(10);
 360         phy_soft_reset(dram->phy);
 361         /* release ctrl presetn, and config ctl registers */
 362         rkclk_ddr_reset(dram, 1, 0, 0, 0);
 363         pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE);
 364         cap_info->ddrconfig = calculate_ddrconfig(sdram_params);
 365         set_ctl_address_map(dram, sdram_params);
 366         phy_cfg(dram->phy, &sdram_params->phy_regs, &sdram_params->skew,
 367                 &sdram_params->base, cap_info->bw);
 368
 369         /* enable dfi_init_start to init phy after ctl srstn deassert */
 370         setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
 371         rkclk_ddr_reset(dram, 0, 0, 0, 0);
 372         /* wait for dfi_init_done and dram init complete */
 373         while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
 374                 continue;
 375
 376         /* do ddr gate training */
 377         if (data_training(dram, 0, sdram_params->base.dramtype) != 0) {
 378                 printf("data training error\n");
 379                 return -1;
 380         }
 381
 382         if (sdram_params->base.dramtype == DDR4)
 383                 pctl_write_vrefdq(dram->pctl, 0x3, 5670,
 384                                   sdram_params->base.dramtype);
 385
 386         if (pre_init != 0) {
 387                 rx_deskew_switch_adjust(dram);
 388                 tx_deskew_switch_adjust(dram);
 389         }
 390
 391         dram_all_config(dram, sdram_params);
 392         enable_low_power(dram, sdram_params);
 393
 394         return 0;
 395 }
 396
 397 static u64 dram_detect_cap(struct dram_info *dram,
 398                            struct rk3328_sdram_params *sdram_params,
 399                            unsigned char channel)
 400 {
 401         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 402
 403         /*
 404          * for ddr3: ddrconf = 3
 405          * for ddr4: ddrconf = 12
 406          * for lpddr3: ddrconf = 3
 407          * default bw = 1
 408          */
 409         u32 bk, bktmp;
 410         u32 col, coltmp;
 411         u32 rowtmp;
 412         u32 cs;
 413         u32 bw = 1;
 414         u32 dram_type = sdram_params->base.dramtype;
 415
 416         if (dram_type != DDR4) {
 417                 /* detect col and bk for ddr3/lpddr3 */
 418                 coltmp = 12;
 419                 bktmp = 3;
 420                 rowtmp = 16;
 421
 422                 if (sdram_detect_col(cap_info, coltmp) != 0)
 423                         goto cap_err;
 424                 sdram_detect_bank(cap_info, coltmp, bktmp);
 425                 sdram_detect_dbw(cap_info, dram_type);
 426         } else {
 427                 /* detect bg for ddr4 */
 428                 coltmp = 10;
 429                 bktmp = 4;
 430                 rowtmp = 17;
 431
 432                 col = 10;
 433                 bk = 2;
 434                 cap_info->col = col;
 435                 cap_info->bk = bk;
 436                 sdram_detect_bg(cap_info, coltmp);
 437         }
 438
 439         /* detect row */
 440         if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0)
 441                 goto cap_err;
 442
 443         /* detect row_3_4 */
 444         sdram_detect_row_3_4(cap_info, coltmp, bktmp);
 445
 446         /* bw and cs detect using data training */
 447         if (data_training(dram, 1, dram_type) == 0)
 448                 cs = 1;
 449         else
 450                 cs = 0;
 451         cap_info->rank = cs + 1;
 452
 453         bw = 2;
 454         cap_info->bw = bw;
 455
 456         cap_info->cs0_high16bit_row = cap_info->cs0_row;
 457         if (cs) {
 458                 cap_info->cs1_row = cap_info->cs0_row;
 459                 cap_info->cs1_high16bit_row = cap_info->cs0_row;
 460         } else {
 461                 cap_info->cs1_row = 0;
 462                 cap_info->cs1_high16bit_row = 0;
 463         }
 464
 465         return 0;
 466 cap_err:
 467         return -1;
 468 }
 469
 470 static int sdram_init_detect(struct dram_info *dram,
 471                              struct rk3328_sdram_params *sdram_params)
 472 {
 473         u32 sys_reg = 0;
 474         u32 sys_reg3 = 0;
 475         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 476
 477         debug("Starting SDRAM initialization...\n");
 478
 479         memcpy(&sdram_ch, &sdram_params->ch,
 480                sizeof(struct rk3328_sdram_channel));
 481
 482         sdram_init(dram, sdram_params, 0);
 483         dram_detect_cap(dram, sdram_params, 0);
 484
 485         /* modify bw, cs related timing */
 486         pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info,
 487                                    sdram_params->base.dramtype);
 488
 489         if (cap_info->bw == 2)
 490                 sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
 491         else
 492                 sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
 493
 494         /* reinit sdram by real dram cap */
 495         sdram_init(dram, sdram_params, 1);
 496
 497         /* redetect cs1 row */
 498         sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype);
 499         if (cap_info->cs1_row) {
 500                 sys_reg = readl(&dram->grf->os_reg[2]);
 501                 sys_reg3 = readl(&dram->grf->os_reg[3]);
 502                 SYS_REG_ENC_CS1_ROW(cap_info->cs1_row,
 503                                     sys_reg, sys_reg3, 0);
 504                 writel(sys_reg, &dram->grf->os_reg[2]);
 505                 writel(sys_reg3, &dram->grf->os_reg[3]);
 506         }
 507
 508         sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base);
 509
 510         return 0;
 511 }
 512
 513 static int rk3328_dmc_init(struct udevice *dev)
 514 {
 515         struct dram_info *priv = dev_get_priv(dev);
 516         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
 517         int ret;
 518
 519 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 520         struct rk3328_sdram_params *params = &plat->sdram_params;
 521 #else
 522         struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
 523         struct rk3328_sdram_params *params =
 524                                         (void *)dtplat->rockchip_sdram_params;
 525
 526         ret = conv_of_platdata(dev);
 527         if (ret)
 528                 return ret;
 529 #endif
 530         priv->phy = regmap_get_range(plat->map, 0);
 531         priv->pctl = regmap_get_range(plat->map, 1);
 532         priv->grf = regmap_get_range(plat->map, 2);
 533         priv->cru = regmap_get_range(plat->map, 3);
 534         priv->msch = regmap_get_range(plat->map, 4);
 535         priv->ddr_grf = regmap_get_range(plat->map, 5);
 536
 537         debug("%s phy %p pctrl %p grf %p cru %p msch %p ddr_grf %p\n",
 538               __func__, priv->phy, priv->pctl, priv->grf, priv->cru,
 539               priv->msch, priv->ddr_grf);
 540         ret = sdram_init_detect(priv, params);
 541         if (ret < 0) {
 542                 printf("%s DRAM init failed%d\n", __func__, ret);
 543                 return ret;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int rk3328_dmc_ofdata_to_platdata(struct udevice *dev)
 550 {
 551 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 552         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
 553         int ret;
 554
 555         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
 556                                  (u32 *)&plat->sdram_params,
 557                                  sizeof(plat->sdram_params) / sizeof(u32));
 558         if (ret) {
 559                 printf("%s: Cannot read rockchip,sdram-params %d\n",
 560                        __func__, ret);
 561                 return ret;
 562         }
 563         ret = regmap_init_mem(dev, &plat->map);
 564         if (ret)
 565                 printf("%s: regmap failed %d\n", __func__, ret);
 566 #endif
 567         return 0;
 568 }
 569
 570 #endif
 571
 572 static int rk3328_dmc_probe(struct udevice *dev)
 573 {
 574 #ifdef CONFIG_TPL_BUILD
 575         if (rk3328_dmc_init(dev))
 576                 return 0;
 577 #else
 578         struct dram_info *priv = dev_get_priv(dev);
 579
 580         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 581         debug("%s: grf=%p\n", __func__, priv->grf);
 582         priv->info.base = CONFIG_SYS_SDRAM_BASE;
 583         priv->info.size = rockchip_sdram_size(
 584                                 (phys_addr_t)&priv->grf->os_reg[2]);
 585 #endif
 586         return 0;
 587 }
 588
 589 static int rk3328_dmc_get_info(struct udevice *dev, struct ram_info *info)
 590 {
 591         struct dram_info *priv = dev_get_priv(dev);
 592
 593         *info = priv->info;
 594
 595         return 0;
 596 }
 597
 598 static struct ram_ops rk3328_dmc_ops = {
 599         .get_info = rk3328_dmc_get_info,
 600 };
 601
 602 static const struct udevice_id rk3328_dmc_ids[] = {
 603         { .compatible = "rockchip,rk3328-dmc" },
 604         { }
 605 };
 606
 607 U_BOOT_DRIVER(dmc_rk3328) = {
 608         .name = "rockchip_rk3328_dmc",
 609         .id = UCLASS_RAM,
 610         .of_match = rk3328_dmc_ids,
 611         .ops = &rk3328_dmc_ops,
 612 #ifdef CONFIG_TPL_BUILD
 613         .ofdata_to_platdata = rk3328_dmc_ofdata_to_platdata,
 614 #endif
 615         .probe = rk3328_dmc_probe,
 616         .priv_auto_alloc_size = sizeof(struct dram_info),
 617 #ifdef CONFIG_TPL_BUILD
 618         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
 619 #endif
 620 };