1 // SPDX-License-Identifier: GPL-2.0+
4 * Corscience GmbH & Co. KG, <www.corscience.de>
9 * Derived from Devkit8000 code by
16 #include <status_led.h>
19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/mux.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
23 #include "tricorder.h"
24 #include "tricorder-eeprom.h"
26 DECLARE_GLOBAL_DATA_PTR;
30 * Description: Early hardware init.
34 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
36 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
42 * get_eeprom - read the eeprom
44 * @eeprom - pointer to a eeprom struct to fill
46 * This function will panic() on wrong EEPROM content
48 static void get_eeprom(struct tricorder_eeprom *eeprom)
53 panic("No eeprom given!\n");
55 ret = gpio_request(7, "BMS");
57 panic("gpio: requesting BMS pin failed\n");
59 ret = gpio_direction_input(7);
61 panic("gpio: set BMS as input failed\n");
63 ret = gpio_get_value(7);
65 panic("gpio: get BMS pin state failed\n");
70 /* BMS is _not_ set, do the EEPROM check */
71 ret = tricorder_get_eeprom(0x51, eeprom);
73 if (strncmp(eeprom->board_name, "CS10411", 7) != 0)
74 panic("Wrong board name '%.*s'\n",
75 sizeof(eeprom->board_name),
77 if (eeprom->board_version[0] < 'D')
78 panic("Wrong board version '%.*s'\n",
79 sizeof(eeprom->board_version),
80 eeprom->board_version);
82 panic("Could not get board revision\n");
85 memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
90 * print_hwversion - print out a HW version string
92 * @eeprom - pointer to the eeprom
94 static void print_hwversion(struct tricorder_eeprom *eeprom)
98 panic("No eeprom given!");
100 printf("Board %.*s:%.*s serial %.*s",
101 sizeof(eeprom->board_name), eeprom->board_name,
102 sizeof(eeprom->board_version), eeprom->board_version,
103 sizeof(eeprom->board_serial), eeprom->board_serial);
105 len = strnlen(eeprom->interface_version,
106 sizeof(eeprom->interface_version));
108 printf(" HW interface version %.*s",
109 sizeof(eeprom->interface_version),
110 eeprom->interface_version);
115 * Routine: misc_init_r
116 * Description: Configure board specific parts
118 int misc_init_r(void)
120 struct tricorder_eeprom eeprom;
122 print_hwversion(&eeprom);
124 twl4030_power_init();
125 status_led_set(0, CONFIG_LED_STATUS_ON);
126 status_led_set(1, CONFIG_LED_STATUS_ON);
127 status_led_set(2, CONFIG_LED_STATUS_ON);
129 omap_die_id_display();
135 * Routine: set_muxconf_regs
136 * Description: Setting up the configuration Mux registers specific to the
137 * hardware. Many pins need to be moved from protect to primary
140 void set_muxconf_regs(void)
145 #if defined(CONFIG_MMC)
146 int board_mmc_init(bd_t *bis)
148 return omap_mmc_init(0, 0, 0, -1, -1);
152 #if defined(CONFIG_MMC)
153 void board_mmc_power_init(void)
155 twl4030_power_mmc_init(0);
160 * Routine: get_board_mem_timings
161 * Description: If we use SPL then there is no x-loader nor config header
162 * so we have to setup the DDR timings ourself on the first bank. This
163 * provides the timing values back to the function that configures
164 * the memory. We have either one or two banks of 128MB DDR.
166 void get_board_mem_timings(struct board_sdrc_timings *timings)
168 struct tricorder_eeprom eeprom;
171 /* General SDRC config */
172 if (eeprom.board_version[0] > 'D') {
173 /* use optimized timings for our SDRAM device */
174 timings->mcfg = MCFG((256 << 20), 14);
175 #define MT46H64M32_TDAL 6 /* Twr/Tck + Trp/tck */
176 /* 15/6 + 18/6 = 5.5 -> 6 */
177 #define MT46H64M32_TDPL 3 /* 15/6 = 2.5 -> 3 (Twr) */
178 #define MT46H64M32_TRRD 2 /* 12/6 = 2 */
179 #define MT46H64M32_TRCD 3 /* 18/6 = 3 */
180 #define MT46H64M32_TRP 3 /* 18/6 = 3 */
181 #define MT46H64M32_TRAS 7 /* 42/6 = 7 */
182 #define MT46H64M32_TRC 10 /* 60/6 = 10 */
183 #define MT46H64M32_TRFC 12 /* 72/6 = 12 */
184 timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC,
185 MT46H64M32_TRAS, MT46H64M32_TRP,
186 MT46H64M32_TRCD, MT46H64M32_TRRD,
190 #define MT46H64M32_TWTR 1
191 #define MT46H64M32_TCKE 1
192 #define MT46H64M32_XSR 19 /* 112.5/6 = 18.75 => ~19 */
193 #define MT46H64M32_TXP 1
194 timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE,
195 MT46H64M32_TXP, MT46H64M32_XSR);
197 timings->mr = MICRON_V_MR_165;
198 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
200 /* use conservative beagleboard timings as default */
201 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
202 timings->ctrla = MICRON_V_ACTIMA_165;
203 timings->ctrlb = MICRON_V_ACTIMB_165;
204 timings->mr = MICRON_V_MR_165;
205 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;