drivers/memory/stm32-fmc2-ebi.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) STMicroelectronics 2020
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <reset.h>
  10 #include <linux/bitfield.h>
  11 #include <linux/err.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/ioport.h>
  14
  15 /* FMC2 Controller Registers */
  16 #define FMC2_BCR1                       0x0
  17 #define FMC2_BTR1                       0x4
  18 #define FMC2_BCR(x)                     ((x) * 0x8 + FMC2_BCR1)
  19 #define FMC2_BTR(x)                     ((x) * 0x8 + FMC2_BTR1)
  20 #define FMC2_PCSCNTR                    0x20
  21 #define FMC2_BWTR1                      0x104
  22 #define FMC2_BWTR(x)                    ((x) * 0x8 + FMC2_BWTR1)
  23
  24 /* Register: FMC2_BCR1 */
  25 #define FMC2_BCR1_CCLKEN                BIT(20)
  26 #define FMC2_BCR1_FMC2EN                BIT(31)
  27
  28 /* Register: FMC2_BCRx */
  29 #define FMC2_BCR_MBKEN                  BIT(0)
  30 #define FMC2_BCR_MUXEN                  BIT(1)
  31 #define FMC2_BCR_MTYP                   GENMASK(3, 2)
  32 #define FMC2_BCR_MWID                   GENMASK(5, 4)
  33 #define FMC2_BCR_FACCEN                 BIT(6)
  34 #define FMC2_BCR_BURSTEN                BIT(8)
  35 #define FMC2_BCR_WAITPOL                BIT(9)
  36 #define FMC2_BCR_WAITCFG                BIT(11)
  37 #define FMC2_BCR_WREN                   BIT(12)
  38 #define FMC2_BCR_WAITEN                 BIT(13)
  39 #define FMC2_BCR_EXTMOD                 BIT(14)
  40 #define FMC2_BCR_ASYNCWAIT              BIT(15)
  41 #define FMC2_BCR_CPSIZE                 GENMASK(18, 16)
  42 #define FMC2_BCR_CBURSTRW               BIT(19)
  43 #define FMC2_BCR_NBLSET                 GENMASK(23, 22)
  44
  45 /* Register: FMC2_BTRx/FMC2_BWTRx */
  46 #define FMC2_BXTR_ADDSET                GENMASK(3, 0)
  47 #define FMC2_BXTR_ADDHLD                GENMASK(7, 4)
  48 #define FMC2_BXTR_DATAST                GENMASK(15, 8)
  49 #define FMC2_BXTR_BUSTURN               GENMASK(19, 16)
  50 #define FMC2_BTR_CLKDIV                 GENMASK(23, 20)
  51 #define FMC2_BTR_DATLAT                 GENMASK(27, 24)
  52 #define FMC2_BXTR_ACCMOD                GENMASK(29, 28)
  53 #define FMC2_BXTR_DATAHLD               GENMASK(31, 30)
  54
  55 /* Register: FMC2_PCSCNTR */
  56 #define FMC2_PCSCNTR_CSCOUNT            GENMASK(15, 0)
  57 #define FMC2_PCSCNTR_CNTBEN(x)          BIT((x) + 16)
  58
  59 #define FMC2_MAX_EBI_CE                 4
  60 #define FMC2_MAX_BANKS                  5
  61
  62 #define FMC2_BCR_CPSIZE_0               0x0
  63 #define FMC2_BCR_CPSIZE_128             0x1
  64 #define FMC2_BCR_CPSIZE_256             0x2
  65 #define FMC2_BCR_CPSIZE_512             0x3
  66 #define FMC2_BCR_CPSIZE_1024            0x4
  67
  68 #define FMC2_BCR_MWID_8                 0x0
  69 #define FMC2_BCR_MWID_16                0x1
  70
  71 #define FMC2_BCR_MTYP_SRAM              0x0
  72 #define FMC2_BCR_MTYP_PSRAM             0x1
  73 #define FMC2_BCR_MTYP_NOR               0x2
  74
  75 #define FMC2_BXTR_EXTMOD_A              0x0
  76 #define FMC2_BXTR_EXTMOD_B              0x1
  77 #define FMC2_BXTR_EXTMOD_C              0x2
  78 #define FMC2_BXTR_EXTMOD_D              0x3
  79
  80 #define FMC2_BCR_NBLSET_MAX             0x3
  81 #define FMC2_BXTR_ADDSET_MAX            0xf
  82 #define FMC2_BXTR_ADDHLD_MAX            0xf
  83 #define FMC2_BXTR_DATAST_MAX            0xff
  84 #define FMC2_BXTR_BUSTURN_MAX           0xf
  85 #define FMC2_BXTR_DATAHLD_MAX           0x3
  86 #define FMC2_BTR_CLKDIV_MAX             0xf
  87 #define FMC2_BTR_DATLAT_MAX             0xf
  88 #define FMC2_PCSCNTR_CSCOUNT_MAX        0xff
  89
  90 #define FMC2_NSEC_PER_SEC               1000000000L
  91
  92 enum stm32_fmc2_ebi_bank {
  93         FMC2_EBI1 = 0,
  94         FMC2_EBI2,
  95         FMC2_EBI3,
  96         FMC2_EBI4,
  97         FMC2_NAND
  98 };
  99
 100 enum stm32_fmc2_ebi_register_type {
 101         FMC2_REG_BCR = 1,
 102         FMC2_REG_BTR,
 103         FMC2_REG_BWTR,
 104         FMC2_REG_PCSCNTR
 105 };
 106
 107 enum stm32_fmc2_ebi_transaction_type {
 108         FMC2_ASYNC_MODE_1_SRAM = 0,
 109         FMC2_ASYNC_MODE_1_PSRAM,
 110         FMC2_ASYNC_MODE_A_SRAM,
 111         FMC2_ASYNC_MODE_A_PSRAM,
 112         FMC2_ASYNC_MODE_2_NOR,
 113         FMC2_ASYNC_MODE_B_NOR,
 114         FMC2_ASYNC_MODE_C_NOR,
 115         FMC2_ASYNC_MODE_D_NOR,
 116         FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
 117         FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
 118         FMC2_SYNC_READ_SYNC_WRITE_NOR,
 119         FMC2_SYNC_READ_ASYNC_WRITE_NOR
 120 };
 121
 122 enum stm32_fmc2_ebi_buswidth {
 123         FMC2_BUSWIDTH_8 = 8,
 124         FMC2_BUSWIDTH_16 = 16
 125 };
 126
 127 enum stm32_fmc2_ebi_cpsize {
 128         FMC2_CPSIZE_0 = 0,
 129         FMC2_CPSIZE_128 = 128,
 130         FMC2_CPSIZE_256 = 256,
 131         FMC2_CPSIZE_512 = 512,
 132         FMC2_CPSIZE_1024 = 1024
 133 };
 134
 135 struct stm32_fmc2_ebi {
 136         struct clk clk;
 137         fdt_addr_t io_base;
 138         u8 bank_assigned;
 139 };
 140
 141 /*
 142  * struct stm32_fmc2_prop - STM32 FMC2 EBI property
 143  * @name: the device tree binding name of the property
 144  * @bprop: indicate that it is a boolean property
 145  * @mprop: indicate that it is a mandatory property
 146  * @reg_type: the register that have to be modified
 147  * @reg_mask: the bit that have to be modified in the selected register
 148  *            in case of it is a boolean property
 149  * @reset_val: the default value that have to be set in case the property
 150  *             has not been defined in the device tree
 151  * @check: this callback ckecks that the property is compliant with the
 152  *         transaction type selected
 153  * @calculate: this callback is called to calculate for exemple a timing
 154  *             set in nanoseconds in the device tree in clock cycles or in
 155  *             clock period
 156  * @set: this callback applies the values in the registers
 157  */
 158 struct stm32_fmc2_prop {
 159         const char *name;
 160         bool bprop;
 161         bool mprop;
 162         int reg_type;
 163         u32 reg_mask;
 164         u32 reset_val;
 165         int (*check)(struct stm32_fmc2_ebi *ebi,
 166                      const struct stm32_fmc2_prop *prop, int cs);
 167         u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
 168         int (*set)(struct stm32_fmc2_ebi *ebi,
 169                    const struct stm32_fmc2_prop *prop,
 170                    int cs, u32 setup);
 171 };
 172
 173 static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
 174                                     const struct stm32_fmc2_prop *prop,
 175                                     int cs)
 176 {
 177         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 178
 179         if (bcr & FMC2_BCR_MTYP)
 180                 return 0;
 181
 182         return -EINVAL;
 183 }
 184
 185 static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
 186                                         const struct stm32_fmc2_prop *prop,
 187                                         int cs)
 188 {
 189         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 190         u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 191
 192         if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
 193                 return 0;
 194
 195         return -EINVAL;
 196 }
 197
 198 static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
 199                                            const struct stm32_fmc2_prop *prop,
 200                                            int cs)
 201 {
 202         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 203
 204         if (bcr & FMC2_BCR_BURSTEN)
 205                 return 0;
 206
 207         return -EINVAL;
 208 }
 209
 210 static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
 211                                             const struct stm32_fmc2_prop *prop,
 212                                             int cs)
 213 {
 214         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 215
 216         if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
 217                 return 0;
 218
 219         return -EINVAL;
 220 }
 221
 222 static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
 223                                        const struct stm32_fmc2_prop *prop,
 224                                        int cs)
 225 {
 226         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 227         u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 228
 229         if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
 230                 return 0;
 231
 232         return -EINVAL;
 233 }
 234
 235 static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
 236                                              const struct stm32_fmc2_prop *prop,
 237                                              int cs)
 238 {
 239         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 240         u32 bxtr = prop->reg_type == FMC2_REG_BWTR ?
 241                    readl(ebi->io_base + FMC2_BWTR(cs)) :
 242                    readl(ebi->io_base + FMC2_BTR(cs));
 243         u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 244
 245         if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
 246             ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
 247                 return 0;
 248
 249         return -EINVAL;
 250 }
 251
 252 static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
 253                                            const struct stm32_fmc2_prop *prop,
 254                                            int cs)
 255 {
 256         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 257         u32 bcr1 = cs ? readl(ebi->io_base + FMC2_BCR1) : bcr;
 258
 259         if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
 260                 return 0;
 261
 262         return -EINVAL;
 263 }
 264
 265 static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
 266                                      const struct stm32_fmc2_prop *prop,
 267                                      int cs)
 268 {
 269         if (cs)
 270                 return -EINVAL;
 271
 272         return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
 273 }
 274
 275 static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
 276                                              int cs, u32 setup)
 277 {
 278         unsigned long hclk = clk_get_rate(&ebi->clk);
 279         unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
 280
 281         return DIV_ROUND_UP(setup * 1000, hclkp);
 282 }
 283
 284 static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
 285                                            int cs, u32 setup)
 286 {
 287         u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
 288         u32 bcr = readl(ebi->io_base + FMC2_BCR1);
 289         u32 btr = bcr & FMC2_BCR1_CCLKEN || !cs ?
 290                   readl(ebi->io_base + FMC2_BTR1) :
 291                   readl(ebi->io_base + FMC2_BTR(cs));
 292         u32 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
 293
 294         return DIV_ROUND_UP(nb_clk_cycles, clk_period);
 295 }
 296
 297 static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
 298 {
 299         switch (reg_type) {
 300         case FMC2_REG_BCR:
 301                 *reg = FMC2_BCR(cs);
 302                 break;
 303         case FMC2_REG_BTR:
 304                 *reg = FMC2_BTR(cs);
 305                 break;
 306         case FMC2_REG_BWTR:
 307                 *reg = FMC2_BWTR(cs);
 308                 break;
 309         case FMC2_REG_PCSCNTR:
 310                 *reg = FMC2_PCSCNTR;
 311                 break;
 312         default:
 313                 return -EINVAL;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
 320                                         const struct stm32_fmc2_prop *prop,
 321                                         int cs, u32 setup)
 322 {
 323         u32 reg;
 324         int ret;
 325
 326         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 327         if (ret)
 328                 return ret;
 329
 330         clrsetbits_le32(ebi->io_base + reg, prop->reg_mask,
 331                         setup ? prop->reg_mask : 0);
 332
 333         return 0;
 334 }
 335
 336 static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
 337                                          const struct stm32_fmc2_prop *prop,
 338                                          int cs, u32 setup)
 339 {
 340         u32 bcr_mask, bcr = FMC2_BCR_WREN;
 341         u32 btr_mask, btr = 0;
 342         u32 bwtr_mask, bwtr = 0;
 343
 344         bwtr_mask = FMC2_BXTR_ACCMOD;
 345         btr_mask = FMC2_BXTR_ACCMOD;
 346         bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
 347                    FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
 348                    FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
 349
 350         switch (setup) {
 351         case FMC2_ASYNC_MODE_1_SRAM:
 352                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
 353                 /*
 354                  * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 355                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 356                  */
 357                 break;
 358         case FMC2_ASYNC_MODE_1_PSRAM:
 359                 /*
 360                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 361                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 362                  */
 363                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 364                 break;
 365         case FMC2_ASYNC_MODE_A_SRAM:
 366                 /*
 367                  * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 368                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
 369                  */
 370                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
 371                 bcr |= FMC2_BCR_EXTMOD;
 372                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 373                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 374                 break;
 375         case FMC2_ASYNC_MODE_A_PSRAM:
 376                 /*
 377                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 378                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
 379                  */
 380                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 381                 bcr |= FMC2_BCR_EXTMOD;
 382                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 383                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 384                 break;
 385         case FMC2_ASYNC_MODE_2_NOR:
 386                 /*
 387                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 388                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 389                  */
 390                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 391                 bcr |= FMC2_BCR_FACCEN;
 392                 break;
 393         case FMC2_ASYNC_MODE_B_NOR:
 394                 /*
 395                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 396                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
 397                  */
 398                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 399                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 400                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
 401                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
 402                 break;
 403         case FMC2_ASYNC_MODE_C_NOR:
 404                 /*
 405                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 406                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
 407                  */
 408                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 409                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 410                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
 411                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
 412                 break;
 413         case FMC2_ASYNC_MODE_D_NOR:
 414                 /*
 415                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 416                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
 417                  */
 418                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 419                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 420                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 421                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 422                 break;
 423         case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
 424                 /*
 425                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
 426                  * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
 427                  */
 428                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 429                 bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
 430                 break;
 431         case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
 432                 /*
 433                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
 434                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 435                  */
 436                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 437                 bcr |= FMC2_BCR_BURSTEN;
 438                 break;
 439         case FMC2_SYNC_READ_SYNC_WRITE_NOR:
 440                 /*
 441                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
 442                  * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
 443                  */
 444                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 445                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
 446                 break;
 447         case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
 448                 /*
 449                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
 450                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 451                  */
 452                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 453                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
 454                 break;
 455         default:
 456                 /* Type of transaction not supported */
 457                 return -EINVAL;
 458         }
 459
 460         if (bcr & FMC2_BCR_EXTMOD)
 461                 clrsetbits_le32(ebi->io_base + FMC2_BWTR(cs),
 462                                 bwtr_mask, bwtr);
 463         clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), btr_mask, btr);
 464         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), bcr_mask, bcr);
 465
 466         return 0;
 467 }
 468
 469 static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
 470                                        const struct stm32_fmc2_prop *prop,
 471                                        int cs, u32 setup)
 472 {
 473         u32 val;
 474
 475         switch (setup) {
 476         case FMC2_BUSWIDTH_8:
 477                 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
 478                 break;
 479         case FMC2_BUSWIDTH_16:
 480                 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
 481                 break;
 482         default:
 483                 /* Buswidth not supported */
 484                 return -EINVAL;
 485         }
 486
 487         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MWID, val);
 488
 489         return 0;
 490 }
 491
 492 static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
 493                                      const struct stm32_fmc2_prop *prop,
 494                                      int cs, u32 setup)
 495 {
 496         u32 val;
 497
 498         switch (setup) {
 499         case FMC2_CPSIZE_0:
 500                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
 501                 break;
 502         case FMC2_CPSIZE_128:
 503                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
 504                 break;
 505         case FMC2_CPSIZE_256:
 506                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
 507                 break;
 508         case FMC2_CPSIZE_512:
 509                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
 510                 break;
 511         case FMC2_CPSIZE_1024:
 512                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
 513                 break;
 514         default:
 515                 /* Cpsize not supported */
 516                 return -EINVAL;
 517         }
 518
 519         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
 520
 521         return 0;
 522 }
 523
 524 static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
 525                                        const struct stm32_fmc2_prop *prop,
 526                                        int cs, u32 setup)
 527 {
 528         u32 val;
 529
 530         val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
 531         val = FIELD_PREP(FMC2_BCR_NBLSET, val);
 532         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
 533
 534         return 0;
 535 }
 536
 537 static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
 538                                             const struct stm32_fmc2_prop *prop,
 539                                             int cs, u32 setup)
 540 {
 541         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 542         u32 bxtr = prop->reg_type == FMC2_REG_BWTR ?
 543                    readl(ebi->io_base + FMC2_BWTR(cs)) :
 544                    readl(ebi->io_base + FMC2_BTR(cs));
 545         u32 reg, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 546         int ret;
 547
 548         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 549         if (ret)
 550                 return ret;
 551
 552         if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
 553                 val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
 554         else
 555                 val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
 556         val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
 557         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDSET, val);
 558
 559         return 0;
 560 }
 561
 562 static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
 563                                            const struct stm32_fmc2_prop *prop,
 564                                            int cs, u32 setup)
 565 {
 566         u32 val, reg;
 567         int ret;
 568
 569         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 570         if (ret)
 571                 return ret;
 572
 573         val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
 574         val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
 575         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDHLD, val);
 576
 577         return 0;
 578 }
 579
 580 static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
 581                                          const struct stm32_fmc2_prop *prop,
 582                                          int cs, u32 setup)
 583 {
 584         u32 val, reg;
 585         int ret;
 586
 587         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 588         if (ret)
 589                 return ret;
 590
 591         val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
 592         val = FIELD_PREP(FMC2_BXTR_DATAST, val);
 593         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAST, val);
 594
 595         return 0;
 596 }
 597
 598 static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
 599                                              const struct stm32_fmc2_prop *prop,
 600                                              int cs, u32 setup)
 601 {
 602         u32 val, reg;
 603         int ret;
 604
 605         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 606         if (ret)
 607                 return ret;
 608
 609         val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
 610         val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
 611         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_BUSTURN, val);
 612
 613         return 0;
 614 }
 615
 616 static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
 617                                         const struct stm32_fmc2_prop *prop,
 618                                         int cs, u32 setup)
 619 {
 620         u32 val, reg;
 621         int ret;
 622
 623         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 624         if (ret)
 625                 return ret;
 626
 627         if (prop->reg_type == FMC2_REG_BWTR)
 628                 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
 629         else
 630                 val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
 631         val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
 632         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAHLD, val);
 633
 634         return 0;
 635 }
 636
 637 static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
 638                                          const struct stm32_fmc2_prop *prop,
 639                                          int cs, u32 setup)
 640 {
 641         u32 val;
 642
 643         val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
 644         val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
 645         clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
 646
 647         return 0;
 648 }
 649
 650 static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
 651                                            const struct stm32_fmc2_prop *prop,
 652                                            int cs, u32 setup)
 653 {
 654         u32 val;
 655
 656         val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
 657         val = FIELD_PREP(FMC2_BTR_DATLAT, val);
 658         clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
 659
 660         return 0;
 661 }
 662
 663 static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
 664                                             const struct stm32_fmc2_prop *prop,
 665                                             int cs, u32 setup)
 666 {
 667         u32 old_val, new_val, pcscntr;
 668
 669         if (setup < 1)
 670                 return 0;
 671
 672         pcscntr = readl(ebi->io_base + FMC2_PCSCNTR);
 673
 674         /* Enable counter for the bank */
 675         setbits_le32(ebi->io_base + FMC2_PCSCNTR, FMC2_PCSCNTR_CNTBEN(cs));
 676
 677         new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
 678         old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
 679         if (old_val && new_val > old_val)
 680                 /* Keep current counter value */
 681                 return 0;
 682
 683         new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
 684         clrsetbits_le32(ebi->io_base + FMC2_PCSCNTR,
 685                         FMC2_PCSCNTR_CSCOUNT, new_val);
 686
 687         return 0;
 688 }
 689
 690 static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
 691         /* st,fmc2-ebi-cs-trans-type must be the first property */
 692         {
 693                 .name = "st,fmc2-ebi-cs-transaction-type",
 694                 .mprop = true,
 695                 .set = stm32_fmc2_ebi_set_trans_type,
 696         },
 697         {
 698                 .name = "st,fmc2-ebi-cs-cclk-enable",
 699                 .bprop = true,
 700                 .reg_type = FMC2_REG_BCR,
 701                 .reg_mask = FMC2_BCR1_CCLKEN,
 702                 .check = stm32_fmc2_ebi_check_cclk,
 703                 .set = stm32_fmc2_ebi_set_bit_field,
 704         },
 705         {
 706                 .name = "st,fmc2-ebi-cs-mux-enable",
 707                 .bprop = true,
 708                 .reg_type = FMC2_REG_BCR,
 709                 .reg_mask = FMC2_BCR_MUXEN,
 710                 .check = stm32_fmc2_ebi_check_mux,
 711                 .set = stm32_fmc2_ebi_set_bit_field,
 712         },
 713         {
 714                 .name = "st,fmc2-ebi-cs-buswidth",
 715                 .reset_val = FMC2_BUSWIDTH_16,
 716                 .set = stm32_fmc2_ebi_set_buswidth,
 717         },
 718         {
 719                 .name = "st,fmc2-ebi-cs-waitpol-high",
 720                 .bprop = true,
 721                 .reg_type = FMC2_REG_BCR,
 722                 .reg_mask = FMC2_BCR_WAITPOL,
 723                 .set = stm32_fmc2_ebi_set_bit_field,
 724         },
 725         {
 726                 .name = "st,fmc2-ebi-cs-waitcfg-enable",
 727                 .bprop = true,
 728                 .reg_type = FMC2_REG_BCR,
 729                 .reg_mask = FMC2_BCR_WAITCFG,
 730                 .check = stm32_fmc2_ebi_check_waitcfg,
 731                 .set = stm32_fmc2_ebi_set_bit_field,
 732         },
 733         {
 734                 .name = "st,fmc2-ebi-cs-wait-enable",
 735                 .bprop = true,
 736                 .reg_type = FMC2_REG_BCR,
 737                 .reg_mask = FMC2_BCR_WAITEN,
 738                 .check = stm32_fmc2_ebi_check_sync_trans,
 739                 .set = stm32_fmc2_ebi_set_bit_field,
 740         },
 741         {
 742                 .name = "st,fmc2-ebi-cs-asyncwait-enable",
 743                 .bprop = true,
 744                 .reg_type = FMC2_REG_BCR,
 745                 .reg_mask = FMC2_BCR_ASYNCWAIT,
 746                 .check = stm32_fmc2_ebi_check_async_trans,
 747                 .set = stm32_fmc2_ebi_set_bit_field,
 748         },
 749         {
 750                 .name = "st,fmc2-ebi-cs-cpsize",
 751                 .check = stm32_fmc2_ebi_check_cpsize,
 752                 .set = stm32_fmc2_ebi_set_cpsize,
 753         },
 754         {
 755                 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
 756                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 757                 .set = stm32_fmc2_ebi_set_bl_setup,
 758         },
 759         {
 760                 .name = "st,fmc2-ebi-cs-address-setup-ns",
 761                 .reg_type = FMC2_REG_BTR,
 762                 .reset_val = FMC2_BXTR_ADDSET_MAX,
 763                 .check = stm32_fmc2_ebi_check_async_trans,
 764                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 765                 .set = stm32_fmc2_ebi_set_address_setup,
 766         },
 767         {
 768                 .name = "st,fmc2-ebi-cs-address-hold-ns",
 769                 .reg_type = FMC2_REG_BTR,
 770                 .reset_val = FMC2_BXTR_ADDHLD_MAX,
 771                 .check = stm32_fmc2_ebi_check_address_hold,
 772                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 773                 .set = stm32_fmc2_ebi_set_address_hold,
 774         },
 775         {
 776                 .name = "st,fmc2-ebi-cs-data-setup-ns",
 777                 .reg_type = FMC2_REG_BTR,
 778                 .reset_val = FMC2_BXTR_DATAST_MAX,
 779                 .check = stm32_fmc2_ebi_check_async_trans,
 780                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 781                 .set = stm32_fmc2_ebi_set_data_setup,
 782         },
 783         {
 784                 .name = "st,fmc2-ebi-cs-bus-turnaround-ns",
 785                 .reg_type = FMC2_REG_BTR,
 786                 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
 787                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 788                 .set = stm32_fmc2_ebi_set_bus_turnaround,
 789         },
 790         {
 791                 .name = "st,fmc2-ebi-cs-data-hold-ns",
 792                 .reg_type = FMC2_REG_BTR,
 793                 .check = stm32_fmc2_ebi_check_async_trans,
 794                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 795                 .set = stm32_fmc2_ebi_set_data_hold,
 796         },
 797         {
 798                 .name = "st,fmc2-ebi-cs-clk-period-ns",
 799                 .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
 800                 .check = stm32_fmc2_ebi_check_clk_period,
 801                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 802                 .set = stm32_fmc2_ebi_set_clk_period,
 803         },
 804         {
 805                 .name = "st,fmc2-ebi-cs-data-latency-ns",
 806                 .check = stm32_fmc2_ebi_check_sync_trans,
 807                 .calculate = stm32_fmc2_ebi_ns_to_clk_period,
 808                 .set = stm32_fmc2_ebi_set_data_latency,
 809         },
 810         {
 811                 .name = "st,fmc2-ebi-cs-write-address-setup-ns",
 812                 .reg_type = FMC2_REG_BWTR,
 813                 .reset_val = FMC2_BXTR_ADDSET_MAX,
 814                 .check = stm32_fmc2_ebi_check_async_trans,
 815                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 816                 .set = stm32_fmc2_ebi_set_address_setup,
 817         },
 818         {
 819                 .name = "st,fmc2-ebi-cs-write-address-hold-ns",
 820                 .reg_type = FMC2_REG_BWTR,
 821                 .reset_val = FMC2_BXTR_ADDHLD_MAX,
 822                 .check = stm32_fmc2_ebi_check_address_hold,
 823                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 824                 .set = stm32_fmc2_ebi_set_address_hold,
 825         },
 826         {
 827                 .name = "st,fmc2-ebi-cs-write-data-setup-ns",
 828                 .reg_type = FMC2_REG_BWTR,
 829                 .reset_val = FMC2_BXTR_DATAST_MAX,
 830                 .check = stm32_fmc2_ebi_check_async_trans,
 831                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 832                 .set = stm32_fmc2_ebi_set_data_setup,
 833         },
 834         {
 835                 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
 836                 .reg_type = FMC2_REG_BWTR,
 837                 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
 838                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 839                 .set = stm32_fmc2_ebi_set_bus_turnaround,
 840         },
 841         {
 842                 .name = "st,fmc2-ebi-cs-write-data-hold-ns",
 843                 .reg_type = FMC2_REG_BWTR,
 844                 .check = stm32_fmc2_ebi_check_async_trans,
 845                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 846                 .set = stm32_fmc2_ebi_set_data_hold,
 847         },
 848         {
 849                 .name = "st,fmc2-ebi-cs-max-low-pulse-ns",
 850                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 851                 .set = stm32_fmc2_ebi_set_max_low_pulse,
 852         },
 853 };
 854
 855 static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
 856                                      ofnode node,
 857                                      const struct stm32_fmc2_prop *prop,
 858                                      int cs)
 859 {
 860         u32 setup = 0;
 861
 862         if (!prop->set) {
 863                 pr_err("property %s is not well defined\n", prop->name);
 864                 return -EINVAL;
 865         }
 866
 867         if (prop->check && prop->check(ebi, prop, cs))
 868                 /* Skip this property */
 869                 return 0;
 870
 871         if (prop->bprop) {
 872                 bool bprop;
 873
 874                 bprop = ofnode_read_bool(node, prop->name);
 875                 if (prop->mprop && !bprop) {
 876                         pr_err("mandatory property %s not defined in the device tree\n",
 877                                prop->name);
 878                         return -EINVAL;
 879                 }
 880
 881                 if (bprop)
 882                         setup = 1;
 883         } else {
 884                 u32 val;
 885                 int ret;
 886
 887                 ret = ofnode_read_u32(node, prop->name, &val);
 888                 if (prop->mprop && ret) {
 889                         pr_err("mandatory property %s not defined in the device tree\n",
 890                                prop->name);
 891                         return ret;
 892                 }
 893
 894                 if (ret)
 895                         setup = prop->reset_val;
 896                 else if (prop->calculate)
 897                         setup = prop->calculate(ebi, cs, val);
 898                 else
 899                         setup = val;
 900         }
 901
 902         return prop->set(ebi, prop, cs, setup);
 903 }
 904
 905 static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
 906 {
 907         setbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN);
 908 }
 909
 910 static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
 911 {
 912         clrbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN);
 913 }
 914
 915 /* NWAIT signal can not be connected to EBI controller and NAND controller */
 916 static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
 917 {
 918         unsigned int cs;
 919         u32 bcr;
 920
 921         for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
 922                 if (!(ebi->bank_assigned & BIT(cs)))
 923                         continue;
 924
 925                 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 926                 if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
 927                     ebi->bank_assigned & BIT(FMC2_NAND))
 928                         return true;
 929         }
 930
 931         return false;
 932 }
 933
 934 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
 935 {
 936         setbits_le32(ebi->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN);
 937 }
 938
 939 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
 940                                    ofnode node, u32 cs)
 941 {
 942         unsigned int i;
 943         int ret;
 944
 945         stm32_fmc2_ebi_disable_bank(ebi, cs);
 946
 947         for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
 948                 const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
 949
 950                 ret = stm32_fmc2_ebi_parse_prop(ebi, node, p, cs);
 951                 if (ret) {
 952                         pr_err("property %s could not be set: %d\n",
 953                                p->name, ret);
 954                         return ret;
 955                 }
 956         }
 957
 958         stm32_fmc2_ebi_enable_bank(ebi, cs);
 959
 960         return 0;
 961 }
 962
 963 static int stm32_fmc2_ebi_parse_dt(struct udevice *dev,
 964                                    struct stm32_fmc2_ebi *ebi)
 965 {
 966         ofnode child;
 967         bool child_found = false;
 968         u32 bank;
 969         int ret;
 970
 971         dev_for_each_subnode(child, dev) {
 972                 ret = ofnode_read_u32(child, "reg", &bank);
 973                 if (ret) {
 974                         pr_err("could not retrieve reg property: %d\n", ret);
 975                         return ret;
 976                 }
 977
 978                 if (bank >= FMC2_MAX_BANKS) {
 979                         pr_err("invalid reg value: %d\n", bank);
 980                         return -EINVAL;
 981                 }
 982
 983                 if (ebi->bank_assigned & BIT(bank)) {
 984                         pr_err("bank already assigned: %d\n", bank);
 985                         return -EINVAL;
 986                 }
 987
 988                 if (bank < FMC2_MAX_EBI_CE) {
 989                         ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
 990                         if (ret) {
 991                                 pr_err("setup chip select %d failed: %d\n",
 992                                        bank, ret);
 993                                 return ret;
 994                         }
 995                 }
 996
 997                 ebi->bank_assigned |= BIT(bank);
 998                 child_found = true;
 999         }
1000
1001         if (!child_found) {
1002                 pr_warn("no subnodes found, disable the driver.\n");
1003                 return -ENODEV;
1004         }
1005
1006         if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
1007                 pr_err("NWAIT signal connected to EBI and NAND controllers\n");
1008                 return -EINVAL;
1009         }
1010
1011         stm32_fmc2_ebi_enable(ebi);
1012
1013         return 0;
1014 }
1015
1016 static int stm32_fmc2_ebi_probe(struct udevice *dev)
1017 {
1018         struct stm32_fmc2_ebi *ebi = dev_get_priv(dev);
1019         struct reset_ctl reset;
1020         int ret;
1021
1022         ebi->io_base = dev_read_addr(dev);
1023         if (ebi->io_base == FDT_ADDR_T_NONE)
1024                 return -EINVAL;
1025
1026         ret = clk_get_by_index(dev, 0, &ebi->clk);
1027         if (ret)
1028                 return ret;
1029
1030         ret = clk_enable(&ebi->clk);
1031         if (ret)
1032                 return ret;
1033
1034         ret = reset_get_by_index(dev, 0, &reset);
1035         if (!ret) {
1036                 reset_assert(&reset);
1037                 udelay(2);
1038                 reset_deassert(&reset);
1039         }
1040
1041         return stm32_fmc2_ebi_parse_dt(dev, ebi);
1042 }
1043
1044 static const struct udevice_id stm32_fmc2_ebi_match[] = {
1045         {.compatible = "st,stm32mp1-fmc2-ebi"},
1046         { /* Sentinel */ }
1047 };
1048
1049 U_BOOT_DRIVER(stm32_fmc2_ebi) = {
1050         .name = "stm32_fmc2_ebi",
1051         .id = UCLASS_NOP,
1052         .of_match = stm32_fmc2_ebi_match,
1053         .probe = stm32_fmc2_ebi_probe,
1054         .priv_auto_alloc_size = sizeof(struct stm32_fmc2_ebi),
1055         .bind = dm_scan_fdt_dev,
1056 };