board/toradex/colibri_imx6/colibri_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <[email protected]>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <env.h>
  13 #include <init.h>
  14
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/imx-regs.h>
  18 #include <asm/arch/mx6-ddr.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/mxc_hdmi.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/bootm.h>
  23 #include <asm/gpio.h>
  24 #include <asm/mach-imx/boot_mode.h>
  25 #include <asm/mach-imx/iomux-v3.h>
  26 #include <asm/mach-imx/sata.h>
  27 #include <asm/mach-imx/video.h>
  28 #include <cpu.h>
  29 #include <dm/platform_data/serial_mxc.h>
  30 #include <fsl_esdhc_imx.h>
  31 #include <imx_thermal.h>
  32 #include <miiphy.h>
  33 #include <netdev.h>
  34 #include <cpu.h>
  35
  36 #include "../common/tdx-cfg-block.h"
  37 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  38 #include "pf0100.h"
  39 #endif
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  45         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  46
  47 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  48         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  49         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  50
  51 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  52         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  53         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  54
  55 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  57         PAD_CTL_SRE_SLOW)
  58
  59 #define NO_PULLUP       (                                       \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_SRE_SLOW)
  62
  63 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  65         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  66
  67 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  68
  69 int dram_init(void)
  70 {
  71         /* use the DDR controllers configured size */
  72         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  73                                     (ulong)imx_ddr_size());
  74
  75         return 0;
  76 }
  77
  78 /* Colibri UARTA */
  79 iomux_v3_cfg_t const uart1_pads[] = {
  80         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  82 };
  83
  84 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  85 /* Colibri MMC */
  86 iomux_v3_cfg_t const usdhc1_pads[] = {
  87         MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  94 #       define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  95 };
  96
  97 /* eMMC */
  98 iomux_v3_cfg_t const usdhc3_pads[] = {
  99         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 100         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 101         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 102         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 103         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 104         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 105         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 106         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 107         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 108         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 109         MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110 };
 111 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 112
 113 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 114 iomux_v3_cfg_t const gpio_pads[] = {
 115         /* ADDRESS[17:18] [25] used as GPIO */
 116         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 117                                           MUX_MODE_SION,
 118         MX6_PAD_KEY_COL2__GPIO4_IO10    | MUX_PAD_CTRL(WEAK_PULLUP) |
 119                                           MUX_MODE_SION,
 120         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(WEAK_PULLUP) |
 121                                           MUX_MODE_SION,
 122         /* ADDRESS[19:24] used as GPIO */
 123         MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
 124                                           MUX_MODE_SION,
 125         MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
 126                                           MUX_MODE_SION,
 127         MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
 128                                           MUX_MODE_SION,
 129         MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
 130                                           MUX_MODE_SION,
 131         MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
 132                                           MUX_MODE_SION,
 133         MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
 134                                           MUX_MODE_SION,
 135         /* DATA[16:29] [31]      used as GPIO */
 136         MX6_PAD_EIM_LBA__GPIO2_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 137                                           MUX_MODE_SION,
 138         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(WEAK_PULLUP) |
 139                                           MUX_MODE_SION,
 140         MX6_PAD_NANDF_CS3__GPIO6_IO16   | MUX_PAD_CTRL(WEAK_PULLUP) |
 141                                           MUX_MODE_SION,
 142         MX6_PAD_NANDF_CS1__GPIO6_IO14   | MUX_PAD_CTRL(WEAK_PULLUP) |
 143                                           MUX_MODE_SION,
 144         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 145                                           MUX_MODE_SION,
 146         MX6_PAD_NANDF_ALE__GPIO6_IO08   | MUX_PAD_CTRL(WEAK_PULLUP) |
 147                                           MUX_MODE_SION,
 148         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 149                                           MUX_MODE_SION,
 150         MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(WEAK_PULLUP) |
 151                                           MUX_MODE_SION,
 152         MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(WEAK_PULLUP) |
 153                                           MUX_MODE_SION,
 154         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(WEAK_PULLUP) |
 155                                           MUX_MODE_SION,
 156         MX6_PAD_CSI0_MCLK__GPIO5_IO19   | MUX_PAD_CTRL(WEAK_PULLUP) |
 157                                           MUX_MODE_SION,
 158         MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
 159                                           MUX_MODE_SION,
 160         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 161                                           MUX_MODE_SION,
 162         MX6_PAD_GPIO_5__GPIO1_IO05      | MUX_PAD_CTRL(WEAK_PULLUP) |
 163                                           MUX_MODE_SION,
 164         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLUP) |
 165                                           MUX_MODE_SION,
 166         /* DQM[0:3]      used as GPIO */
 167         MX6_PAD_EIM_EB0__GPIO2_IO28     | MUX_PAD_CTRL(WEAK_PULLUP) |
 168                                           MUX_MODE_SION,
 169         MX6_PAD_EIM_EB1__GPIO2_IO29     | MUX_PAD_CTRL(WEAK_PULLUP) |
 170                                           MUX_MODE_SION,
 171         MX6_PAD_SD2_DAT2__GPIO1_IO13    | MUX_PAD_CTRL(WEAK_PULLUP) |
 172                                           MUX_MODE_SION,
 173         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 174                                           MUX_MODE_SION,
 175         /* RDY  used as GPIO */
 176         MX6_PAD_EIM_WAIT__GPIO5_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 177                                           MUX_MODE_SION,
 178         /* ADDRESS[16] DATA[30]  used as GPIO */
 179         MX6_PAD_KEY_ROW4__GPIO4_IO15    | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 180                                           MUX_MODE_SION,
 181         MX6_PAD_KEY_COL4__GPIO4_IO14    | MUX_PAD_CTRL(WEAK_PULLUP) |
 182                                           MUX_MODE_SION,
 183         /* CSI pins used as GPIO */
 184         MX6_PAD_EIM_A24__GPIO5_IO04     | MUX_PAD_CTRL(WEAK_PULLUP) |
 185                                           MUX_MODE_SION,
 186         MX6_PAD_SD2_CMD__GPIO1_IO11     | MUX_PAD_CTRL(WEAK_PULLUP) |
 187                                           MUX_MODE_SION,
 188         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(WEAK_PULLUP) |
 189                                           MUX_MODE_SION,
 190         MX6_PAD_EIM_D18__GPIO3_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 191                                           MUX_MODE_SION,
 192         MX6_PAD_EIM_A19__GPIO2_IO19     | MUX_PAD_CTRL(WEAK_PULLUP) |
 193                                           MUX_MODE_SION,
 194         MX6_PAD_EIM_D29__GPIO3_IO29     | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 195                                           MUX_MODE_SION,
 196         MX6_PAD_EIM_A23__GPIO6_IO06     | MUX_PAD_CTRL(WEAK_PULLUP) |
 197                                           MUX_MODE_SION,
 198         MX6_PAD_EIM_A20__GPIO2_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 199                                           MUX_MODE_SION,
 200         MX6_PAD_EIM_A17__GPIO2_IO21     | MUX_PAD_CTRL(WEAK_PULLUP) |
 201                                           MUX_MODE_SION,
 202         MX6_PAD_EIM_A18__GPIO2_IO20     | MUX_PAD_CTRL(WEAK_PULLUP) |
 203                                           MUX_MODE_SION,
 204         MX6_PAD_EIM_EB3__GPIO2_IO31     | MUX_PAD_CTRL(WEAK_PULLUP) |
 205                                           MUX_MODE_SION,
 206         MX6_PAD_EIM_D17__GPIO3_IO17     | MUX_PAD_CTRL(WEAK_PULLUP) |
 207                                           MUX_MODE_SION,
 208         MX6_PAD_SD2_DAT0__GPIO1_IO15    | MUX_PAD_CTRL(WEAK_PULLUP) |
 209                                           MUX_MODE_SION,
 210         /* GPIO */
 211         MX6_PAD_EIM_D26__GPIO3_IO26     | MUX_PAD_CTRL(WEAK_PULLUP) |
 212                                           MUX_MODE_SION,
 213         MX6_PAD_EIM_D27__GPIO3_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 214                                           MUX_MODE_SION,
 215         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 216                                           MUX_MODE_SION,
 217         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(WEAK_PULLUP) |
 218                                           MUX_MODE_SION,
 219         MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
 220                                           MUX_MODE_SION,
 221         MX6_PAD_DI0_PIN4__GPIO4_IO20    | MUX_PAD_CTRL(WEAK_PULLUP) |
 222                                           MUX_MODE_SION,
 223         MX6_PAD_SD4_DAT3__GPIO2_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 224                                           MUX_MODE_SION,
 225         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 226                                           MUX_MODE_SION,
 227         MX6_PAD_SD4_DAT0__GPIO2_IO08    | MUX_PAD_CTRL(WEAK_PULLUP) |
 228                                           MUX_MODE_SION,
 229         MX6_PAD_GPIO_7__GPIO1_IO07      | MUX_PAD_CTRL(WEAK_PULLUP) |
 230                                           MUX_MODE_SION,
 231         MX6_PAD_GPIO_8__GPIO1_IO08      | MUX_PAD_CTRL(WEAK_PULLUP) |
 232                                           MUX_MODE_SION,
 233         /* USBH_OC */
 234         MX6_PAD_EIM_D30__GPIO3_IO30     | MUX_PAD_CTRL(WEAK_PULLUP),
 235         /* USBC_ID */
 236         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(WEAK_PULLUP),
 237         /* USBC_DET */
 238         MX6_PAD_GPIO_17__GPIO7_IO12     | MUX_PAD_CTRL(WEAK_PULLUP),
 239 };
 240
 241 static void setup_iomux_gpio(void)
 242 {
 243         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 244 }
 245
 246 iomux_v3_cfg_t const usb_pads[] = {
 247         /* USBH_PEN */
 248         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 249 #       define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
 250 };
 251
 252 /*
 253  * UARTs are used in DTE mode, switch the mode on all UARTs before
 254  * any pinmuxing connects a (DCE) output to a transceiver output.
 255  */
 256 #define UCR3            0x88    /* FIFO Control Register */
 257 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 258 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 259 #define UFCR            0x90    /* FIFO Control Register */
 260 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 261
 262 static void setup_dtemode_uart(void)
 263 {
 264         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 265         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 266         setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
 267
 268         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 269         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 270         clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
 271 }
 272
 273 static void setup_iomux_uart(void)
 274 {
 275         setup_dtemode_uart();
 276         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 277 }
 278
 279 #ifdef CONFIG_USB_EHCI_MX6
 280 int board_ehci_hcd_init(int port)
 281 {
 282         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 283         return 0;
 284 }
 285 #endif
 286
 287 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
 288 /* use the following sequence: eMMC, MMC */
 289 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 290         {USDHC3_BASE_ADDR},
 291         {USDHC1_BASE_ADDR},
 292 };
 293
 294 int board_mmc_getcd(struct mmc *mmc)
 295 {
 296         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 297         int ret = true; /* default: assume inserted */
 298
 299         switch (cfg->esdhc_base) {
 300         case USDHC1_BASE_ADDR:
 301                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 302                 gpio_direction_input(GPIO_MMC_CD);
 303                 ret = !gpio_get_value(GPIO_MMC_CD);
 304                 break;
 305         }
 306
 307         return ret;
 308 }
 309
 310 int board_mmc_init(bd_t *bis)
 311 {
 312         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 313         unsigned reg = readl(&psrc->sbmr1) >> 11;
 314         /*
 315          * Upon reading BOOT_CFG register the following map is done:
 316          * Bit 11 and 12 of BOOT_CFG register can determine the current
 317          * mmc port
 318          * 0x1                  SD1
 319          * 0x2                  SD2
 320          * 0x3                  SD4
 321          */
 322
 323         switch (reg & 0x3) {
 324         case 0x0:
 325                 imx_iomux_v3_setup_multiple_pads(
 326                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 327                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 328                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 329                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 330                 break;
 331         case 0x2:
 332                 imx_iomux_v3_setup_multiple_pads(
 333                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 334                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 335                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 336                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 337                 break;
 338         default:
 339                 puts("MMC boot device not available");
 340         }
 341
 342         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 343 }
 344 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 345
 346 int board_phy_config(struct phy_device *phydev)
 347 {
 348         if (phydev->drv->config)
 349                 phydev->drv->config(phydev);
 350
 351         return 0;
 352 }
 353
 354 int setup_fec(void)
 355 {
 356         int ret;
 357
 358         /* provide the PHY clock from the i.MX 6 */
 359         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 360         if (ret)
 361                 return ret;
 362
 363         return 0;
 364 }
 365
 366 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 367         /*
 368          * the bootrom sets the iomux to vselect, potentially connecting
 369          * two outputs. Set this back to GPIO
 370          */
 371         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 372 };
 373
 374 #if defined(CONFIG_VIDEO_IPUV3)
 375
 376 static iomux_v3_cfg_t const backlight_pads[] = {
 377         /* Backlight On */
 378         MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 379 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
 380         /* Backlight PWM, used as GPIO in U-Boot */
 381         MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
 382         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 383                                        MUX_MODE_SION,
 384 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
 385 };
 386
 387 static iomux_v3_cfg_t const rgb_pads[] = {
 388         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 389         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 390         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 391         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 392         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 393         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 394         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 395         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 396         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 397         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 398         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 399         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 400         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 401         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 402         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 403         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 404         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 405         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 406         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 407         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 408         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 409         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 410 };
 411
 412 static void do_enable_hdmi(struct display_info_t const *dev)
 413 {
 414         imx_enable_hdmi_phy();
 415 }
 416
 417 static void enable_rgb(struct display_info_t const *dev)
 418 {
 419         imx_iomux_v3_setup_multiple_pads(
 420                 rgb_pads,
 421                 ARRAY_SIZE(rgb_pads));
 422         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 423         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 424 }
 425
 426 static int detect_default(struct display_info_t const *dev)
 427 {
 428         (void) dev;
 429         return 1;
 430 }
 431
 432 struct display_info_t const displays[] = {{
 433         .bus    = -1,
 434         .addr   = 0,
 435         .pixfmt = IPU_PIX_FMT_RGB24,
 436         .detect = detect_hdmi,
 437         .enable = do_enable_hdmi,
 438         .mode   = {
 439                 .name           = "HDMI",
 440                 .refresh        = 60,
 441                 .xres           = 1024,
 442                 .yres           = 768,
 443                 .pixclock       = 15385,
 444                 .left_margin    = 220,
 445                 .right_margin   = 40,
 446                 .upper_margin   = 21,
 447                 .lower_margin   = 7,
 448                 .hsync_len      = 60,
 449                 .vsync_len      = 10,
 450                 .sync           = FB_SYNC_EXT,
 451                 .vmode          = FB_VMODE_NONINTERLACED
 452 } }, {
 453         .bus    = -1,
 454         .addr   = 0,
 455         .pixfmt = IPU_PIX_FMT_RGB666,
 456         .detect = detect_default,
 457         .enable = enable_rgb,
 458         .mode   = {
 459                 .name           = "vga-rgb",
 460                 .refresh        = 60,
 461                 .xres           = 640,
 462                 .yres           = 480,
 463                 .pixclock       = 33000,
 464                 .left_margin    = 48,
 465                 .right_margin   = 16,
 466                 .upper_margin   = 31,
 467                 .lower_margin   = 11,
 468                 .hsync_len      = 96,
 469                 .vsync_len      = 2,
 470                 .sync           = 0,
 471                 .vmode          = FB_VMODE_NONINTERLACED
 472 } }, {
 473         .bus    = -1,
 474         .addr   = 0,
 475         .pixfmt = IPU_PIX_FMT_RGB666,
 476         .enable = enable_rgb,
 477         .mode   = {
 478                 .name           = "wvga-rgb",
 479                 .refresh        = 60,
 480                 .xres           = 800,
 481                 .yres           = 480,
 482                 .pixclock       = 25000,
 483                 .left_margin    = 40,
 484                 .right_margin   = 88,
 485                 .upper_margin   = 33,
 486                 .lower_margin   = 10,
 487                 .hsync_len      = 128,
 488                 .vsync_len      = 2,
 489                 .sync           = 0,
 490                 .vmode          = FB_VMODE_NONINTERLACED
 491 } } };
 492 size_t display_count = ARRAY_SIZE(displays);
 493
 494 static void setup_display(void)
 495 {
 496         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 497         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 498         int reg;
 499
 500         enable_ipu_clock();
 501         imx_setup_hdmi();
 502         /* Turn on LDB0,IPU,IPU DI0 clocks */
 503         reg = __raw_readl(&mxc_ccm->CCGR3);
 504         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 505         writel(reg, &mxc_ccm->CCGR3);
 506
 507         /* set LDB0, LDB1 clk select to 011/011 */
 508         reg = readl(&mxc_ccm->cs2cdr);
 509         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 510                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 511         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 512               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 513         writel(reg, &mxc_ccm->cs2cdr);
 514
 515         reg = readl(&mxc_ccm->cscmr2);
 516         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 517         writel(reg, &mxc_ccm->cscmr2);
 518
 519         reg = readl(&mxc_ccm->chsccdr);
 520         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 521                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 522         writel(reg, &mxc_ccm->chsccdr);
 523
 524         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 525              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 526              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 527              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 528              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 529              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 530              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 531              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 532              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 533         writel(reg, &iomux->gpr[2]);
 534
 535         reg = readl(&iomux->gpr[3]);
 536         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 537                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 538             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 539                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 540         writel(reg, &iomux->gpr[3]);
 541
 542         /* backlight unconditionally on for now */
 543         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 544                                          ARRAY_SIZE(backlight_pads));
 545         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 546         gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
 547         gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
 548         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 549         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 550 }
 551
 552 /*
 553  * Backlight off before OS handover
 554  */
 555 void board_preboot_os(void)
 556 {
 557         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 558         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 559 }
 560 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 561
 562 int board_early_init_f(void)
 563 {
 564         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 565                                          ARRAY_SIZE(pwr_intb_pads));
 566         setup_iomux_uart();
 567
 568         return 0;
 569 }
 570
 571 /*
 572  * Do not overwrite the console
 573  * Use always serial for U-Boot console
 574  */
 575 int overwrite_console(void)
 576 {
 577         return 1;
 578 }
 579
 580 int board_init(void)
 581 {
 582         /* address of boot parameters */
 583         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 584 #if defined(CONFIG_FEC_MXC)
 585         setup_fec();
 586 #endif
 587 #if defined(CONFIG_VIDEO_IPUV3)
 588         setup_display();
 589 #endif
 590
 591 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 592         (void) pmic_init();
 593 #endif
 594
 595 #ifdef CONFIG_SATA
 596         setup_sata();
 597 #endif
 598
 599         setup_iomux_gpio();
 600
 601         return 0;
 602 }
 603
 604 #ifdef CONFIG_BOARD_LATE_INIT
 605 int board_late_init(void)
 606 {
 607 #if defined(CONFIG_REVISION_TAG) && \
 608     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 609         char env_str[256];
 610         u32 rev;
 611
 612         rev = get_board_rev();
 613         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 614         env_set("board_rev", env_str);
 615 #endif
 616
 617 #ifdef CONFIG_CMD_USB_SDP
 618         if (is_boot_from_usb()) {
 619                 printf("Serial Downloader recovery mode, using sdp command\n");
 620                 env_set("bootdelay", "0");
 621                 env_set("bootcmd", "sdp 0");
 622         }
 623 #endif /* CONFIG_CMD_USB_SDP */
 624
 625         return 0;
 626 }
 627 #endif /* CONFIG_BOARD_LATE_INIT */
 628
 629 int checkboard(void)
 630 {
 631         char it[] = " IT";
 632         int minc, maxc;
 633
 634         switch (get_cpu_temp_grade(&minc, &maxc)) {
 635         case TEMP_AUTOMOTIVE:
 636         case TEMP_INDUSTRIAL:
 637                 break;
 638         case TEMP_EXTCOMMERCIAL:
 639         default:
 640                 it[0] = 0;
 641         };
 642         printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
 643                is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
 644                (gd->ram_size == 0x20000000) ? "512" : "256", it);
 645         return 0;
 646 }
 647
 648 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 649 int ft_board_setup(void *blob, bd_t *bd)
 650 {
 651         u32 cma_size;
 652
 653         ft_common_board_setup(blob, bd);
 654
 655         cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
 656         cma_size = min((u32)(gd->ram_size >> 1), cma_size);
 657
 658         fdt_setprop_u32(blob,
 659                         fdt_path_offset(blob, "/reserved-memory/linux,cma"),
 660                         "size",
 661                         cma_size);
 662         return 0;
 663 }
 664 #endif
 665
 666 #ifdef CONFIG_CMD_BMODE
 667 static const struct boot_mode board_boot_modes[] = {
 668         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 669         {NULL,  0},
 670 };
 671 #endif
 672
 673 int misc_init_r(void)
 674 {
 675 #ifdef CONFIG_CMD_BMODE
 676         add_board_boot_modes(board_boot_modes);
 677 #endif
 678         return 0;
 679 }
 680
 681 #ifdef CONFIG_LDO_BYPASS_CHECK
 682 /* TODO, use external pmic, for now always ldo_enable */
 683 void ldo_mode_set(int ldo_bypass)
 684 {
 685         return;
 686 }
 687 #endif
 688
 689 #ifdef CONFIG_SPL_BUILD
 690 #include <spl.h>
 691 #include <linux/libfdt.h>
 692 #include "asm/arch/mx6dl-ddr.h"
 693 #include "asm/arch/iomux.h"
 694 #include "asm/arch/crm_regs.h"
 695
 696 static int mx6s_dcd_table[] = {
 697 /* ddr-setup.cfg */
 698
 699 MX6_IOM_DRAM_SDQS0, 0x00000030,
 700 MX6_IOM_DRAM_SDQS1, 0x00000030,
 701 MX6_IOM_DRAM_SDQS2, 0x00000030,
 702 MX6_IOM_DRAM_SDQS3, 0x00000030,
 703 MX6_IOM_DRAM_SDQS4, 0x00000030,
 704 MX6_IOM_DRAM_SDQS5, 0x00000030,
 705 MX6_IOM_DRAM_SDQS6, 0x00000030,
 706 MX6_IOM_DRAM_SDQS7, 0x00000030,
 707
 708 MX6_IOM_GRP_B0DS, 0x00000030,
 709 MX6_IOM_GRP_B1DS, 0x00000030,
 710 MX6_IOM_GRP_B2DS, 0x00000030,
 711 MX6_IOM_GRP_B3DS, 0x00000030,
 712 MX6_IOM_GRP_B4DS, 0x00000030,
 713 MX6_IOM_GRP_B5DS, 0x00000030,
 714 MX6_IOM_GRP_B6DS, 0x00000030,
 715 MX6_IOM_GRP_B7DS, 0x00000030,
 716 MX6_IOM_GRP_ADDDS, 0x00000030,
 717 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 718 MX6_IOM_GRP_CTLDS, 0x00000030,
 719
 720 MX6_IOM_DRAM_DQM0, 0x00020030,
 721 MX6_IOM_DRAM_DQM1, 0x00020030,
 722 MX6_IOM_DRAM_DQM2, 0x00020030,
 723 MX6_IOM_DRAM_DQM3, 0x00020030,
 724 MX6_IOM_DRAM_DQM4, 0x00020030,
 725 MX6_IOM_DRAM_DQM5, 0x00020030,
 726 MX6_IOM_DRAM_DQM6, 0x00020030,
 727 MX6_IOM_DRAM_DQM7, 0x00020030,
 728
 729 MX6_IOM_DRAM_CAS, 0x00020030,
 730 MX6_IOM_DRAM_RAS, 0x00020030,
 731 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 732 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 733
 734 MX6_IOM_DRAM_RESET, 0x00020030,
 735 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 736 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 737
 738 MX6_IOM_DRAM_SDODT0, 0x00003030,
 739 MX6_IOM_DRAM_SDODT1, 0x00003030,
 740
 741 /* (differential input) */
 742 MX6_IOM_DDRMODE_CTL, 0x00020000,
 743 /* (differential input) */
 744 MX6_IOM_GRP_DDRMODE, 0x00020000,
 745 /* disable ddr pullups */
 746 MX6_IOM_GRP_DDRPKE, 0x00000000,
 747 MX6_IOM_DRAM_SDBA2, 0x00000000,
 748 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 749 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 750
 751 /* Read data DQ Byte0-3 delay */
 752 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 753 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 754 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 755 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 756 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 757 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 758 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 759 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 760
 761 /*
 762  * MDMISC       mirroring       interleaved (row/bank/col)
 763  */
 764 /* TODO: check what the RALAT field does */
 765 MX6_MMDC_P0_MDMISC, 0x00081740,
 766
 767 /*
 768  * MDSCR        con_req
 769  */
 770 MX6_MMDC_P0_MDSCR, 0x00008000,
 771
 772
 773 /* 800mhz_2x64mx16.cfg */
 774
 775 MX6_MMDC_P0_MDPDC, 0x0002002D,
 776 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 777 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 778 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 779 MX6_MMDC_P0_MDRWD, 0x000026D2,
 780 MX6_MMDC_P0_MDOR, 0x00301023,
 781 MX6_MMDC_P0_MDOTC, 0x00333030,
 782 MX6_MMDC_P0_MDPDC, 0x0002556D,
 783 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 784 MX6_MMDC_P0_MDASP, 0x00000017,
 785 /* DDR3 DATA BUS SIZE: 64BIT */
 786 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
 787 /* DDR3 DATA BUS SIZE: 32BIT */
 788 MX6_MMDC_P0_MDCTL, 0x82190000,
 789
 790 /* Write commands to DDR */
 791 /* Load Mode Registers */
 792 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 793 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 794 MX6_MMDC_P0_MDSCR, 0x04008032,
 795 MX6_MMDC_P0_MDSCR, 0x00008033,
 796 MX6_MMDC_P0_MDSCR, 0x00048031,
 797 MX6_MMDC_P0_MDSCR, 0x13208030,
 798 /* ZQ calibration */
 799 MX6_MMDC_P0_MDSCR, 0x04008040,
 800
 801 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 802 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 803 MX6_MMDC_P0_MDREF, 0x00005800,
 804
 805 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 806 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 807
 808 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 809 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 810 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 811 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 812
 813 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 814 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 815 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 816 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 817
 818 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 819 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 820 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 821 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 822
 823 MX6_MMDC_P0_MPMUR0, 0x00000800,
 824 MX6_MMDC_P1_MPMUR0, 0x00000800,
 825 MX6_MMDC_P0_MDSCR, 0x00000000,
 826 MX6_MMDC_P0_MAPSR, 0x00011006,
 827 };
 828
 829 static int mx6dl_dcd_table[] = {
 830 /* ddr-setup.cfg */
 831
 832 MX6_IOM_DRAM_SDQS0, 0x00000030,
 833 MX6_IOM_DRAM_SDQS1, 0x00000030,
 834 MX6_IOM_DRAM_SDQS2, 0x00000030,
 835 MX6_IOM_DRAM_SDQS3, 0x00000030,
 836 MX6_IOM_DRAM_SDQS4, 0x00000030,
 837 MX6_IOM_DRAM_SDQS5, 0x00000030,
 838 MX6_IOM_DRAM_SDQS6, 0x00000030,
 839 MX6_IOM_DRAM_SDQS7, 0x00000030,
 840
 841 MX6_IOM_GRP_B0DS, 0x00000030,
 842 MX6_IOM_GRP_B1DS, 0x00000030,
 843 MX6_IOM_GRP_B2DS, 0x00000030,
 844 MX6_IOM_GRP_B3DS, 0x00000030,
 845 MX6_IOM_GRP_B4DS, 0x00000030,
 846 MX6_IOM_GRP_B5DS, 0x00000030,
 847 MX6_IOM_GRP_B6DS, 0x00000030,
 848 MX6_IOM_GRP_B7DS, 0x00000030,
 849 MX6_IOM_GRP_ADDDS, 0x00000030,
 850 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 851 MX6_IOM_GRP_CTLDS, 0x00000030,
 852
 853 MX6_IOM_DRAM_DQM0, 0x00020030,
 854 MX6_IOM_DRAM_DQM1, 0x00020030,
 855 MX6_IOM_DRAM_DQM2, 0x00020030,
 856 MX6_IOM_DRAM_DQM3, 0x00020030,
 857 MX6_IOM_DRAM_DQM4, 0x00020030,
 858 MX6_IOM_DRAM_DQM5, 0x00020030,
 859 MX6_IOM_DRAM_DQM6, 0x00020030,
 860 MX6_IOM_DRAM_DQM7, 0x00020030,
 861
 862 MX6_IOM_DRAM_CAS, 0x00020030,
 863 MX6_IOM_DRAM_RAS, 0x00020030,
 864 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 865 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 866
 867 MX6_IOM_DRAM_RESET, 0x00020030,
 868 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 869 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 870
 871 MX6_IOM_DRAM_SDODT0, 0x00003030,
 872 MX6_IOM_DRAM_SDODT1, 0x00003030,
 873
 874 /* (differential input) */
 875 MX6_IOM_DDRMODE_CTL, 0x00020000,
 876 /* (differential input) */
 877 MX6_IOM_GRP_DDRMODE, 0x00020000,
 878 /* disable ddr pullups */
 879 MX6_IOM_GRP_DDRPKE, 0x00000000,
 880 MX6_IOM_DRAM_SDBA2, 0x00000000,
 881 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 882 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 883
 884 /* Read data DQ Byte0-3 delay */
 885 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 886 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 887 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 888 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 889 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 890 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 891 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 892 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 893
 894 /*
 895  * MDMISC       mirroring       interleaved (row/bank/col)
 896  */
 897 /* TODO: check what the RALAT field does */
 898 MX6_MMDC_P0_MDMISC, 0x00081740,
 899
 900 /*
 901  * MDSCR        con_req
 902  */
 903 MX6_MMDC_P0_MDSCR, 0x00008000,
 904
 905
 906 /* 800mhz_2x64mx16.cfg */
 907
 908 MX6_MMDC_P0_MDPDC, 0x0002002D,
 909 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 910 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 911 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 912 MX6_MMDC_P0_MDRWD, 0x000026D2,
 913 MX6_MMDC_P0_MDOR, 0x00301023,
 914 MX6_MMDC_P0_MDOTC, 0x00333030,
 915 MX6_MMDC_P0_MDPDC, 0x0002556D,
 916 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 917 MX6_MMDC_P0_MDASP, 0x00000017,
 918 /* DDR3 DATA BUS SIZE: 64BIT */
 919 MX6_MMDC_P0_MDCTL, 0x821A0000,
 920 /* DDR3 DATA BUS SIZE: 32BIT */
 921 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
 922
 923 /* Write commands to DDR */
 924 /* Load Mode Registers */
 925 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 926 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 927 MX6_MMDC_P0_MDSCR, 0x04008032,
 928 MX6_MMDC_P0_MDSCR, 0x00008033,
 929 MX6_MMDC_P0_MDSCR, 0x00048031,
 930 MX6_MMDC_P0_MDSCR, 0x13208030,
 931 /* ZQ calibration */
 932 MX6_MMDC_P0_MDSCR, 0x04008040,
 933
 934 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 935 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 936 MX6_MMDC_P0_MDREF, 0x00005800,
 937
 938 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 939 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 940
 941 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 942 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 943 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 944 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 945
 946 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 947 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 948 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 949 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 950
 951 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 952 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 953 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 954 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 955
 956 MX6_MMDC_P0_MPMUR0, 0x00000800,
 957 MX6_MMDC_P1_MPMUR0, 0x00000800,
 958 MX6_MMDC_P0_MDSCR, 0x00000000,
 959 MX6_MMDC_P0_MAPSR, 0x00011006,
 960 };
 961
 962 static void ccgr_init(void)
 963 {
 964         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 965
 966         writel(0x00C03F3F, &ccm->CCGR0);
 967         writel(0x0030FC03, &ccm->CCGR1);
 968         writel(0x0FFFFFF3, &ccm->CCGR2);
 969         writel(0x3FF0300F, &ccm->CCGR3);
 970         writel(0x00FFF300, &ccm->CCGR4);
 971         writel(0x0F0000F3, &ccm->CCGR5);
 972         writel(0x000003FF, &ccm->CCGR6);
 973
 974 /*
 975  * Setup CCM_CCOSR register as follows:
 976  *
 977  * cko1_en  = 1    --> CKO1 enabled
 978  * cko1_div = 111  --> divide by 8
 979  * cko1_sel = 1011 --> ahb_clk_root
 980  *
 981  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
 982  */
 983         writel(0x000000FB, &ccm->ccosr);
 984 }
 985
 986 static void ddr_init(int *table, int size)
 987 {
 988         int i;
 989
 990         for (i = 0; i < size / 2 ; i++)
 991                 writel(table[2 * i + 1], table[2 * i]);
 992 }
 993
 994 static void spl_dram_init(void)
 995 {
 996         int minc, maxc;
 997
 998         switch (get_cpu_temp_grade(&minc, &maxc)) {
 999         case TEMP_COMMERCIAL:
1000         case TEMP_EXTCOMMERCIAL:
1001                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1002                         puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1003                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1004                 } else {
1005                         puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1006                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1007                 }
1008                 break;
1009         case TEMP_INDUSTRIAL:
1010         case TEMP_AUTOMOTIVE:
1011         default:
1012                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1013                         puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
1014                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1015                 } else {
1016                         puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1017                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1018                 }
1019                 break;
1020         };
1021         udelay(100);
1022 }
1023
1024 static iomux_v3_cfg_t const gpio_reset_pad[] = {
1025         MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
1026                                         MUX_MODE_SION
1027 #define GPIO_NRESET IMX_GPIO_NR(6, 27)
1028 };
1029
1030 #define IMX_RESET_CAUSE_POR 0x00011
1031 static void nreset_out(void)
1032 {
1033         int reset_cause = get_imx_reset_cause();
1034
1035         if (reset_cause != IMX_RESET_CAUSE_POR) {
1036                 imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
1037                                                  ARRAY_SIZE(gpio_reset_pad));
1038                 gpio_direction_output(GPIO_NRESET, 1);
1039                 udelay(100);
1040                 gpio_direction_output(GPIO_NRESET, 0);
1041         }
1042 }
1043
1044 void board_init_f(ulong dummy)
1045 {
1046         /* setup AIPS and disable watchdog */
1047         arch_cpu_init();
1048
1049         ccgr_init();
1050         gpr_init();
1051
1052         /* iomux */
1053         board_early_init_f();
1054
1055         /* setup GP timer */
1056         timer_init();
1057
1058         /* UART clocks enabled and gd valid - init serial console */
1059         preloader_console_init();
1060
1061         /* Make sure we use dte mode */
1062         setup_dtemode_uart();
1063
1064         /* DDR initialization */
1065         spl_dram_init();
1066
1067         /* Clear the BSS. */
1068         memset(__bss_start, 0, __bss_end - __bss_start);
1069
1070         /* Assert nReset_Out */
1071         nreset_out();
1072
1073         /* load/boot image from boot device */
1074         board_init_r(NULL, 0);
1075 }
1076
1077 void reset_cpu(ulong addr)
1078 {
1079 }
1080
1081 #endif /* CONFIG_SPL_BUILD */
1082
1083 static struct mxc_serial_platdata mxc_serial_plat = {
1084         .reg = (struct mxc_uart *)UART1_BASE,
1085         .use_dte = true,
1086 };
1087
1088 U_BOOT_DEVICE(mxc_serial) = {
1089         .name = "serial_mxc",
1090         .platdata = &mxc_serial_plat,
1091 };