drivers/timer/cadence-ttc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <errno.h>
   9 #include <timer.h>
  10 #include <asm/io.h>
  11 #include <linux/err.h>
  12
  13 #define CNT_CNTRL_RESET         BIT(4)
  14
  15 struct cadence_ttc_regs {
  16         u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
  17         u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
  18         u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
  19         u32 counter_cntrl1; /* 0xC - Counter Control 1 */
  20         u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
  21         u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
  22         u32 counter_val1; /* 0x18 - Counter Control 1 */
  23         u32 counter_val2; /* 0x1C - Counter Control 2 */
  24         u32 counter_val3; /* 0x20 - Counter Control 3 */
  25         u32 reserved[15];
  26         u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */
  27         u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */
  28         u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */
  29 };
  30
  31 struct cadence_ttc_priv {
  32         struct cadence_ttc_regs *regs;
  33 };
  34
  35 #if CONFIG_IS_ENABLED(BOOTSTAGE)
  36 ulong timer_get_boot_us(void)
  37 {
  38         u64 ticks = 0;
  39         u32 rate = 1;
  40         u64 us;
  41         int ret;
  42
  43         ret = dm_timer_init();
  44         if (!ret) {
  45                 /* The timer is available */
  46                 rate = timer_get_rate(gd->timer);
  47                 timer_get_count(gd->timer, &ticks);
  48         } else {
  49                 return 0;
  50         }
  51
  52         us = (ticks * 1000) / rate;
  53         return us;
  54 }
  55 #endif
  56
  57 static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
  58 {
  59         struct cadence_ttc_priv *priv = dev_get_priv(dev);
  60
  61         *count = readl(&priv->regs->counter_val1);
  62
  63         return 0;
  64 }
  65
  66 static int cadence_ttc_probe(struct udevice *dev)
  67 {
  68         struct cadence_ttc_priv *priv = dev_get_priv(dev);
  69
  70         /* Disable interrupts for sure */
  71         writel(0, &priv->regs->interrupt_enable1);
  72         writel(0, &priv->regs->interrupt_enable2);
  73         writel(0, &priv->regs->interrupt_enable3);
  74
  75         /* Make sure that clocks are configured properly without prescaller */
  76         writel(0, &priv->regs->clk_cntrl1);
  77         writel(0, &priv->regs->clk_cntrl2);
  78         writel(0, &priv->regs->clk_cntrl3);
  79
  80         /* Reset and enable this counter */
  81         writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1);
  82
  83         return 0;
  84 }
  85
  86 static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
  87 {
  88         struct cadence_ttc_priv *priv = dev_get_priv(dev);
  89
  90         priv->regs = map_physmem(dev_read_addr(dev),
  91                                  sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
  92         if (IS_ERR(priv->regs))
  93                 return PTR_ERR(priv->regs);
  94
  95         return 0;
  96 }
  97
  98 static const struct timer_ops cadence_ttc_ops = {
  99         .get_count = cadence_ttc_get_count,
 100 };
 101
 102 static const struct udevice_id cadence_ttc_ids[] = {
 103         { .compatible = "cdns,ttc" },
 104         {}
 105 };
 106
 107 U_BOOT_DRIVER(cadence_ttc) = {
 108         .name = "cadence_ttc",
 109         .id = UCLASS_TIMER,
 110         .of_match = cadence_ttc_ids,
 111         .ofdata_to_platdata = cadence_ttc_ofdata_to_platdata,
 112         .priv_auto_alloc_size = sizeof(struct cadence_ttc_priv),
 113         .probe = cadence_ttc_probe,
 114         .ops = &cadence_ttc_ops,
 115 };