cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * (C) Copyright 2007-2008
  10  * Stefan Roese, DENX Software Engineering, [email protected].
  11  *
  12  * COPYRIGHT   AMCC   CORPORATION 2004
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  * MA 02111-1307 USA
  31  *
  32  */
  33
  34 /* define DEBUG for debugging output (obviously ;-)) */
  35 #if 0
  36 #define DEBUG
  37 #endif
  38
  39 #include <common.h>
  40 #include <command.h>
  41 #include <ppc4xx.h>
  42 #include <i2c.h>
  43 #include <asm/io.h>
  44 #include <asm/processor.h>
  45 #include <asm/mmu.h>
  46 #include <asm/cache.h>
  47
  48 #if defined(CONFIG_SPD_EEPROM) &&                               \
  49         (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  50          defined(CONFIG_460EX) || defined(CONFIG_460GT))
  51
  52 /*-----------------------------------------------------------------------------+
  53  * Defines
  54  *-----------------------------------------------------------------------------*/
  55 #ifndef TRUE
  56 #define TRUE            1
  57 #endif
  58 #ifndef FALSE
  59 #define FALSE           0
  60 #endif
  61
  62 #define SDRAM_DDR1      1
  63 #define SDRAM_DDR2      2
  64 #define SDRAM_NONE      0
  65
  66 #define MAXDIMMS        2
  67 #define MAXRANKS        4
  68 #define MAXBXCF         4
  69 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
  70
  71 #define ONE_BILLION     1000000000
  72
  73 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  74
  75 #define CMD_NOP         (7 << 19)
  76 #define CMD_PRECHARGE   (2 << 19)
  77 #define CMD_REFRESH     (1 << 19)
  78 #define CMD_EMR         (0 << 19)
  79 #define CMD_READ        (5 << 19)
  80 #define CMD_WRITE       (4 << 19)
  81
  82 #define SELECT_MR       (0 << 16)
  83 #define SELECT_EMR      (1 << 16)
  84 #define SELECT_EMR2     (2 << 16)
  85 #define SELECT_EMR3     (3 << 16)
  86
  87 /* MR */
  88 #define DLL_RESET       0x00000100
  89
  90 #define WRITE_RECOV_2   (1 << 9)
  91 #define WRITE_RECOV_3   (2 << 9)
  92 #define WRITE_RECOV_4   (3 << 9)
  93 #define WRITE_RECOV_5   (4 << 9)
  94 #define WRITE_RECOV_6   (5 << 9)
  95
  96 #define BURST_LEN_4     0x00000002
  97
  98 /* EMR */
  99 #define ODT_0_OHM       0x00000000
 100 #define ODT_50_OHM      0x00000044
 101 #define ODT_75_OHM      0x00000004
 102 #define ODT_150_OHM     0x00000040
 103
 104 #define ODS_FULL        0x00000000
 105 #define ODS_REDUCED     0x00000002
 106
 107 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 108 #define ODT_EB0R        (0x80000000 >> 8)
 109 #define ODT_EB0W        (0x80000000 >> 7)
 110 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 111 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 112 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 113
 114 /* Defines for the Read Cycle Delay test */
 115 #define NUMMEMTESTS     8
 116 #define NUMMEMWORDS     8
 117 #define NUMLOOPS        64              /* memory test loops */
 118
 119 /*
 120  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 121  * region. Right now the cache should still be disabled in U-Boot because of the
 122  * EMAC driver, that need it's buffer descriptor to be located in non cached
 123  * memory.
 124  *
 125  * If at some time this restriction doesn't apply anymore, just define
 126  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 127  * everything correctly.
 128  */
 129 #ifdef CONFIG_4xx_DCACHE
 130 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 131 #else
 132 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 133 #endif
 134
 135 /*
 136  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 137  */
 138 void __spd_ddr_init_hang (void)
 139 {
 140         hang ();
 141 }
 142 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 143
 144 /*
 145  * To provide an interface for board specific config values in this common
 146  * DDR setup code, we implement he "weak" default functions here. They return
 147  * the default value back to the caller.
 148  *
 149  * Please see include/configs/yucca.h for an example fora board specific
 150  * implementation.
 151  */
 152 u32 __ddr_wrdtr(u32 default_val)
 153 {
 154         return default_val;
 155 }
 156 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 157
 158 u32 __ddr_clktr(u32 default_val)
 159 {
 160         return default_val;
 161 }
 162 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 163
 164
 165 /* Private Structure Definitions */
 166
 167 /* enum only to ease code for cas latency setting */
 168 typedef enum ddr_cas_id {
 169         DDR_CAS_2      = 20,
 170         DDR_CAS_2_5    = 25,
 171         DDR_CAS_3      = 30,
 172         DDR_CAS_4      = 40,
 173         DDR_CAS_5      = 50
 174 } ddr_cas_id_t;
 175
 176 /*-----------------------------------------------------------------------------+
 177  * Prototypes
 178  *-----------------------------------------------------------------------------*/
 179 static unsigned long sdram_memsize(void);
 180 static void get_spd_info(unsigned long *dimm_populated,
 181                          unsigned char *iic0_dimm_addr,
 182                          unsigned long num_dimm_banks);
 183 static void check_mem_type(unsigned long *dimm_populated,
 184                            unsigned char *iic0_dimm_addr,
 185                            unsigned long num_dimm_banks);
 186 static void check_frequency(unsigned long *dimm_populated,
 187                             unsigned char *iic0_dimm_addr,
 188                             unsigned long num_dimm_banks);
 189 static void check_rank_number(unsigned long *dimm_populated,
 190                               unsigned char *iic0_dimm_addr,
 191                               unsigned long num_dimm_banks);
 192 static void check_voltage_type(unsigned long *dimm_populated,
 193                                unsigned char *iic0_dimm_addr,
 194                                unsigned long num_dimm_banks);
 195 static void program_memory_queue(unsigned long *dimm_populated,
 196                                  unsigned char *iic0_dimm_addr,
 197                                  unsigned long num_dimm_banks);
 198 static void program_codt(unsigned long *dimm_populated,
 199                          unsigned char *iic0_dimm_addr,
 200                          unsigned long num_dimm_banks);
 201 static void program_mode(unsigned long *dimm_populated,
 202                          unsigned char *iic0_dimm_addr,
 203                          unsigned long num_dimm_banks,
 204                          ddr_cas_id_t *selected_cas,
 205                          int *write_recovery);
 206 static void program_tr(unsigned long *dimm_populated,
 207                        unsigned char *iic0_dimm_addr,
 208                        unsigned long num_dimm_banks);
 209 static void program_rtr(unsigned long *dimm_populated,
 210                         unsigned char *iic0_dimm_addr,
 211                         unsigned long num_dimm_banks);
 212 static void program_bxcf(unsigned long *dimm_populated,
 213                          unsigned char *iic0_dimm_addr,
 214                          unsigned long num_dimm_banks);
 215 static void program_copt1(unsigned long *dimm_populated,
 216                           unsigned char *iic0_dimm_addr,
 217                           unsigned long num_dimm_banks);
 218 static void program_initplr(unsigned long *dimm_populated,
 219                             unsigned char *iic0_dimm_addr,
 220                             unsigned long num_dimm_banks,
 221                             ddr_cas_id_t selected_cas,
 222                             int write_recovery);
 223 static unsigned long is_ecc_enabled(void);
 224 #ifdef CONFIG_DDR_ECC
 225 static void program_ecc(unsigned long *dimm_populated,
 226                         unsigned char *iic0_dimm_addr,
 227                         unsigned long num_dimm_banks,
 228                         unsigned long tlb_word2_i_value);
 229 static void program_ecc_addr(unsigned long start_address,
 230                              unsigned long num_bytes,
 231                              unsigned long tlb_word2_i_value);
 232 #endif
 233 static void program_DQS_calibration(unsigned long *dimm_populated,
 234                                     unsigned char *iic0_dimm_addr,
 235                                     unsigned long num_dimm_banks);
 236 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 237 static void     test(void);
 238 #else
 239 static void     DQS_calibration_process(void);
 240 #endif
 241 static void ppc440sp_sdram_register_dump(void);
 242 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 243 void dcbz_area(u32 start_address, u32 num_bytes);
 244
 245 static u32 mfdcr_any(u32 dcr)
 246 {
 247         u32 val;
 248
 249         switch (dcr) {
 250         case SDRAM_R0BAS + 0:
 251                 val = mfdcr(SDRAM_R0BAS + 0);
 252                 break;
 253         case SDRAM_R0BAS + 1:
 254                 val = mfdcr(SDRAM_R0BAS + 1);
 255                 break;
 256         case SDRAM_R0BAS + 2:
 257                 val = mfdcr(SDRAM_R0BAS + 2);
 258                 break;
 259         case SDRAM_R0BAS + 3:
 260                 val = mfdcr(SDRAM_R0BAS + 3);
 261                 break;
 262         default:
 263                 printf("DCR %d not defined in case statement!!!\n", dcr);
 264                 val = 0; /* just to satisfy the compiler */
 265         }
 266
 267         return val;
 268 }
 269
 270 static void mtdcr_any(u32 dcr, u32 val)
 271 {
 272         switch (dcr) {
 273         case SDRAM_R0BAS + 0:
 274                 mtdcr(SDRAM_R0BAS + 0, val);
 275                 break;
 276         case SDRAM_R0BAS + 1:
 277                 mtdcr(SDRAM_R0BAS + 1, val);
 278                 break;
 279         case SDRAM_R0BAS + 2:
 280                 mtdcr(SDRAM_R0BAS + 2, val);
 281                 break;
 282         case SDRAM_R0BAS + 3:
 283                 mtdcr(SDRAM_R0BAS + 3, val);
 284                 break;
 285         default:
 286                 printf("DCR %d not defined in case statement!!!\n", dcr);
 287         }
 288 }
 289
 290 static unsigned char spd_read(uchar chip, uint addr)
 291 {
 292         unsigned char data[2];
 293
 294         if (i2c_probe(chip) == 0)
 295                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 296                         return data[0];
 297
 298         return 0;
 299 }
 300
 301 /*-----------------------------------------------------------------------------+
 302  * sdram_memsize
 303  *-----------------------------------------------------------------------------*/
 304 static unsigned long sdram_memsize(void)
 305 {
 306         unsigned long mem_size;
 307         unsigned long mcopt2;
 308         unsigned long mcstat;
 309         unsigned long mb0cf;
 310         unsigned long sdsz;
 311         unsigned long i;
 312
 313         mem_size = 0;
 314
 315         mfsdram(SDRAM_MCOPT2, mcopt2);
 316         mfsdram(SDRAM_MCSTAT, mcstat);
 317
 318         /* DDR controller must be enabled and not in self-refresh. */
 319         /* Otherwise memsize is zero. */
 320         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 321             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 322             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 323                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 324                 for (i = 0; i < MAXBXCF; i++) {
 325                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 326                         /* Banks enabled */
 327                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 328                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 329
 330                                 switch(sdsz) {
 331                                 case SDRAM_RXBAS_SDSZ_8:
 332                                         mem_size+=8;
 333                                         break;
 334                                 case SDRAM_RXBAS_SDSZ_16:
 335                                         mem_size+=16;
 336                                         break;
 337                                 case SDRAM_RXBAS_SDSZ_32:
 338                                         mem_size+=32;
 339                                         break;
 340                                 case SDRAM_RXBAS_SDSZ_64:
 341                                         mem_size+=64;
 342                                         break;
 343                                 case SDRAM_RXBAS_SDSZ_128:
 344                                         mem_size+=128;
 345                                         break;
 346                                 case SDRAM_RXBAS_SDSZ_256:
 347                                         mem_size+=256;
 348                                         break;
 349                                 case SDRAM_RXBAS_SDSZ_512:
 350                                         mem_size+=512;
 351                                         break;
 352                                 case SDRAM_RXBAS_SDSZ_1024:
 353                                         mem_size+=1024;
 354                                         break;
 355                                 case SDRAM_RXBAS_SDSZ_2048:
 356                                         mem_size+=2048;
 357                                         break;
 358                                 case SDRAM_RXBAS_SDSZ_4096:
 359                                         mem_size+=4096;
 360                                         break;
 361                                 default:
 362                                         mem_size=0;
 363                                         break;
 364                                 }
 365                         }
 366                 }
 367         }
 368
 369         mem_size *= 1024 * 1024;
 370         return(mem_size);
 371 }
 372
 373 /*-----------------------------------------------------------------------------+
 374  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 375  * Note: This routine runs from flash with a stack set up in the chip's
 376  * sram space.  It is important that the routine does not require .sbss, .bss or
 377  * .data sections.  It also cannot call routines that require these sections.
 378  *-----------------------------------------------------------------------------*/
 379 /*-----------------------------------------------------------------------------
 380  * Function:     initdram
 381  * Description:  Configures SDRAM memory banks for DDR operation.
 382  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 383  *               via the IIC bus and then configures the DDR SDRAM memory
 384  *               banks appropriately. If Auto Memory Configuration is
 385  *               not used, it is assumed that no DIMM is plugged
 386  *-----------------------------------------------------------------------------*/
 387 long int initdram(int board_type)
 388 {
 389         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 390         unsigned char spd0[MAX_SPD_BYTES];
 391         unsigned char spd1[MAX_SPD_BYTES];
 392         unsigned char *dimm_spd[MAXDIMMS];
 393         unsigned long dimm_populated[MAXDIMMS];
 394         unsigned long num_dimm_banks;           /* on board dimm banks */
 395         unsigned long val;
 396         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 397         int write_recovery;
 398         unsigned long dram_size = 0;
 399
 400         num_dimm_banks = sizeof(iic0_dimm_addr);
 401
 402         /*------------------------------------------------------------------
 403          * Set up an array of SPD matrixes.
 404          *-----------------------------------------------------------------*/
 405         dimm_spd[0] = spd0;
 406         dimm_spd[1] = spd1;
 407
 408         /*------------------------------------------------------------------
 409          * Reset the DDR-SDRAM controller.
 410          *-----------------------------------------------------------------*/
 411         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 412         mtsdr(SDR0_SRST, 0x00000000);
 413
 414         /*
 415          * Make sure I2C controller is initialized
 416          * before continuing.
 417          */
 418
 419         /* switch to correct I2C bus */
 420         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 421         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 422
 423         /*------------------------------------------------------------------
 424          * Clear out the serial presence detect buffers.
 425          * Perform IIC reads from the dimm.  Fill in the spds.
 426          * Check to see if the dimm slots are populated
 427          *-----------------------------------------------------------------*/
 428         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 429
 430         /*------------------------------------------------------------------
 431          * Check the memory type for the dimms plugged.
 432          *-----------------------------------------------------------------*/
 433         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 434
 435         /*------------------------------------------------------------------
 436          * Check the frequency supported for the dimms plugged.
 437          *-----------------------------------------------------------------*/
 438         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 439
 440         /*------------------------------------------------------------------
 441          * Check the total rank number.
 442          *-----------------------------------------------------------------*/
 443         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 444
 445         /*------------------------------------------------------------------
 446          * Check the voltage type for the dimms plugged.
 447          *-----------------------------------------------------------------*/
 448         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 449
 450         /*------------------------------------------------------------------
 451          * Program SDRAM controller options 2 register
 452          * Except Enabling of the memory controller.
 453          *-----------------------------------------------------------------*/
 454         mfsdram(SDRAM_MCOPT2, val);
 455         mtsdram(SDRAM_MCOPT2,
 456                 (val &
 457                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 458                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 459                    SDRAM_MCOPT2_ISIE_MASK))
 460                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 461                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 462                    SDRAM_MCOPT2_ISIE_ENABLE));
 463
 464         /*------------------------------------------------------------------
 465          * Program SDRAM controller options 1 register
 466          * Note: Does not enable the memory controller.
 467          *-----------------------------------------------------------------*/
 468         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 469
 470         /*------------------------------------------------------------------
 471          * Set the SDRAM Controller On Die Termination Register
 472          *-----------------------------------------------------------------*/
 473         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 474
 475         /*------------------------------------------------------------------
 476          * Program SDRAM refresh register.
 477          *-----------------------------------------------------------------*/
 478         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 479
 480         /*------------------------------------------------------------------
 481          * Program SDRAM mode register.
 482          *-----------------------------------------------------------------*/
 483         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 484                      &selected_cas, &write_recovery);
 485
 486         /*------------------------------------------------------------------
 487          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 488          *-----------------------------------------------------------------*/
 489         mfsdram(SDRAM_WRDTR, val);
 490         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 491                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 492
 493         /*------------------------------------------------------------------
 494          * Set the SDRAM Clock Timing Register
 495          *-----------------------------------------------------------------*/
 496         mfsdram(SDRAM_CLKTR, val);
 497         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 498                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 499
 500         /*------------------------------------------------------------------
 501          * Program the BxCF registers.
 502          *-----------------------------------------------------------------*/
 503         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 504
 505         /*------------------------------------------------------------------
 506          * Program SDRAM timing registers.
 507          *-----------------------------------------------------------------*/
 508         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 509
 510         /*------------------------------------------------------------------
 511          * Set the Extended Mode register
 512          *-----------------------------------------------------------------*/
 513         mfsdram(SDRAM_MEMODE, val);
 514         mtsdram(SDRAM_MEMODE,
 515                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 516                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 517                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 518                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 519
 520         /*------------------------------------------------------------------
 521          * Program Initialization preload registers.
 522          *-----------------------------------------------------------------*/
 523         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 524                         selected_cas, write_recovery);
 525
 526         /*------------------------------------------------------------------
 527          * Delay to ensure 200usec have elapsed since reset.
 528          *-----------------------------------------------------------------*/
 529         udelay(400);
 530
 531         /*------------------------------------------------------------------
 532          * Set the memory queue core base addr.
 533          *-----------------------------------------------------------------*/
 534         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 535
 536         /*------------------------------------------------------------------
 537          * Program SDRAM controller options 2 register
 538          * Enable the memory controller.
 539          *-----------------------------------------------------------------*/
 540         mfsdram(SDRAM_MCOPT2, val);
 541         mtsdram(SDRAM_MCOPT2,
 542                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 543                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 544                 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
 545
 546         /*------------------------------------------------------------------
 547          * Wait for SDRAM_CFG0_DC_EN to complete.
 548          *-----------------------------------------------------------------*/
 549         do {
 550                 mfsdram(SDRAM_MCSTAT, val);
 551         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 552
 553         /* get installed memory size */
 554         dram_size = sdram_memsize();
 555
 556         /* and program tlb entries for this size (dynamic) */
 557
 558         /*
 559          * Program TLB entries with caches enabled, for best performace
 560          * while auto-calibrating and ECC generation
 561          */
 562         program_tlb(0, 0, dram_size, 0);
 563
 564         /*------------------------------------------------------------------
 565          * DQS calibration.
 566          *-----------------------------------------------------------------*/
 567         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 568
 569 #ifdef CONFIG_DDR_ECC
 570         /*------------------------------------------------------------------
 571          * If ecc is enabled, initialize the parity bits.
 572          *-----------------------------------------------------------------*/
 573         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 574 #endif
 575
 576         /*
 577          * Now after initialization (auto-calibration and ECC generation)
 578          * remove the TLB entries with caches enabled and program again with
 579          * desired cache functionality
 580          */
 581         remove_tlb(0, dram_size);
 582         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 583
 584         ppc440sp_sdram_register_dump();
 585
 586         /*
 587          * Clear potential errors resulting from auto-calibration.
 588          * If not done, then we could get an interrupt later on when
 589          * exceptions are enabled.
 590          */
 591         set_mcsr(get_mcsr());
 592
 593         return dram_size;
 594 }
 595
 596 static void get_spd_info(unsigned long *dimm_populated,
 597                          unsigned char *iic0_dimm_addr,
 598                          unsigned long num_dimm_banks)
 599 {
 600         unsigned long dimm_num;
 601         unsigned long dimm_found;
 602         unsigned char num_of_bytes;
 603         unsigned char total_size;
 604
 605         dimm_found = FALSE;
 606         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 607                 num_of_bytes = 0;
 608                 total_size = 0;
 609
 610                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 611                 debug("\nspd_read(0x%x) returned %d\n",
 612                       iic0_dimm_addr[dimm_num], num_of_bytes);
 613                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 614                 debug("spd_read(0x%x) returned %d\n",
 615                       iic0_dimm_addr[dimm_num], total_size);
 616
 617                 if ((num_of_bytes != 0) && (total_size != 0)) {
 618                         dimm_populated[dimm_num] = TRUE;
 619                         dimm_found = TRUE;
 620                         debug("DIMM slot %lu: populated\n", dimm_num);
 621                 } else {
 622                         dimm_populated[dimm_num] = FALSE;
 623                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 624                 }
 625         }
 626
 627         if (dimm_found == FALSE) {
 628                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 629                 spd_ddr_init_hang ();
 630         }
 631 }
 632
 633 void board_add_ram_info(int use_default)
 634 {
 635         PPC4xx_SYS_INFO board_cfg;
 636         u32 val;
 637
 638         if (is_ecc_enabled())
 639                 puts(" (ECC");
 640         else
 641                 puts(" (ECC not");
 642
 643         get_sys_info(&board_cfg);
 644
 645         mfsdr(SDR0_DDR0, val);
 646         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 647         printf(" enabled, %d MHz", (val * 2) / 1000000);
 648
 649         mfsdram(SDRAM_MMODE, val);
 650         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 651         printf(", CL%d)", val);
 652 }
 653
 654 /*------------------------------------------------------------------
 655  * For the memory DIMMs installed, this routine verifies that they
 656  * really are DDR specific DIMMs.
 657  *-----------------------------------------------------------------*/
 658 static void check_mem_type(unsigned long *dimm_populated,
 659                            unsigned char *iic0_dimm_addr,
 660                            unsigned long num_dimm_banks)
 661 {
 662         unsigned long dimm_num;
 663         unsigned long dimm_type;
 664
 665         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 666                 if (dimm_populated[dimm_num] == TRUE) {
 667                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 668                         switch (dimm_type) {
 669                         case 1:
 670                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 671                                        "slot %d.\n", (unsigned int)dimm_num);
 672                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 673                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 674                                 spd_ddr_init_hang ();
 675                                 break;
 676                         case 2:
 677                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 678                                        (unsigned int)dimm_num);
 679                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 680                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 681                                 spd_ddr_init_hang ();
 682                                 break;
 683                         case 3:
 684                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 685                                        (unsigned int)dimm_num);
 686                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 687                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 688                                 spd_ddr_init_hang ();
 689                                 break;
 690                         case 4:
 691                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 692                                        (unsigned int)dimm_num);
 693                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 694                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 695                                 spd_ddr_init_hang ();
 696                                 break;
 697                         case 5:
 698                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 699                                        (unsigned int)dimm_num);
 700                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 701                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 702                                 spd_ddr_init_hang ();
 703                                 break;
 704                         case 6:
 705                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 706                                        (unsigned int)dimm_num);
 707                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 708                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 709                                 spd_ddr_init_hang ();
 710                                 break;
 711                         case 7:
 712                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 713                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 714                                 break;
 715                         case 8:
 716                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 717                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 718                                 break;
 719                         default:
 720                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 721                                        (unsigned int)dimm_num);
 722                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 723                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 724                                 spd_ddr_init_hang ();
 725                                 break;
 726                         }
 727                 }
 728         }
 729         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 730                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 731                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 732                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 733                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 734                         spd_ddr_init_hang ();
 735                 }
 736         }
 737 }
 738
 739 /*------------------------------------------------------------------
 740  * For the memory DIMMs installed, this routine verifies that
 741  * frequency previously calculated is supported.
 742  *-----------------------------------------------------------------*/
 743 static void check_frequency(unsigned long *dimm_populated,
 744                             unsigned char *iic0_dimm_addr,
 745                             unsigned long num_dimm_banks)
 746 {
 747         unsigned long dimm_num;
 748         unsigned long tcyc_reg;
 749         unsigned long cycle_time;
 750         unsigned long calc_cycle_time;
 751         unsigned long sdram_freq;
 752         unsigned long sdr_ddrpll;
 753         PPC4xx_SYS_INFO board_cfg;
 754
 755         /*------------------------------------------------------------------
 756          * Get the board configuration info.
 757          *-----------------------------------------------------------------*/
 758         get_sys_info(&board_cfg);
 759
 760         mfsdr(SDR0_DDR0, sdr_ddrpll);
 761         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 762
 763         /*
 764          * calc_cycle_time is calculated from DDR frequency set by board/chip
 765          * and is expressed in multiple of 10 picoseconds
 766          * to match the way DIMM cycle time is calculated below.
 767          */
 768         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 769
 770         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 771                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 772                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 773                         /*
 774                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 775                          * the higher order nibble (bits 4-7) designates the cycle time
 776                          * to a granularity of 1ns;
 777                          * the value presented by the lower order nibble (bits 0-3)
 778                          * has a granularity of .1ns and is added to the value designated
 779                          * by the higher nibble. In addition, four lines of the lower order
 780                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 781                          */
 782                          /* Convert from hex to decimal */
 783                         if ((tcyc_reg & 0x0F) == 0x0D)
 784                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 785                         else if ((tcyc_reg & 0x0F) == 0x0C)
 786                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 787                         else if ((tcyc_reg & 0x0F) == 0x0B)
 788                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 789                         else if ((tcyc_reg & 0x0F) == 0x0A)
 790                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 791                         else
 792                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 793                                         ((tcyc_reg & 0x0F)*10);
 794                         debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
 795
 796                         if  (cycle_time > (calc_cycle_time + 10)) {
 797                                 /*
 798                                  * the provided sdram cycle_time is too small
 799                                  * for the available DIMM cycle_time.
 800                                  * The additionnal 100ps is here to accept a small incertainty.
 801                                  */
 802                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 803                                        "slot %d \n while calculated cycle time is %d ps.\n",
 804                                        (unsigned int)(cycle_time*10),
 805                                        (unsigned int)dimm_num,
 806                                        (unsigned int)(calc_cycle_time*10));
 807                                 printf("Replace the DIMM, or change DDR frequency via "
 808                                        "strapping bits.\n\n");
 809                                 spd_ddr_init_hang ();
 810                         }
 811                 }
 812         }
 813 }
 814
 815 /*------------------------------------------------------------------
 816  * For the memory DIMMs installed, this routine verifies two
 817  * ranks/banks maximum are availables.
 818  *-----------------------------------------------------------------*/
 819 static void check_rank_number(unsigned long *dimm_populated,
 820                               unsigned char *iic0_dimm_addr,
 821                               unsigned long num_dimm_banks)
 822 {
 823         unsigned long dimm_num;
 824         unsigned long dimm_rank;
 825         unsigned long total_rank = 0;
 826
 827         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 828                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 829                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 830                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 831                                 dimm_rank = (dimm_rank & 0x0F) +1;
 832                         else
 833                                 dimm_rank = dimm_rank & 0x0F;
 834
 835
 836                         if (dimm_rank > MAXRANKS) {
 837                                 printf("ERROR: DRAM DIMM detected with %d ranks in "
 838                                        "slot %d is not supported.\n", dimm_rank, dimm_num);
 839                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 840                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 841                                 spd_ddr_init_hang ();
 842                         } else
 843                                 total_rank += dimm_rank;
 844                 }
 845                 if (total_rank > MAXRANKS) {
 846                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 847                                "for all slots.\n", (unsigned int)total_rank);
 848                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 849                         printf("Remove one of the DIMM modules.\n\n");
 850                         spd_ddr_init_hang ();
 851                 }
 852         }
 853 }
 854
 855 /*------------------------------------------------------------------
 856  * only support 2.5V modules.
 857  * This routine verifies this.
 858  *-----------------------------------------------------------------*/
 859 static void check_voltage_type(unsigned long *dimm_populated,
 860                                unsigned char *iic0_dimm_addr,
 861                                unsigned long num_dimm_banks)
 862 {
 863         unsigned long dimm_num;
 864         unsigned long voltage_type;
 865
 866         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 867                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 868                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 869                         switch (voltage_type) {
 870                         case 0x00:
 871                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 872                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 873                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 874                                        (unsigned int)dimm_num);
 875                                 spd_ddr_init_hang ();
 876                                 break;
 877                         case 0x01:
 878                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 879                                 printf("This DIMM is LVTTL.\n");
 880                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 881                                        (unsigned int)dimm_num);
 882                                 spd_ddr_init_hang ();
 883                                 break;
 884                         case 0x02:
 885                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 886                                 printf("This DIMM is 1.5 Volt.\n");
 887                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 888                                        (unsigned int)dimm_num);
 889                                 spd_ddr_init_hang ();
 890                                 break;
 891                         case 0x03:
 892                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 893                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 894                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 895                                        (unsigned int)dimm_num);
 896                                 spd_ddr_init_hang ();
 897                                 break;
 898                         case 0x04:
 899                                 /* 2.5 Voltage only for DDR1 */
 900                                 break;
 901                         case 0x05:
 902                                 /* 1.8 Voltage only for DDR2 */
 903                                 break;
 904                         default:
 905                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 906                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 907                                        (unsigned int)dimm_num);
 908                                 spd_ddr_init_hang ();
 909                                 break;
 910                         }
 911                 }
 912         }
 913 }
 914
 915 /*-----------------------------------------------------------------------------+
 916  * program_copt1.
 917  *-----------------------------------------------------------------------------*/
 918 static void program_copt1(unsigned long *dimm_populated,
 919                           unsigned char *iic0_dimm_addr,
 920                           unsigned long num_dimm_banks)
 921 {
 922         unsigned long dimm_num;
 923         unsigned long mcopt1;
 924         unsigned long ecc_enabled;
 925         unsigned long ecc = 0;
 926         unsigned long data_width = 0;
 927         unsigned long dimm_32bit;
 928         unsigned long dimm_64bit;
 929         unsigned long registered = 0;
 930         unsigned long attribute = 0;
 931         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 932         unsigned long bankcount;
 933         unsigned long ddrtype;
 934         unsigned long val;
 935
 936 #ifdef CONFIG_DDR_ECC
 937         ecc_enabled = TRUE;
 938 #else
 939         ecc_enabled = FALSE;
 940 #endif
 941         dimm_32bit = FALSE;
 942         dimm_64bit = FALSE;
 943         buf0 = FALSE;
 944         buf1 = FALSE;
 945
 946         /*------------------------------------------------------------------
 947          * Set memory controller options reg 1, SDRAM_MCOPT1.
 948          *-----------------------------------------------------------------*/
 949         mfsdram(SDRAM_MCOPT1, val);
 950         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 951                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 952                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 953                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 954                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 955                          SDRAM_MCOPT1_DREF_MASK);
 956
 957         mcopt1 |= SDRAM_MCOPT1_QDEP;
 958         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 959         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 960         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 961         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 962         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 963
 964         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 965                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 966                         /* test ecc support */
 967                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 968                         if (ecc != 0x02) /* ecc not supported */
 969                                 ecc_enabled = FALSE;
 970
 971                         /* test bank count */
 972                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
 973                         if (bankcount == 0x04) /* bank count = 4 */
 974                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
 975                         else /* bank count = 8 */
 976                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
 977
 978                         /* test DDR type */
 979                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
 980                         /* test for buffered/unbuffered, registered, differential clocks */
 981                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
 982                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
 983
 984                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 985                         if (dimm_num == 0) {
 986                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 987                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 988                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
 989                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
 990                                 if (registered == 1) { /* DDR2 always buffered */
 991                                         /* TODO: what about above  comments ? */
 992                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
 993                                         buf0 = TRUE;
 994                                 } else {
 995                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
 996                                         if ((attribute & 0x02) == 0x00) {
 997                                                 /* buffered not supported */
 998                                                 buf0 = FALSE;
 999                                         } else {
1000                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1001                                                 buf0 = TRUE;
1002                                         }
1003                                 }
1004                         }
1005                         else if (dimm_num == 1) {
1006                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1007                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1008                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1009                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1010                                 if (registered == 1) {
1011                                         /* DDR2 always buffered */
1012                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1013                                         buf1 = TRUE;
1014                                 } else {
1015                                         if ((attribute & 0x02) == 0x00) {
1016                                                 /* buffered not supported */
1017                                                 buf1 = FALSE;
1018                                         } else {
1019                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1020                                                 buf1 = TRUE;
1021                                         }
1022                                 }
1023                         }
1024
1025                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1026                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1027                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1028
1029                         switch (data_width) {
1030                         case 72:
1031                         case 64:
1032                                 dimm_64bit = TRUE;
1033                                 break;
1034                         case 40:
1035                         case 32:
1036                                 dimm_32bit = TRUE;
1037                                 break;
1038                         default:
1039                                 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
1040                                        data_width);
1041                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1042                                 break;
1043                         }
1044                 }
1045         }
1046
1047         /* verify matching properties */
1048         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1049                 if (buf0 != buf1) {
1050                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1051                         spd_ddr_init_hang ();
1052                 }
1053         }
1054
1055         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1056                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1057                 spd_ddr_init_hang ();
1058         }
1059         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1060                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1061         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1062                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1063         } else {
1064                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1065                 spd_ddr_init_hang ();
1066         }
1067
1068         if (ecc_enabled == TRUE)
1069                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1070         else
1071                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1072
1073         mtsdram(SDRAM_MCOPT1, mcopt1);
1074 }
1075
1076 /*-----------------------------------------------------------------------------+
1077  * program_codt.
1078  *-----------------------------------------------------------------------------*/
1079 static void program_codt(unsigned long *dimm_populated,
1080                          unsigned char *iic0_dimm_addr,
1081                          unsigned long num_dimm_banks)
1082 {
1083         unsigned long codt;
1084         unsigned long modt0 = 0;
1085         unsigned long modt1 = 0;
1086         unsigned long modt2 = 0;
1087         unsigned long modt3 = 0;
1088         unsigned char dimm_num;
1089         unsigned char dimm_rank;
1090         unsigned char total_rank = 0;
1091         unsigned char total_dimm = 0;
1092         unsigned char dimm_type = 0;
1093         unsigned char firstSlot = 0;
1094
1095         /*------------------------------------------------------------------
1096          * Set the SDRAM Controller On Die Termination Register
1097          *-----------------------------------------------------------------*/
1098         mfsdram(SDRAM_CODT, codt);
1099         codt |= (SDRAM_CODT_IO_NMODE
1100                  & (~SDRAM_CODT_DQS_SINGLE_END
1101                     & ~SDRAM_CODT_CKSE_SINGLE_END
1102                     & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1103                     & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1104
1105         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1106                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1107                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1108                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1109                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1110                                 dimm_type = SDRAM_DDR2;
1111                         } else {
1112                                 dimm_rank = dimm_rank & 0x0F;
1113                                 dimm_type = SDRAM_DDR1;
1114                         }
1115
1116                         total_rank += dimm_rank;
1117                         total_dimm++;
1118                         if ((dimm_num == 0) && (total_dimm == 1))
1119                                 firstSlot = TRUE;
1120                         else
1121                                 firstSlot = FALSE;
1122                 }
1123         }
1124         if (dimm_type == SDRAM_DDR2) {
1125                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1126                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1127                         if (total_rank == 1) {
1128                                 codt |= CALC_ODT_R(0);
1129                                 modt0 = CALC_ODT_W(0);
1130                                 modt1 = 0x00000000;
1131                                 modt2 = 0x00000000;
1132                                 modt3 = 0x00000000;
1133                         }
1134                         if (total_rank == 2) {
1135                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1136                                 modt0 = CALC_ODT_W(0);
1137                                 modt1 = CALC_ODT_W(0);
1138                                 modt2 = 0x00000000;
1139                                 modt3 = 0x00000000;
1140                         }
1141                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1142                         if (total_rank == 1) {
1143                                 codt |= CALC_ODT_R(2);
1144                                 modt0 = 0x00000000;
1145                                 modt1 = 0x00000000;
1146                                 modt2 = CALC_ODT_W(2);
1147                                 modt3 = 0x00000000;
1148                         }
1149                         if (total_rank == 2) {
1150                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1151                                 modt0 = 0x00000000;
1152                                 modt1 = 0x00000000;
1153                                 modt2 = CALC_ODT_W(2);
1154                                 modt3 = CALC_ODT_W(2);
1155                         }
1156                 }
1157                 if (total_dimm == 2) {
1158                         if (total_rank == 2) {
1159                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1160                                 modt0 = CALC_ODT_RW(2);
1161                                 modt1 = 0x00000000;
1162                                 modt2 = CALC_ODT_RW(0);
1163                                 modt3 = 0x00000000;
1164                         }
1165                         if (total_rank == 4) {
1166                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1167                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1168                                 modt0 = CALC_ODT_RW(2);
1169                                 modt1 = 0x00000000;
1170                                 modt2 = CALC_ODT_RW(0);
1171                                 modt3 = 0x00000000;
1172                         }
1173                 }
1174         } else {
1175                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1176                 modt0 = 0x00000000;
1177                 modt1 = 0x00000000;
1178                 modt2 = 0x00000000;
1179                 modt3 = 0x00000000;
1180
1181                 if (total_dimm == 1) {
1182                         if (total_rank == 1)
1183                                 codt |= 0x00800000;
1184                         if (total_rank == 2)
1185                                 codt |= 0x02800000;
1186                 }
1187                 if (total_dimm == 2) {
1188                         if (total_rank == 2)
1189                                 codt |= 0x08800000;
1190                         if (total_rank == 4)
1191                                 codt |= 0x2a800000;
1192                 }
1193         }
1194
1195         debug("nb of dimm %d\n", total_dimm);
1196         debug("nb of rank %d\n", total_rank);
1197         if (total_dimm == 1)
1198                 debug("dimm in slot %d\n", firstSlot);
1199
1200         mtsdram(SDRAM_CODT, codt);
1201         mtsdram(SDRAM_MODT0, modt0);
1202         mtsdram(SDRAM_MODT1, modt1);
1203         mtsdram(SDRAM_MODT2, modt2);
1204         mtsdram(SDRAM_MODT3, modt3);
1205 }
1206
1207 /*-----------------------------------------------------------------------------+
1208  * program_initplr.
1209  *-----------------------------------------------------------------------------*/
1210 static void program_initplr(unsigned long *dimm_populated,
1211                             unsigned char *iic0_dimm_addr,
1212                             unsigned long num_dimm_banks,
1213                             ddr_cas_id_t selected_cas,
1214                             int write_recovery)
1215 {
1216         u32 cas = 0;
1217         u32 odt = 0;
1218         u32 ods = 0;
1219         u32 mr;
1220         u32 wr;
1221         u32 emr;
1222         u32 emr2;
1223         u32 emr3;
1224         int dimm_num;
1225         int total_dimm = 0;
1226
1227         /******************************************************
1228          ** Assumption: if more than one DIMM, all DIMMs are the same
1229          **             as already checked in check_memory_type
1230          ******************************************************/
1231
1232         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1233                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1234                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1235                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1236                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1237                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1238                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1239                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1240                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1241         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1242                 switch (selected_cas) {
1243                 case DDR_CAS_3:
1244                         cas = 3 << 4;
1245                         break;
1246                 case DDR_CAS_4:
1247                         cas = 4 << 4;
1248                         break;
1249                 case DDR_CAS_5:
1250                         cas = 5 << 4;
1251                         break;
1252                 default:
1253                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1254                         spd_ddr_init_hang ();
1255                         break;
1256                 }
1257
1258 #if 0
1259                 /*
1260                  * ToDo - Still a problem with the write recovery:
1261                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1262                  * in the INITPLR reg to the value calculated in program_mode()
1263                  * results in not correctly working DDR2 memory (crash after
1264                  * relocation).
1265                  *
1266                  * So for now, set the write recovery to 3. This seems to work
1267                  * on the Corair module too.
1268                  *
1269                  * 2007-03-01, sr
1270                  */
1271                 switch (write_recovery) {
1272                 case 3:
1273                         wr = WRITE_RECOV_3;
1274                         break;
1275                 case 4:
1276                         wr = WRITE_RECOV_4;
1277                         break;
1278                 case 5:
1279                         wr = WRITE_RECOV_5;
1280                         break;
1281                 case 6:
1282                         wr = WRITE_RECOV_6;
1283                         break;
1284                 default:
1285                         printf("ERROR: write recovery not support (%d)", write_recovery);
1286                         spd_ddr_init_hang ();
1287                         break;
1288                 }
1289 #else
1290                 wr = WRITE_RECOV_3; /* test-only, see description above */
1291 #endif
1292
1293                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1294                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1295                                 total_dimm++;
1296                 if (total_dimm == 1) {
1297                         odt = ODT_150_OHM;
1298                         ods = ODS_FULL;
1299                 } else if (total_dimm == 2) {
1300                         odt = ODT_75_OHM;
1301                         ods = ODS_REDUCED;
1302                 } else {
1303                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1304                         spd_ddr_init_hang ();
1305                 }
1306
1307                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1308                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1309                 emr2 = CMD_EMR | SELECT_EMR2;
1310                 emr3 = CMD_EMR | SELECT_EMR3;
1311                 mtsdram(SDRAM_INITPLR0,  0xB5000000 | CMD_NOP);         /* NOP */
1312                 udelay(1000);
1313                 mtsdram(SDRAM_INITPLR1,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1314                 mtsdram(SDRAM_INITPLR2,  0x80800000 | emr2);            /* EMR2 */
1315                 mtsdram(SDRAM_INITPLR3,  0x80800000 | emr3);            /* EMR3 */
1316                 mtsdram(SDRAM_INITPLR4,  0x80800000 | emr);             /* EMR DLL ENABLE */
1317                 mtsdram(SDRAM_INITPLR5,  0x80800000 | mr | DLL_RESET);  /* MR w/ DLL reset */
1318                 udelay(1000);
1319                 mtsdram(SDRAM_INITPLR6,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1320                 mtsdram(SDRAM_INITPLR7,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1321                 mtsdram(SDRAM_INITPLR8,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1322                 mtsdram(SDRAM_INITPLR9,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1323                 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1324                 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr);              /* MR w/o DLL reset */
1325                 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr);             /* EMR OCD Default */
1326                 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr);             /* EMR OCD Exit */
1327         } else {
1328                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1329                 spd_ddr_init_hang ();
1330         }
1331 }
1332
1333 /*------------------------------------------------------------------
1334  * This routine programs the SDRAM_MMODE register.
1335  * the selected_cas is an output parameter, that will be passed
1336  * by caller to call the above program_initplr( )
1337  *-----------------------------------------------------------------*/
1338 static void program_mode(unsigned long *dimm_populated,
1339                          unsigned char *iic0_dimm_addr,
1340                          unsigned long num_dimm_banks,
1341                          ddr_cas_id_t *selected_cas,
1342                          int *write_recovery)
1343 {
1344         unsigned long dimm_num;
1345         unsigned long sdram_ddr1;
1346         unsigned long t_wr_ns;
1347         unsigned long t_wr_clk;
1348         unsigned long cas_bit;
1349         unsigned long cas_index;
1350         unsigned long sdram_freq;
1351         unsigned long ddr_check;
1352         unsigned long mmode;
1353         unsigned long tcyc_reg;
1354         unsigned long cycle_2_0_clk;
1355         unsigned long cycle_2_5_clk;
1356         unsigned long cycle_3_0_clk;
1357         unsigned long cycle_4_0_clk;
1358         unsigned long cycle_5_0_clk;
1359         unsigned long max_2_0_tcyc_ns_x_100;
1360         unsigned long max_2_5_tcyc_ns_x_100;
1361         unsigned long max_3_0_tcyc_ns_x_100;
1362         unsigned long max_4_0_tcyc_ns_x_100;
1363         unsigned long max_5_0_tcyc_ns_x_100;
1364         unsigned long cycle_time_ns_x_100[3];
1365         PPC4xx_SYS_INFO board_cfg;
1366         unsigned char cas_2_0_available;
1367         unsigned char cas_2_5_available;
1368         unsigned char cas_3_0_available;
1369         unsigned char cas_4_0_available;
1370         unsigned char cas_5_0_available;
1371         unsigned long sdr_ddrpll;
1372
1373         /*------------------------------------------------------------------
1374          * Get the board configuration info.
1375          *-----------------------------------------------------------------*/
1376         get_sys_info(&board_cfg);
1377
1378         mfsdr(SDR0_DDR0, sdr_ddrpll);
1379         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1380         debug("sdram_freq=%d\n", sdram_freq);
1381
1382         /*------------------------------------------------------------------
1383          * Handle the timing.  We need to find the worst case timing of all
1384          * the dimm modules installed.
1385          *-----------------------------------------------------------------*/
1386         t_wr_ns = 0;
1387         cas_2_0_available = TRUE;
1388         cas_2_5_available = TRUE;
1389         cas_3_0_available = TRUE;
1390         cas_4_0_available = TRUE;
1391         cas_5_0_available = TRUE;
1392         max_2_0_tcyc_ns_x_100 = 10;
1393         max_2_5_tcyc_ns_x_100 = 10;
1394         max_3_0_tcyc_ns_x_100 = 10;
1395         max_4_0_tcyc_ns_x_100 = 10;
1396         max_5_0_tcyc_ns_x_100 = 10;
1397         sdram_ddr1 = TRUE;
1398
1399         /* loop through all the DIMM slots on the board */
1400         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1401                 /* If a dimm is installed in a particular slot ... */
1402                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1403                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1404                                 sdram_ddr1 = TRUE;
1405                         else
1406                                 sdram_ddr1 = FALSE;
1407
1408                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1409                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1410                         debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1411
1412                         /* For a particular DIMM, grab the three CAS values it supports */
1413                         for (cas_index = 0; cas_index < 3; cas_index++) {
1414                                 switch (cas_index) {
1415                                 case 0:
1416                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1417                                         break;
1418                                 case 1:
1419                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1420                                         break;
1421                                 default:
1422                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1423                                         break;
1424                                 }
1425
1426                                 if ((tcyc_reg & 0x0F) >= 10) {
1427                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1428                                                 /* Convert from hex to decimal */
1429                                                 cycle_time_ns_x_100[cas_index] =
1430                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1431                                         } else {
1432                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1433                                                        "in slot %d\n", (unsigned int)dimm_num);
1434                                                 spd_ddr_init_hang ();
1435                                         }
1436                                 } else {
1437                                         /* Convert from hex to decimal */
1438                                         cycle_time_ns_x_100[cas_index] =
1439                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1440                                                 ((tcyc_reg & 0x0F)*10);
1441                                 }
1442                                 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1443                                       cycle_time_ns_x_100[cas_index]);
1444                         }
1445
1446                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1447                         /* supported for a particular DIMM. */
1448                         cas_index = 0;
1449
1450                         if (sdram_ddr1) {
1451                                 /*
1452                                  * DDR devices use the following bitmask for CAS latency:
1453                                  *  Bit   7    6    5    4    3    2    1    0
1454                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1455                                  */
1456                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1457                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1458                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1459                                                                     cycle_time_ns_x_100[cas_index]);
1460                                         cas_index++;
1461                                 } else {
1462                                         if (cas_index != 0)
1463                                                 cas_index++;
1464                                         cas_4_0_available = FALSE;
1465                                 }
1466
1467                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1468                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1469                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1470                                                                     cycle_time_ns_x_100[cas_index]);
1471                                         cas_index++;
1472                                 } else {
1473                                         if (cas_index != 0)
1474                                                 cas_index++;
1475                                         cas_3_0_available = FALSE;
1476                                 }
1477
1478                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1479                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1480                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1481                                                                     cycle_time_ns_x_100[cas_index]);
1482                                         cas_index++;
1483                                 } else {
1484                                         if (cas_index != 0)
1485                                                 cas_index++;
1486                                         cas_2_5_available = FALSE;
1487                                 }
1488
1489                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1490                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1491                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1492                                                                     cycle_time_ns_x_100[cas_index]);
1493                                         cas_index++;
1494                                 } else {
1495                                         if (cas_index != 0)
1496                                                 cas_index++;
1497                                         cas_2_0_available = FALSE;
1498                                 }
1499                         } else {
1500                                 /*
1501                                  * DDR2 devices use the following bitmask for CAS latency:
1502                                  *  Bit   7    6    5    4    3    2    1    0
1503                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1504                                  */
1505                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1506                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1507                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1508                                                                     cycle_time_ns_x_100[cas_index]);
1509                                         cas_index++;
1510                                 } else {
1511                                         if (cas_index != 0)
1512                                                 cas_index++;
1513                                         cas_5_0_available = FALSE;
1514                                 }
1515
1516                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1517                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1518                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1519                                                                     cycle_time_ns_x_100[cas_index]);
1520                                         cas_index++;
1521                                 } else {
1522                                         if (cas_index != 0)
1523                                                 cas_index++;
1524                                         cas_4_0_available = FALSE;
1525                                 }
1526
1527                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1528                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1529                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1530                                                                     cycle_time_ns_x_100[cas_index]);
1531                                         cas_index++;
1532                                 } else {
1533                                         if (cas_index != 0)
1534                                                 cas_index++;
1535                                         cas_3_0_available = FALSE;
1536                                 }
1537                         }
1538                 }
1539         }
1540
1541         /*------------------------------------------------------------------
1542          * Set the SDRAM mode, SDRAM_MMODE
1543          *-----------------------------------------------------------------*/
1544         mfsdram(SDRAM_MMODE, mmode);
1545         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1546
1547         /* add 10 here because of rounding problems */
1548         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1549         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1550         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1551         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1552         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1553         debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1554         debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1555         debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1556
1557         if (sdram_ddr1 == TRUE) { /* DDR1 */
1558                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1559                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1560                         *selected_cas = DDR_CAS_2;
1561                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1562                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1563                         *selected_cas = DDR_CAS_2_5;
1564                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1565                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1566                         *selected_cas = DDR_CAS_3;
1567                 } else {
1568                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1569                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1570                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1571                         spd_ddr_init_hang ();
1572                 }
1573         } else { /* DDR2 */
1574                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1575                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1576                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1577                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1578                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1579                         *selected_cas = DDR_CAS_3;
1580                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1581                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1582                         *selected_cas = DDR_CAS_4;
1583                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1584                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1585                         *selected_cas = DDR_CAS_5;
1586                 } else {
1587                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1588                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1589                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1590                         printf("cas3=%d cas4=%d cas5=%d\n",
1591                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1592                         printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1593                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1594                         spd_ddr_init_hang ();
1595                 }
1596         }
1597
1598         if (sdram_ddr1 == TRUE)
1599                 mmode |= SDRAM_MMODE_WR_DDR1;
1600         else {
1601
1602                 /* loop through all the DIMM slots on the board */
1603                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1604                         /* If a dimm is installed in a particular slot ... */
1605                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1606                                 t_wr_ns = max(t_wr_ns,
1607                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1608                 }
1609
1610                 /*
1611                  * convert from nanoseconds to ddr clocks
1612                  * round up if necessary
1613                  */
1614                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1615                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1616                 if (sdram_freq != ddr_check)
1617                         t_wr_clk++;
1618
1619                 switch (t_wr_clk) {
1620                 case 0:
1621                 case 1:
1622                 case 2:
1623                 case 3:
1624                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1625                         break;
1626                 case 4:
1627                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1628                         break;
1629                 case 5:
1630                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1631                         break;
1632                 default:
1633                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1634                         break;
1635                 }
1636                 *write_recovery = t_wr_clk;
1637         }
1638
1639         debug("CAS latency = %d\n", *selected_cas);
1640         debug("Write recovery = %d\n", *write_recovery);
1641
1642         mtsdram(SDRAM_MMODE, mmode);
1643 }
1644
1645 /*-----------------------------------------------------------------------------+
1646  * program_rtr.
1647  *-----------------------------------------------------------------------------*/
1648 static void program_rtr(unsigned long *dimm_populated,
1649                         unsigned char *iic0_dimm_addr,
1650                         unsigned long num_dimm_banks)
1651 {
1652         PPC4xx_SYS_INFO board_cfg;
1653         unsigned long max_refresh_rate;
1654         unsigned long dimm_num;
1655         unsigned long refresh_rate_type;
1656         unsigned long refresh_rate;
1657         unsigned long rint;
1658         unsigned long sdram_freq;
1659         unsigned long sdr_ddrpll;
1660         unsigned long val;
1661
1662         /*------------------------------------------------------------------
1663          * Get the board configuration info.
1664          *-----------------------------------------------------------------*/
1665         get_sys_info(&board_cfg);
1666
1667         /*------------------------------------------------------------------
1668          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1669          *-----------------------------------------------------------------*/
1670         mfsdr(SDR0_DDR0, sdr_ddrpll);
1671         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1672
1673         max_refresh_rate = 0;
1674         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1675                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1676
1677                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1678                         refresh_rate_type &= 0x7F;
1679                         switch (refresh_rate_type) {
1680                         case 0:
1681                                 refresh_rate =  15625;
1682                                 break;
1683                         case 1:
1684                                 refresh_rate =   3906;
1685                                 break;
1686                         case 2:
1687                                 refresh_rate =   7812;
1688                                 break;
1689                         case 3:
1690                                 refresh_rate =  31250;
1691                                 break;
1692                         case 4:
1693                                 refresh_rate =  62500;
1694                                 break;
1695                         case 5:
1696                                 refresh_rate = 125000;
1697                                 break;
1698                         default:
1699                                 refresh_rate = 0;
1700                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1701                                        (unsigned int)dimm_num);
1702                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1703                                 spd_ddr_init_hang ();
1704                                 break;
1705                         }
1706
1707                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1708                 }
1709         }
1710
1711         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1712         mfsdram(SDRAM_RTR, val);
1713         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1714                 (SDRAM_RTR_RINT_ENCODE(rint)));
1715 }
1716
1717 /*------------------------------------------------------------------
1718  * This routine programs the SDRAM_TRx registers.
1719  *-----------------------------------------------------------------*/
1720 static void program_tr(unsigned long *dimm_populated,
1721                        unsigned char *iic0_dimm_addr,
1722                        unsigned long num_dimm_banks)
1723 {
1724         unsigned long dimm_num;
1725         unsigned long sdram_ddr1;
1726         unsigned long t_rp_ns;
1727         unsigned long t_rcd_ns;
1728         unsigned long t_rrd_ns;
1729         unsigned long t_ras_ns;
1730         unsigned long t_rc_ns;
1731         unsigned long t_rfc_ns;
1732         unsigned long t_wpc_ns;
1733         unsigned long t_wtr_ns;
1734         unsigned long t_rpc_ns;
1735         unsigned long t_rp_clk;
1736         unsigned long t_rcd_clk;
1737         unsigned long t_rrd_clk;
1738         unsigned long t_ras_clk;
1739         unsigned long t_rc_clk;
1740         unsigned long t_rfc_clk;
1741         unsigned long t_wpc_clk;
1742         unsigned long t_wtr_clk;
1743         unsigned long t_rpc_clk;
1744         unsigned long sdtr1, sdtr2, sdtr3;
1745         unsigned long ddr_check;
1746         unsigned long sdram_freq;
1747         unsigned long sdr_ddrpll;
1748
1749         PPC4xx_SYS_INFO board_cfg;
1750
1751         /*------------------------------------------------------------------
1752          * Get the board configuration info.
1753          *-----------------------------------------------------------------*/
1754         get_sys_info(&board_cfg);
1755
1756         mfsdr(SDR0_DDR0, sdr_ddrpll);
1757         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1758
1759         /*------------------------------------------------------------------
1760          * Handle the timing.  We need to find the worst case timing of all
1761          * the dimm modules installed.
1762          *-----------------------------------------------------------------*/
1763         t_rp_ns = 0;
1764         t_rrd_ns = 0;
1765         t_rcd_ns = 0;
1766         t_ras_ns = 0;
1767         t_rc_ns = 0;
1768         t_rfc_ns = 0;
1769         t_wpc_ns = 0;
1770         t_wtr_ns = 0;
1771         t_rpc_ns = 0;
1772         sdram_ddr1 = TRUE;
1773
1774         /* loop through all the DIMM slots on the board */
1775         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1776                 /* If a dimm is installed in a particular slot ... */
1777                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1778                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1779                                 sdram_ddr1 = TRUE;
1780                         else
1781                                 sdram_ddr1 = FALSE;
1782
1783                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1784                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1785                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1786                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1787                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1788                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1789                 }
1790         }
1791
1792         /*------------------------------------------------------------------
1793          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1794          *-----------------------------------------------------------------*/
1795         mfsdram(SDRAM_SDTR1, sdtr1);
1796         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1797                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1798
1799         /* default values */
1800         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1801         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1802
1803         /* normal operations */
1804         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1805         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1806
1807         mtsdram(SDRAM_SDTR1, sdtr1);
1808
1809         /*------------------------------------------------------------------
1810          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1811          *-----------------------------------------------------------------*/
1812         mfsdram(SDRAM_SDTR2, sdtr2);
1813         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1814                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1815                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1816                    SDRAM_SDTR2_RRD_MASK);
1817
1818         /*
1819          * convert t_rcd from nanoseconds to ddr clocks
1820          * round up if necessary
1821          */
1822         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1823         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1824         if (sdram_freq != ddr_check)
1825                 t_rcd_clk++;
1826
1827         switch (t_rcd_clk) {
1828         case 0:
1829         case 1:
1830                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1831                 break;
1832         case 2:
1833                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1834                 break;
1835         case 3:
1836                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1837                 break;
1838         case 4:
1839                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1840                 break;
1841         default:
1842                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1843                 break;
1844         }
1845
1846         if (sdram_ddr1 == TRUE) { /* DDR1 */
1847                 if (sdram_freq < 200000000) {
1848                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1849                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1850                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1851                 } else {
1852                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1853                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1854                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1855                 }
1856         } else { /* DDR2 */
1857                 /* loop through all the DIMM slots on the board */
1858                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1859                         /* If a dimm is installed in a particular slot ... */
1860                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1861                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1862                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1863                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1864                         }
1865                 }
1866
1867                 /*
1868                  * convert from nanoseconds to ddr clocks
1869                  * round up if necessary
1870                  */
1871                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1872                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1873                 if (sdram_freq != ddr_check)
1874                         t_wpc_clk++;
1875
1876                 switch (t_wpc_clk) {
1877                 case 0:
1878                 case 1:
1879                 case 2:
1880                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1881                         break;
1882                 case 3:
1883                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1884                         break;
1885                 case 4:
1886                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1887                         break;
1888                 case 5:
1889                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1890                         break;
1891                 default:
1892                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1893                         break;
1894                 }
1895
1896                 /*
1897                  * convert from nanoseconds to ddr clocks
1898                  * round up if necessary
1899                  */
1900                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1901                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1902                 if (sdram_freq != ddr_check)
1903                         t_wtr_clk++;
1904
1905                 switch (t_wtr_clk) {
1906                 case 0:
1907                 case 1:
1908                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1909                         break;
1910                 case 2:
1911                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1912                         break;
1913                 case 3:
1914                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1915                         break;
1916                 default:
1917                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1918                         break;
1919                 }
1920
1921                 /*
1922                  * convert from nanoseconds to ddr clocks
1923                  * round up if necessary
1924                  */
1925                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1926                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1927                 if (sdram_freq != ddr_check)
1928                         t_rpc_clk++;
1929
1930                 switch (t_rpc_clk) {
1931                 case 0:
1932                 case 1:
1933                 case 2:
1934                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1935                         break;
1936                 case 3:
1937                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1938                         break;
1939                 default:
1940                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1941                         break;
1942                 }
1943         }
1944
1945         /* default value */
1946         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1947
1948         /*
1949          * convert t_rrd from nanoseconds to ddr clocks
1950          * round up if necessary
1951          */
1952         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1953         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1954         if (sdram_freq != ddr_check)
1955                 t_rrd_clk++;
1956
1957         if (t_rrd_clk == 3)
1958                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1959         else
1960                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1961
1962         /*
1963          * convert t_rp from nanoseconds to ddr clocks
1964          * round up if necessary
1965          */
1966         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1967         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1968         if (sdram_freq != ddr_check)
1969                 t_rp_clk++;
1970
1971         switch (t_rp_clk) {
1972         case 0:
1973         case 1:
1974         case 2:
1975         case 3:
1976                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1977                 break;
1978         case 4:
1979                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1980                 break;
1981         case 5:
1982                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1983                 break;
1984         case 6:
1985                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1986                 break;
1987         default:
1988                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1989                 break;
1990         }
1991
1992         mtsdram(SDRAM_SDTR2, sdtr2);
1993
1994         /*------------------------------------------------------------------
1995          * Set the SDRAM Timing Reg 3, SDRAM_TR3
1996          *-----------------------------------------------------------------*/
1997         mfsdram(SDRAM_SDTR3, sdtr3);
1998         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
1999                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2000
2001         /*
2002          * convert t_ras from nanoseconds to ddr clocks
2003          * round up if necessary
2004          */
2005         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2006         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2007         if (sdram_freq != ddr_check)
2008                 t_ras_clk++;
2009
2010         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2011
2012         /*
2013          * convert t_rc from nanoseconds to ddr clocks
2014          * round up if necessary
2015          */
2016         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2017         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2018         if (sdram_freq != ddr_check)
2019                 t_rc_clk++;
2020
2021         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2022
2023         /* default xcs value */
2024         sdtr3 |= SDRAM_SDTR3_XCS;
2025
2026         /*
2027          * convert t_rfc from nanoseconds to ddr clocks
2028          * round up if necessary
2029          */
2030         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2031         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2032         if (sdram_freq != ddr_check)
2033                 t_rfc_clk++;
2034
2035         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2036
2037         mtsdram(SDRAM_SDTR3, sdtr3);
2038 }
2039
2040 /*-----------------------------------------------------------------------------+
2041  * program_bxcf.
2042  *-----------------------------------------------------------------------------*/
2043 static void program_bxcf(unsigned long *dimm_populated,
2044                          unsigned char *iic0_dimm_addr,
2045                          unsigned long num_dimm_banks)
2046 {
2047         unsigned long dimm_num;
2048         unsigned long num_col_addr;
2049         unsigned long num_ranks;
2050         unsigned long num_banks;
2051         unsigned long mode;
2052         unsigned long ind_rank;
2053         unsigned long ind;
2054         unsigned long ind_bank;
2055         unsigned long bank_0_populated;
2056
2057         /*------------------------------------------------------------------
2058          * Set the BxCF regs.  First, wipe out the bank config registers.
2059          *-----------------------------------------------------------------*/
2060         mtsdram(SDRAM_MB0CF, 0x00000000);
2061         mtsdram(SDRAM_MB1CF, 0x00000000);
2062         mtsdram(SDRAM_MB2CF, 0x00000000);
2063         mtsdram(SDRAM_MB3CF, 0x00000000);
2064
2065         mode = SDRAM_BXCF_M_BE_ENABLE;
2066
2067         bank_0_populated = 0;
2068
2069         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2070                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2071                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2072                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2073                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2074                                 num_ranks = (num_ranks & 0x0F) +1;
2075                         else
2076                                 num_ranks = num_ranks & 0x0F;
2077
2078                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2079
2080                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2081                                 if (num_banks == 4)
2082                                         ind = 0;
2083                                 else
2084                                         ind = 5 << 8;
2085                                 switch (num_col_addr) {
2086                                 case 0x08:
2087                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2088                                         break;
2089                                 case 0x09:
2090                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2091                                         break;
2092                                 case 0x0A:
2093                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2094                                         break;
2095                                 case 0x0B:
2096                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2097                                         break;
2098                                 case 0x0C:
2099                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2100                                         break;
2101                                 default:
2102                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2103                                                (unsigned int)dimm_num);
2104                                         printf("ERROR: Unsupported value for number of "
2105                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2106                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2107                                         spd_ddr_init_hang ();
2108                                 }
2109                         }
2110
2111                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2112                                 bank_0_populated = 1;
2113
2114                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2115                                 mtsdram(SDRAM_MB0CF +
2116                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2117                                         mode);
2118                         }
2119                 }
2120         }
2121 }
2122
2123 /*------------------------------------------------------------------
2124  * program memory queue.
2125  *-----------------------------------------------------------------*/
2126 static void program_memory_queue(unsigned long *dimm_populated,
2127                                  unsigned char *iic0_dimm_addr,
2128                                  unsigned long num_dimm_banks)
2129 {
2130         unsigned long dimm_num;
2131         unsigned long rank_base_addr;
2132         unsigned long rank_reg;
2133         unsigned long rank_size_bytes;
2134         unsigned long rank_size_id;
2135         unsigned long num_ranks;
2136         unsigned long baseadd_size;
2137         unsigned long i;
2138         unsigned long bank_0_populated = 0;
2139         unsigned long total_size = 0;
2140
2141         /*------------------------------------------------------------------
2142          * Reset the rank_base_address.
2143          *-----------------------------------------------------------------*/
2144         rank_reg   = SDRAM_R0BAS;
2145
2146         rank_base_addr = 0x00000000;
2147
2148         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2149                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2150                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2151                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2152                                 num_ranks = (num_ranks & 0x0F) + 1;
2153                         else
2154                                 num_ranks = num_ranks & 0x0F;
2155
2156                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2157
2158                         /*------------------------------------------------------------------
2159                          * Set the sizes
2160                          *-----------------------------------------------------------------*/
2161                         baseadd_size = 0;
2162                         switch (rank_size_id) {
2163                         case 0x01:
2164                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2165                                 total_size = 1024;
2166                                 break;
2167                         case 0x02:
2168                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2169                                 total_size = 2048;
2170                                 break;
2171                         case 0x04:
2172                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2173                                 total_size = 4096;
2174                                 break;
2175                         case 0x08:
2176                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2177                                 total_size = 32;
2178                                 break;
2179                         case 0x10:
2180                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2181                                 total_size = 64;
2182                                 break;
2183                         case 0x20:
2184                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2185                                 total_size = 128;
2186                                 break;
2187                         case 0x40:
2188                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2189                                 total_size = 256;
2190                                 break;
2191                         case 0x80:
2192                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2193                                 total_size = 512;
2194                                 break;
2195                         default:
2196                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2197                                        (unsigned int)dimm_num);
2198                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2199                                        (unsigned int)rank_size_id);
2200                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2201                                 spd_ddr_init_hang ();
2202                         }
2203                         rank_size_bytes = total_size << 20;
2204
2205                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2206                                 bank_0_populated = 1;
2207
2208                         for (i = 0; i < num_ranks; i++) {
2209                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2210                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2211                                            baseadd_size));
2212                                 rank_base_addr += rank_size_bytes;
2213                         }
2214                 }
2215         }
2216
2217 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
2218         /*
2219          * Enable high bandwidth access on 460EX/GT.
2220          * This should/could probably be done on other
2221          * PPC's too, like 440SPe.
2222          * This is currently not used, but with this setup
2223          * it is possible to use it later on in e.g. the Linux
2224          * EMAC driver for performance gain.
2225          */
2226         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2227         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2228 #endif
2229 }
2230
2231 /*-----------------------------------------------------------------------------+
2232  * is_ecc_enabled.
2233  *-----------------------------------------------------------------------------*/
2234 static unsigned long is_ecc_enabled(void)
2235 {
2236         unsigned long dimm_num;
2237         unsigned long ecc;
2238         unsigned long val;
2239
2240         ecc = 0;
2241         /* loop through all the DIMM slots on the board */
2242         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2243                 mfsdram(SDRAM_MCOPT1, val);
2244                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2245         }
2246
2247         return ecc;
2248 }
2249
2250 static void blank_string(int size)
2251 {
2252         int i;
2253
2254         for (i=0; i<size; i++)
2255                 putc('\b');
2256         for (i=0; i<size; i++)
2257                 putc(' ');
2258         for (i=0; i<size; i++)
2259                 putc('\b');
2260 }
2261
2262 #ifdef CONFIG_DDR_ECC
2263 /*-----------------------------------------------------------------------------+
2264  * program_ecc.
2265  *-----------------------------------------------------------------------------*/
2266 static void program_ecc(unsigned long *dimm_populated,
2267                         unsigned char *iic0_dimm_addr,
2268                         unsigned long num_dimm_banks,
2269                         unsigned long tlb_word2_i_value)
2270 {
2271         unsigned long mcopt1;
2272         unsigned long mcopt2;
2273         unsigned long mcstat;
2274         unsigned long dimm_num;
2275         unsigned long ecc;
2276
2277         ecc = 0;
2278         /* loop through all the DIMM slots on the board */
2279         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2280                 /* If a dimm is installed in a particular slot ... */
2281                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2282                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2283         }
2284         if (ecc == 0)
2285                 return;
2286
2287         mfsdram(SDRAM_MCOPT1, mcopt1);
2288         mfsdram(SDRAM_MCOPT2, mcopt2);
2289
2290         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2291                 /* DDR controller must be enabled and not in self-refresh. */
2292                 mfsdram(SDRAM_MCSTAT, mcstat);
2293                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2294                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2295                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2296                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2297
2298                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2299                 }
2300         }
2301
2302         return;
2303 }
2304
2305 static void wait_ddr_idle(void)
2306 {
2307         u32 val;
2308
2309         do {
2310                 mfsdram(SDRAM_MCSTAT, val);
2311         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2312 }
2313
2314 /*-----------------------------------------------------------------------------+
2315  * program_ecc_addr.
2316  *-----------------------------------------------------------------------------*/
2317 static void program_ecc_addr(unsigned long start_address,
2318                              unsigned long num_bytes,
2319                              unsigned long tlb_word2_i_value)
2320 {
2321         unsigned long current_address;
2322         unsigned long end_address;
2323         unsigned long address_increment;
2324         unsigned long mcopt1;
2325         char str[] = "ECC generation -";
2326         char slash[] = "\\|/-\\|/-";
2327         int loop = 0;
2328         int loopi = 0;
2329
2330         current_address = start_address;
2331         mfsdram(SDRAM_MCOPT1, mcopt1);
2332         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2333                 mtsdram(SDRAM_MCOPT1,
2334                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2335                 sync();
2336                 eieio();
2337                 wait_ddr_idle();
2338
2339                 puts(str);
2340                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2341                         /* ECC bit set method for non-cached memory */
2342                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2343                                 address_increment = 4;
2344                         else
2345                                 address_increment = 8;
2346                         end_address = current_address + num_bytes;
2347
2348                         while (current_address < end_address) {
2349                                 *((unsigned long *)current_address) = 0x00000000;
2350                                 current_address += address_increment;
2351
2352                                 if ((loop++ % (2 << 20)) == 0) {
2353                                         putc('\b');
2354                                         putc(slash[loopi++ % 8]);
2355                                 }
2356                         }
2357
2358                 } else {
2359                         /* ECC bit set method for cached memory */
2360                         dcbz_area(start_address, num_bytes);
2361                         /* Write modified dcache lines back to memory */
2362                         clean_dcache_range(start_address, start_address + num_bytes);
2363                 }
2364
2365                 blank_string(strlen(str));
2366
2367                 sync();
2368                 eieio();
2369                 wait_ddr_idle();
2370
2371                 /* clear ECC error repoting registers */
2372                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2373                 mtdcr(0x4c, 0xffffffff);
2374
2375                 mtsdram(SDRAM_MCOPT1,
2376                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2377                 sync();
2378                 eieio();
2379                 wait_ddr_idle();
2380         }
2381 }
2382 #endif
2383
2384 /*-----------------------------------------------------------------------------+
2385  * program_DQS_calibration.
2386  *-----------------------------------------------------------------------------*/
2387 static void program_DQS_calibration(unsigned long *dimm_populated,
2388                                     unsigned char *iic0_dimm_addr,
2389                                     unsigned long num_dimm_banks)
2390 {
2391         unsigned long val;
2392
2393 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2394         mtsdram(SDRAM_RQDC, 0x80000037);
2395         mtsdram(SDRAM_RDCC, 0x40000000);
2396         mtsdram(SDRAM_RFDC, 0x000001DF);
2397
2398         test();
2399 #else
2400         /*------------------------------------------------------------------
2401          * Program RDCC register
2402          * Read sample cycle auto-update enable
2403          *-----------------------------------------------------------------*/
2404
2405         mfsdram(SDRAM_RDCC, val);
2406         mtsdram(SDRAM_RDCC,
2407                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2408                 | SDRAM_RDCC_RSAE_ENABLE);
2409
2410         /*------------------------------------------------------------------
2411          * Program RQDC register
2412          * Internal DQS delay mechanism enable
2413          *-----------------------------------------------------------------*/
2414         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2415
2416         /*------------------------------------------------------------------
2417          * Program RFDC register
2418          * Set Feedback Fractional Oversample
2419          * Auto-detect read sample cycle enable
2420          *-----------------------------------------------------------------*/
2421         mfsdram(SDRAM_RFDC, val);
2422         mtsdram(SDRAM_RFDC,
2423                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2424                          SDRAM_RFDC_RFFD_MASK))
2425                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2426                    SDRAM_RFDC_RFFD_ENCODE(0)));
2427
2428         DQS_calibration_process();
2429 #endif
2430 }
2431
2432 static int short_mem_test(void)
2433 {
2434         u32 *membase;
2435         u32 bxcr_num;
2436         u32 bxcf;
2437         int i;
2438         int j;
2439         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2440                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2441                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2442                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2443                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2444                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2445                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2446                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2447                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2448                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2449                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2450                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2451                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2452                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2453                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2454                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2455                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2456         int l;
2457
2458         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2459                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2460
2461                 /* Banks enabled */
2462                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2463                         /* Bank is enabled */
2464
2465                         /*------------------------------------------------------------------
2466                          * Run the short memory test.
2467                          *-----------------------------------------------------------------*/
2468                         membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2469
2470                         for (i = 0; i < NUMMEMTESTS; i++) {
2471                                 for (j = 0; j < NUMMEMWORDS; j++) {
2472                                         membase[j] = test[i][j];
2473                                         ppcDcbf((u32)&(membase[j]));
2474                                 }
2475                                 sync();
2476                                 for (l=0; l<NUMLOOPS; l++) {
2477                                         for (j = 0; j < NUMMEMWORDS; j++) {
2478                                                 if (membase[j] != test[i][j]) {
2479                                                         ppcDcbf((u32)&(membase[j]));
2480                                                         return 0;
2481                                                 }
2482                                                 ppcDcbf((u32)&(membase[j]));
2483                                         }
2484                                         sync();
2485                                 }
2486                         }
2487                 }       /* if bank enabled */
2488         }               /* for bxcf_num */
2489
2490         return 1;
2491 }
2492
2493 #ifndef HARD_CODED_DQS
2494 /*-----------------------------------------------------------------------------+
2495  * DQS_calibration_process.
2496  *-----------------------------------------------------------------------------*/
2497 static void DQS_calibration_process(void)
2498 {
2499         unsigned long rfdc_reg;
2500         unsigned long rffd;
2501         unsigned long val;
2502         long rffd_average;
2503         long max_start;
2504         long min_end;
2505         unsigned long begin_rqfd[MAXRANKS];
2506         unsigned long begin_rffd[MAXRANKS];
2507         unsigned long end_rqfd[MAXRANKS];
2508         unsigned long end_rffd[MAXRANKS];
2509         char window_found;
2510         unsigned long dlycal;
2511         unsigned long dly_val;
2512         unsigned long max_pass_length;
2513         unsigned long current_pass_length;
2514         unsigned long current_fail_length;
2515         unsigned long current_start;
2516         long max_end;
2517         unsigned char fail_found;
2518         unsigned char pass_found;
2519 #if !defined(CONFIG_DDR_RQDC_FIXED)
2520         u32 rqdc_reg;
2521         u32 rqfd;
2522         u32 rqfd_start;
2523         u32 rqfd_average;
2524         int loopi = 0;
2525         char str[] = "Auto calibration -";
2526         char slash[] = "\\|/-\\|/-";
2527
2528         /*------------------------------------------------------------------
2529          * Test to determine the best read clock delay tuning bits.
2530          *
2531          * Before the DDR controller can be used, the read clock delay needs to be
2532          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2533          * This value cannot be hardcoded into the program because it changes
2534          * depending on the board's setup and environment.
2535          * To do this, all delay values are tested to see if they
2536          * work or not.  By doing this, you get groups of fails with groups of
2537          * passing values.  The idea is to find the start and end of a passing
2538          * window and take the center of it to use as the read clock delay.
2539          *
2540          * A failure has to be seen first so that when we hit a pass, we know
2541          * that it is truely the start of the window.  If we get passing values
2542          * to start off with, we don't know if we are at the start of the window.
2543          *
2544          * The code assumes that a failure will always be found.
2545          * If a failure is not found, there is no easy way to get the middle
2546          * of the passing window.  I guess we can pretty much pick any value
2547          * but some values will be better than others.  Since the lowest speed
2548          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2549          * from experimentation it is safe to say you will always have a failure.
2550          *-----------------------------------------------------------------*/
2551
2552         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2553         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2554
2555         puts(str);
2556
2557 calibration_loop:
2558         mfsdram(SDRAM_RQDC, rqdc_reg);
2559         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2560                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2561 #else /* CONFIG_DDR_RQDC_FIXED */
2562         /*
2563          * On Katmai the complete auto-calibration somehow doesn't seem to
2564          * produce the best results, meaning optimal values for RQFD/RFFD.
2565          * This was discovered by GDA using a high bandwidth scope,
2566          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2567          * so now on Katmai "only" RFFD is auto-calibrated.
2568          */
2569         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2570 #endif /* CONFIG_DDR_RQDC_FIXED */
2571
2572         max_start = 0;
2573         min_end = 0;
2574         begin_rqfd[0] = 0;
2575         begin_rffd[0] = 0;
2576         begin_rqfd[1] = 0;
2577         begin_rffd[1] = 0;
2578         end_rqfd[0] = 0;
2579         end_rffd[0] = 0;
2580         end_rqfd[1] = 0;
2581         end_rffd[1] = 0;
2582         window_found = FALSE;
2583
2584         max_pass_length = 0;
2585         max_start = 0;
2586         max_end = 0;
2587         current_pass_length = 0;
2588         current_fail_length = 0;
2589         current_start = 0;
2590         window_found = FALSE;
2591         fail_found = FALSE;
2592         pass_found = FALSE;
2593
2594         /*
2595          * get the delay line calibration register value
2596          */
2597         mfsdram(SDRAM_DLCR, dlycal);
2598         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2599
2600         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2601                 mfsdram(SDRAM_RFDC, rfdc_reg);
2602                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2603
2604                 /*------------------------------------------------------------------
2605                  * Set the timing reg for the test.
2606                  *-----------------------------------------------------------------*/
2607                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2608
2609                 /*------------------------------------------------------------------
2610                  * See if the rffd value passed.
2611                  *-----------------------------------------------------------------*/
2612                 if (short_mem_test()) {
2613                         if (fail_found == TRUE) {
2614                                 pass_found = TRUE;
2615                                 if (current_pass_length == 0)
2616                                         current_start = rffd;
2617
2618                                 current_fail_length = 0;
2619                                 current_pass_length++;
2620
2621                                 if (current_pass_length > max_pass_length) {
2622                                         max_pass_length = current_pass_length;
2623                                         max_start = current_start;
2624                                         max_end = rffd;
2625                                 }
2626                         }
2627                 } else {
2628                         current_pass_length = 0;
2629                         current_fail_length++;
2630
2631                         if (current_fail_length >= (dly_val >> 2)) {
2632                                 if (fail_found == FALSE) {
2633                                         fail_found = TRUE;
2634                                 } else if (pass_found == TRUE) {
2635                                         window_found = TRUE;
2636                                         break;
2637                                 }
2638                         }
2639                 }
2640         }               /* for rffd */
2641
2642         /*------------------------------------------------------------------
2643          * Set the average RFFD value
2644          *-----------------------------------------------------------------*/
2645         rffd_average = ((max_start + max_end) >> 1);
2646
2647         if (rffd_average < 0)
2648                 rffd_average = 0;
2649
2650         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2651                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2652         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2653         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2654
2655 #if !defined(CONFIG_DDR_RQDC_FIXED)
2656         max_pass_length = 0;
2657         max_start = 0;
2658         max_end = 0;
2659         current_pass_length = 0;
2660         current_fail_length = 0;
2661         current_start = 0;
2662         window_found = FALSE;
2663         fail_found = FALSE;
2664         pass_found = FALSE;
2665
2666         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2667                 mfsdram(SDRAM_RQDC, rqdc_reg);
2668                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2669
2670                 /*------------------------------------------------------------------
2671                  * Set the timing reg for the test.
2672                  *-----------------------------------------------------------------*/
2673                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2674
2675                 /*------------------------------------------------------------------
2676                  * See if the rffd value passed.
2677                  *-----------------------------------------------------------------*/
2678                 if (short_mem_test()) {
2679                         if (fail_found == TRUE) {
2680                                 pass_found = TRUE;
2681                                 if (current_pass_length == 0)
2682                                         current_start = rqfd;
2683
2684                                 current_fail_length = 0;
2685                                 current_pass_length++;
2686
2687                                 if (current_pass_length > max_pass_length) {
2688                                         max_pass_length = current_pass_length;
2689                                         max_start = current_start;
2690                                         max_end = rqfd;
2691                                 }
2692                         }
2693                 } else {
2694                         current_pass_length = 0;
2695                         current_fail_length++;
2696
2697                         if (fail_found == FALSE) {
2698                                 fail_found = TRUE;
2699                         } else if (pass_found == TRUE) {
2700                                 window_found = TRUE;
2701                                 break;
2702                         }
2703                 }
2704         }
2705
2706         rqfd_average = ((max_start + max_end) >> 1);
2707
2708         /*------------------------------------------------------------------
2709          * Make sure we found the valid read passing window.  Halt if not
2710          *-----------------------------------------------------------------*/
2711         if (window_found == FALSE) {
2712                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2713                         putc('\b');
2714                         putc(slash[loopi++ % 8]);
2715
2716                         /* try again from with a different RQFD start value */
2717                         rqfd_start++;
2718                         goto calibration_loop;
2719                 }
2720
2721                 printf("\nERROR: Cannot determine a common read delay for the "
2722                        "DIMM(s) installed.\n");
2723                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2724                 ppc440sp_sdram_register_dump();
2725                 spd_ddr_init_hang ();
2726         }
2727
2728         if (rqfd_average < 0)
2729                 rqfd_average = 0;
2730
2731         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2732                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2733
2734         mtsdram(SDRAM_RQDC,
2735                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2736                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2737
2738         blank_string(strlen(str));
2739 #endif /* CONFIG_DDR_RQDC_FIXED */
2740
2741         /*
2742          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2743          * PowerPC440SP/SPe DDR2 application note:
2744          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2745          */
2746         mfsdram(SDRAM_RTSR, val);
2747         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2748                 mfsdram(SDRAM_RDCC, val);
2749                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2750                         val += 0x40000000;
2751                         mtsdram(SDRAM_RDCC, val);
2752                 }
2753         }
2754
2755         mfsdram(SDRAM_DLCR, val);
2756         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2757         mfsdram(SDRAM_RQDC, val);
2758         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2759         mfsdram(SDRAM_RFDC, val);
2760         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2761         mfsdram(SDRAM_RDCC, val);
2762         debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2763 }
2764 #else /* calibration test with hardvalues */
2765 /*-----------------------------------------------------------------------------+
2766  * DQS_calibration_process.
2767  *-----------------------------------------------------------------------------*/
2768 static void test(void)
2769 {
2770         unsigned long dimm_num;
2771         unsigned long ecc_temp;
2772         unsigned long i, j;
2773         unsigned long *membase;
2774         unsigned long bxcf[MAXRANKS];
2775         unsigned long val;
2776         char window_found;
2777         char begin_found[MAXDIMMS];
2778         char end_found[MAXDIMMS];
2779         char search_end[MAXDIMMS];
2780         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2781                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2782                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2783                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2784                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2785                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2786                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2787                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2788                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2789                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2790                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2791                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2792                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2793                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2794                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2795                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2796                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2797
2798         /*------------------------------------------------------------------
2799          * Test to determine the best read clock delay tuning bits.
2800          *
2801          * Before the DDR controller can be used, the read clock delay needs to be
2802          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2803          * This value cannot be hardcoded into the program because it changes
2804          * depending on the board's setup and environment.
2805          * To do this, all delay values are tested to see if they
2806          * work or not.  By doing this, you get groups of fails with groups of
2807          * passing values.  The idea is to find the start and end of a passing
2808          * window and take the center of it to use as the read clock delay.
2809          *
2810          * A failure has to be seen first so that when we hit a pass, we know
2811          * that it is truely the start of the window.  If we get passing values
2812          * to start off with, we don't know if we are at the start of the window.
2813          *
2814          * The code assumes that a failure will always be found.
2815          * If a failure is not found, there is no easy way to get the middle
2816          * of the passing window.  I guess we can pretty much pick any value
2817          * but some values will be better than others.  Since the lowest speed
2818          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2819          * from experimentation it is safe to say you will always have a failure.
2820          *-----------------------------------------------------------------*/
2821         mfsdram(SDRAM_MCOPT1, ecc_temp);
2822         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2823         mfsdram(SDRAM_MCOPT1, val);
2824         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2825                 SDRAM_MCOPT1_MCHK_NON);
2826
2827         window_found = FALSE;
2828         begin_found[0] = FALSE;
2829         end_found[0] = FALSE;
2830         search_end[0] = FALSE;
2831         begin_found[1] = FALSE;
2832         end_found[1] = FALSE;
2833         search_end[1] = FALSE;
2834
2835         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2836                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2837
2838                 /* Banks enabled */
2839                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2840
2841                         /* Bank is enabled */
2842                         membase =
2843                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2844
2845                         /*------------------------------------------------------------------
2846                          * Run the short memory test.
2847                          *-----------------------------------------------------------------*/
2848                         for (i = 0; i < NUMMEMTESTS; i++) {
2849                                 for (j = 0; j < NUMMEMWORDS; j++) {
2850                                         membase[j] = test[i][j];
2851                                         ppcDcbf((u32)&(membase[j]));
2852                                 }
2853                                 sync();
2854                                 for (j = 0; j < NUMMEMWORDS; j++) {
2855                                         if (membase[j] != test[i][j]) {
2856                                                 ppcDcbf((u32)&(membase[j]));
2857                                                 break;
2858                                         }
2859                                         ppcDcbf((u32)&(membase[j]));
2860                                 }
2861                                 sync();
2862                                 if (j < NUMMEMWORDS)
2863                                         break;
2864                         }
2865
2866                         /*------------------------------------------------------------------
2867                          * See if the rffd value passed.
2868                          *-----------------------------------------------------------------*/
2869                         if (i < NUMMEMTESTS) {
2870                                 if ((end_found[dimm_num] == FALSE) &&
2871                                     (search_end[dimm_num] == TRUE)) {
2872                                         end_found[dimm_num] = TRUE;
2873                                 }
2874                                 if ((end_found[0] == TRUE) &&
2875                                     (end_found[1] == TRUE))
2876                                         break;
2877                         } else {
2878                                 if (begin_found[dimm_num] == FALSE) {
2879                                         begin_found[dimm_num] = TRUE;
2880                                         search_end[dimm_num] = TRUE;
2881                                 }
2882                         }
2883                 } else {
2884                         begin_found[dimm_num] = TRUE;
2885                         end_found[dimm_num] = TRUE;
2886                 }
2887         }
2888
2889         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2890                 window_found = TRUE;
2891
2892         /*------------------------------------------------------------------
2893          * Make sure we found the valid read passing window.  Halt if not
2894          *-----------------------------------------------------------------*/
2895         if (window_found == FALSE) {
2896                 printf("ERROR: Cannot determine a common read delay for the "
2897                        "DIMM(s) installed.\n");
2898                 spd_ddr_init_hang ();
2899         }
2900
2901         /*------------------------------------------------------------------
2902          * Restore the ECC variable to what it originally was
2903          *-----------------------------------------------------------------*/
2904         mtsdram(SDRAM_MCOPT1,
2905                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2906                 | ecc_temp);
2907 }
2908 #endif
2909
2910 #if defined(DEBUG)
2911 static void ppc440sp_sdram_register_dump(void)
2912 {
2913         unsigned int sdram_reg;
2914         unsigned int sdram_data;
2915         unsigned int dcr_data;
2916
2917         printf("\n  Register Dump:\n");
2918         sdram_reg = SDRAM_MCSTAT;
2919         mfsdram(sdram_reg, sdram_data);
2920         printf("        SDRAM_MCSTAT    = 0x%08X", sdram_data);
2921         sdram_reg = SDRAM_MCOPT1;
2922         mfsdram(sdram_reg, sdram_data);
2923         printf("        SDRAM_MCOPT1    = 0x%08X\n", sdram_data);
2924         sdram_reg = SDRAM_MCOPT2;
2925         mfsdram(sdram_reg, sdram_data);
2926         printf("        SDRAM_MCOPT2    = 0x%08X", sdram_data);
2927         sdram_reg = SDRAM_MODT0;
2928         mfsdram(sdram_reg, sdram_data);
2929         printf("        SDRAM_MODT0     = 0x%08X\n", sdram_data);
2930         sdram_reg = SDRAM_MODT1;
2931         mfsdram(sdram_reg, sdram_data);
2932         printf("        SDRAM_MODT1     = 0x%08X", sdram_data);
2933         sdram_reg = SDRAM_MODT2;
2934         mfsdram(sdram_reg, sdram_data);
2935         printf("        SDRAM_MODT2     = 0x%08X\n", sdram_data);
2936         sdram_reg = SDRAM_MODT3;
2937         mfsdram(sdram_reg, sdram_data);
2938         printf("        SDRAM_MODT3     = 0x%08X", sdram_data);
2939         sdram_reg = SDRAM_CODT;
2940         mfsdram(sdram_reg, sdram_data);
2941         printf("        SDRAM_CODT      = 0x%08X\n", sdram_data);
2942         sdram_reg = SDRAM_VVPR;
2943         mfsdram(sdram_reg, sdram_data);
2944         printf("        SDRAM_VVPR      = 0x%08X", sdram_data);
2945         sdram_reg = SDRAM_OPARS;
2946         mfsdram(sdram_reg, sdram_data);
2947         printf("        SDRAM_OPARS     = 0x%08X\n", sdram_data);
2948         /*
2949          * OPAR2 is only used as a trigger register.
2950          * No data is contained in this register, and reading or writing
2951          * to is can cause bad things to happen (hangs).  Just skip it
2952          * and report NA
2953          * sdram_reg = SDRAM_OPAR2;
2954          * mfsdram(sdram_reg, sdram_data);
2955          * printf("        SDRAM_OPAR2     = 0x%08X\n", sdram_data);
2956          */
2957         printf("        SDRAM_OPART     = N/A       ");
2958         sdram_reg = SDRAM_RTR;
2959         mfsdram(sdram_reg, sdram_data);
2960         printf("        SDRAM_RTR       = 0x%08X\n", sdram_data);
2961         sdram_reg = SDRAM_MB0CF;
2962         mfsdram(sdram_reg, sdram_data);
2963         printf("        SDRAM_MB0CF     = 0x%08X", sdram_data);
2964         sdram_reg = SDRAM_MB1CF;
2965         mfsdram(sdram_reg, sdram_data);
2966         printf("        SDRAM_MB1CF     = 0x%08X\n", sdram_data);
2967         sdram_reg = SDRAM_MB2CF;
2968         mfsdram(sdram_reg, sdram_data);
2969         printf("        SDRAM_MB2CF     = 0x%08X", sdram_data);
2970         sdram_reg = SDRAM_MB3CF;
2971         mfsdram(sdram_reg, sdram_data);
2972         printf("        SDRAM_MB3CF     = 0x%08X\n", sdram_data);
2973         sdram_reg = SDRAM_INITPLR0;
2974         mfsdram(sdram_reg, sdram_data);
2975         printf("        SDRAM_INITPLR0  = 0x%08X", sdram_data);
2976         sdram_reg = SDRAM_INITPLR1;
2977         mfsdram(sdram_reg, sdram_data);
2978         printf("        SDRAM_INITPLR1  = 0x%08X\n", sdram_data);
2979         sdram_reg = SDRAM_INITPLR2;
2980         mfsdram(sdram_reg, sdram_data);
2981         printf("        SDRAM_INITPLR2  = 0x%08X", sdram_data);
2982         sdram_reg = SDRAM_INITPLR3;
2983         mfsdram(sdram_reg, sdram_data);
2984         printf("        SDRAM_INITPLR3  = 0x%08X\n", sdram_data);
2985         sdram_reg = SDRAM_INITPLR4;
2986         mfsdram(sdram_reg, sdram_data);
2987         printf("        SDRAM_INITPLR4  = 0x%08X", sdram_data);
2988         sdram_reg = SDRAM_INITPLR5;
2989         mfsdram(sdram_reg, sdram_data);
2990         printf("        SDRAM_INITPLR5  = 0x%08X\n", sdram_data);
2991         sdram_reg = SDRAM_INITPLR6;
2992         mfsdram(sdram_reg, sdram_data);
2993         printf("        SDRAM_INITPLR6  = 0x%08X", sdram_data);
2994         sdram_reg = SDRAM_INITPLR7;
2995         mfsdram(sdram_reg, sdram_data);
2996         printf("        SDRAM_INITPLR7  = 0x%08X\n", sdram_data);
2997         sdram_reg = SDRAM_INITPLR8;
2998         mfsdram(sdram_reg, sdram_data);
2999         printf("        SDRAM_INITPLR8  = 0x%08X", sdram_data);
3000         sdram_reg = SDRAM_INITPLR9;
3001         mfsdram(sdram_reg, sdram_data);
3002         printf("        SDRAM_INITPLR9  = 0x%08X\n", sdram_data);
3003         sdram_reg = SDRAM_INITPLR10;
3004         mfsdram(sdram_reg, sdram_data);
3005         printf("        SDRAM_INITPLR10 = 0x%08X", sdram_data);
3006         sdram_reg = SDRAM_INITPLR11;
3007         mfsdram(sdram_reg, sdram_data);
3008         printf("        SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
3009         sdram_reg = SDRAM_INITPLR12;
3010         mfsdram(sdram_reg, sdram_data);
3011         printf("        SDRAM_INITPLR12 = 0x%08X", sdram_data);
3012         sdram_reg = SDRAM_INITPLR13;
3013         mfsdram(sdram_reg, sdram_data);
3014         printf("        SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
3015         sdram_reg = SDRAM_INITPLR14;
3016         mfsdram(sdram_reg, sdram_data);
3017         printf("        SDRAM_INITPLR14 = 0x%08X", sdram_data);
3018         sdram_reg = SDRAM_INITPLR15;
3019         mfsdram(sdram_reg, sdram_data);
3020         printf("        SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
3021         sdram_reg = SDRAM_RQDC;
3022         mfsdram(sdram_reg, sdram_data);
3023         printf("        SDRAM_RQDC      = 0x%08X", sdram_data);
3024         sdram_reg = SDRAM_RFDC;
3025         mfsdram(sdram_reg, sdram_data);
3026         printf("        SDRAM_RFDC      = 0x%08X\n", sdram_data);
3027         sdram_reg = SDRAM_RDCC;
3028         mfsdram(sdram_reg, sdram_data);
3029         printf("        SDRAM_RDCC      = 0x%08X", sdram_data);
3030         sdram_reg = SDRAM_DLCR;
3031         mfsdram(sdram_reg, sdram_data);
3032         printf("        SDRAM_DLCR      = 0x%08X\n", sdram_data);
3033         sdram_reg = SDRAM_CLKTR;
3034         mfsdram(sdram_reg, sdram_data);
3035         printf("        SDRAM_CLKTR     = 0x%08X", sdram_data);
3036         sdram_reg = SDRAM_WRDTR;
3037         mfsdram(sdram_reg, sdram_data);
3038         printf("        SDRAM_WRDTR     = 0x%08X\n", sdram_data);
3039         sdram_reg = SDRAM_SDTR1;
3040         mfsdram(sdram_reg, sdram_data);
3041         printf("        SDRAM_SDTR1     = 0x%08X", sdram_data);
3042         sdram_reg = SDRAM_SDTR2;
3043         mfsdram(sdram_reg, sdram_data);
3044         printf("        SDRAM_SDTR2     = 0x%08X\n", sdram_data);
3045         sdram_reg = SDRAM_SDTR3;
3046         mfsdram(sdram_reg, sdram_data);
3047         printf("        SDRAM_SDTR3     = 0x%08X", sdram_data);
3048         sdram_reg = SDRAM_MMODE;
3049         mfsdram(sdram_reg, sdram_data);
3050         printf("        SDRAM_MMODE     = 0x%08X\n", sdram_data);
3051         sdram_reg = SDRAM_MEMODE;
3052         mfsdram(sdram_reg, sdram_data);
3053         printf("        SDRAM_MEMODE    = 0x%08X", sdram_data);
3054         sdram_reg = SDRAM_ECCCR;
3055         mfsdram(sdram_reg, sdram_data);
3056         printf("        SDRAM_ECCCR     = 0x%08X\n\n", sdram_data);
3057
3058         dcr_data = mfdcr(SDRAM_R0BAS);
3059         printf("        MQ0_B0BAS       = 0x%08X", dcr_data);
3060         dcr_data = mfdcr(SDRAM_R1BAS);
3061         printf("        MQ1_B0BAS       = 0x%08X\n", dcr_data);
3062         dcr_data = mfdcr(SDRAM_R2BAS);
3063         printf("        MQ2_B0BAS       = 0x%08X", dcr_data);
3064         dcr_data = mfdcr(SDRAM_R3BAS);
3065         printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
3066 }
3067 #else
3068 static void ppc440sp_sdram_register_dump(void)
3069 {
3070 }
3071 #endif
3072 #endif /* CONFIG_SPD_EEPROM */