drivers/ddr/altera/sdram_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright Altera Corporation (C) 2014-2015
   4  */
   5 #include <common.h>
   6 #include <errno.h>
   7 #include <div64.h>
   8 #include <watchdog.h>
   9 #include <asm/arch/fpga_manager.h>
  10 #include <asm/arch/sdram.h>
  11 #include <asm/arch/system_manager.h>
  12 #include <asm/io.h>
  13
  14 struct sdram_prot_rule {
  15         u32     sdram_start;    /* SDRAM start address */
  16         u32     sdram_end;      /* SDRAM end address */
  17         u32     rule;           /* SDRAM protection rule number: 0-19 */
  18         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  19
  20         u32     security;
  21         u32     portmask;
  22         u32     result;
  23         u32     lo_prot_id;
  24         u32     hi_prot_id;
  25 };
  26
  27 static struct socfpga_system_manager *sysmgr_regs =
  28         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  29 static struct socfpga_sdr_ctrl *sdr_ctrl =
  30         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  31
  32 /**
  33  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  34  * @cfg:        SDRAM controller configuration data
  35  *
  36  * SDRAM Failure happens when accessing non-existent memory. Artificially
  37  * increase the number of rows so that the memory controller thinks it has
  38  * 4GB of RAM. This function returns such amount of rows.
  39  */
  40 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
  41 {
  42         /* Define constant for 4G memory - used for SDRAM errata workaround */
  43 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
  44         const unsigned long long memsize = MEMSIZE_4G;
  45         const unsigned int cs =
  46                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  47                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  48         const unsigned int rows =
  49                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  50                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  51         const unsigned int banks =
  52                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
  53                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
  54         const unsigned int cols =
  55                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
  56                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
  57         const unsigned int width = 8;
  58
  59         unsigned long long newrows;
  60         int bits, inewrowslog2;
  61
  62         debug("workaround rows - memsize %lld\n", memsize);
  63         debug("workaround rows - cs        %d\n", cs);
  64         debug("workaround rows - width     %d\n", width);
  65         debug("workaround rows - rows      %d\n", rows);
  66         debug("workaround rows - banks     %d\n", banks);
  67         debug("workaround rows - cols      %d\n", cols);
  68
  69         newrows = lldiv(memsize, cs * (width / 8));
  70         debug("rows workaround - term1 %lld\n", newrows);
  71
  72         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  73         debug("rows workaround - term2 %lld\n", newrows);
  74
  75         /*
  76          * Compute the hamming weight - same as number of bits set.
  77          * Need to see if result is ordinal power of 2 before
  78          * attempting log2 of result.
  79          */
  80         bits = generic_hweight32(newrows);
  81
  82         debug("rows workaround - bits %d\n", bits);
  83
  84         if (bits != 1) {
  85                 printf("SDRAM workaround failed, bits set %d\n", bits);
  86                 return rows;
  87         }
  88
  89         if (newrows > UINT_MAX) {
  90                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
  91                 return rows;
  92         }
  93
  94         inewrowslog2 = __ilog2(newrows);
  95
  96         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
  97
  98         if (inewrowslog2 == -1) {
  99                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 100                 return rows;
 101         }
 102
 103         return inewrowslog2;
 104 }
 105
 106 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 107 static void sdram_set_rule(struct sdram_prot_rule *prule)
 108 {
 109         u32 lo_addr_bits;
 110         u32 hi_addr_bits;
 111         int ruleno = prule->rule;
 112
 113         /* Select the rule */
 114         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 115
 116         /* Obtain the address bits */
 117         lo_addr_bits = prule->sdram_start >> 20ULL;
 118         hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
 119
 120         debug("sdram set rule start %x, %d\n", lo_addr_bits,
 121               prule->sdram_start);
 122         debug("sdram set rule end   %x, %d\n", hi_addr_bits,
 123               prule->sdram_end);
 124
 125         /* Set rule addresses */
 126         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 127
 128         /* Set rule protection ids */
 129         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 130                &sdr_ctrl->prot_rule_id);
 131
 132         /* Set the rule data */
 133         writel(prule->security | (prule->valid << 2) |
 134                (prule->portmask << 3) | (prule->result << 13),
 135                &sdr_ctrl->prot_rule_data);
 136
 137         /* write the rule */
 138         writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
 139
 140         /* Set rule number to 0 by default */
 141         writel(0, &sdr_ctrl->prot_rule_rdwr);
 142 }
 143
 144 static void sdram_get_rule(struct sdram_prot_rule *prule)
 145 {
 146         u32 addr;
 147         u32 id;
 148         u32 data;
 149         int ruleno = prule->rule;
 150
 151         /* Read the rule */
 152         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 153         writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
 154
 155         /* Get the addresses */
 156         addr = readl(&sdr_ctrl->prot_rule_addr);
 157         prule->sdram_start = (addr & 0xFFF) << 20;
 158         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 159
 160         /* Get the configured protection IDs */
 161         id = readl(&sdr_ctrl->prot_rule_id);
 162         prule->lo_prot_id = id & 0xFFF;
 163         prule->hi_prot_id = (id >> 12) & 0xFFF;
 164
 165         /* Get protection data */
 166         data = readl(&sdr_ctrl->prot_rule_data);
 167
 168         prule->security = data & 0x3;
 169         prule->valid = (data >> 2) & 0x1;
 170         prule->portmask = (data >> 3) & 0x3FF;
 171         prule->result = (data >> 13) & 0x1;
 172 }
 173
 174 static void
 175 sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
 176 {
 177         struct sdram_prot_rule rule;
 178         int rules;
 179
 180         /* Start with accepting all SDRAM transaction */
 181         writel(0x0, &sdr_ctrl->protport_default);
 182
 183         /* Clear all protection rules for warm boot case */
 184         memset(&rule, 0, sizeof(rule));
 185
 186         for (rules = 0; rules < 20; rules++) {
 187                 rule.rule = rules;
 188                 sdram_set_rule(&rule);
 189         }
 190
 191         /* new rule: accept SDRAM */
 192         rule.sdram_start = sdram_start;
 193         rule.sdram_end = sdram_end;
 194         rule.lo_prot_id = 0x0;
 195         rule.hi_prot_id = 0xFFF;
 196         rule.portmask = 0x3FF;
 197         rule.security = 0x3;
 198         rule.result = 0;
 199         rule.valid = 1;
 200         rule.rule = 0;
 201
 202         /* set new rule */
 203         sdram_set_rule(&rule);
 204
 205         /* default rule: reject everything */
 206         writel(0x3ff, &sdr_ctrl->protport_default);
 207 }
 208
 209 static void sdram_dump_protection_config(void)
 210 {
 211         struct sdram_prot_rule rule;
 212         int rules;
 213
 214         debug("SDRAM Prot rule, default %x\n",
 215               readl(&sdr_ctrl->protport_default));
 216
 217         for (rules = 0; rules < 20; rules++) {
 218                 rule.rule = rules;
 219                 sdram_get_rule(&rule);
 220                 debug("Rule %d, rules ...\n", rules);
 221                 debug("    sdram start %x\n", rule.sdram_start);
 222                 debug("    sdram end   %x\n", rule.sdram_end);
 223                 debug("    low prot id %d, hi prot id %d\n",
 224                       rule.lo_prot_id,
 225                       rule.hi_prot_id);
 226                 debug("    portmask %x\n", rule.portmask);
 227                 debug("    security %d\n", rule.security);
 228                 debug("    result %d\n", rule.result);
 229                 debug("    valid %d\n", rule.valid);
 230         }
 231 }
 232
 233 /**
 234  * sdram_write_verify() - write to register and verify the write.
 235  * @addr:       Register address
 236  * @val:        Value to be written and verified
 237  *
 238  * This function writes to a register, reads back the value and compares
 239  * the result with the written value to check if the data match.
 240  */
 241 static unsigned sdram_write_verify(const u32 *addr, const u32 val)
 242 {
 243         u32 rval;
 244
 245         debug("   Write - Address 0x%p Data 0x%08x\n", addr, val);
 246         writel(val, addr);
 247
 248         debug("   Read and verify...");
 249         rval = readl(addr);
 250         if (rval != val) {
 251                 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
 252                       addr, val, rval);
 253                 return -EINVAL;
 254         }
 255
 256         debug("correct!\n");
 257         return 0;
 258 }
 259
 260 /**
 261  * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
 262  * @cfg:        SDRAM controller configuration data
 263  *
 264  * Return the value of DRAM CTRLCFG register.
 265  */
 266 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
 267 {
 268         const u32 csbits =
 269                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 270                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 271         u32 addrorder =
 272                 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
 273                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 274
 275         u32 ctrl_cfg = cfg->ctrl_cfg;
 276
 277         /*
 278          * SDRAM Failure When Accessing Non-Existent Memory
 279          * Set the addrorder field of the SDRAM control register
 280          * based on the CSBITs setting.
 281          */
 282         if (csbits == 1) {
 283                 if (addrorder != 0)
 284                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 285                 addrorder = 0;
 286         } else if (csbits == 2) {
 287                 if (addrorder != 2)
 288                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 289                 addrorder = 2;
 290         }
 291
 292         ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
 293         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 294
 295         return ctrl_cfg;
 296 }
 297
 298 /**
 299  * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
 300  * @cfg:        SDRAM controller configuration data
 301  *
 302  * Return the value of DRAM ADDRW register.
 303  */
 304 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
 305 {
 306         /*
 307          * SDRAM Failure When Accessing Non-Existent Memory
 308          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 309          * log2(number of chip select bits). Since there's only
 310          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 311          * which is the same as "chip selects" - 1.
 312          */
 313         const int rows = get_errata_rows(cfg);
 314         u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
 315
 316         return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 317 }
 318
 319 /**
 320  * sdr_load_regs() - Load SDRAM controller registers
 321  * @cfg:        SDRAM controller configuration data
 322  *
 323  * This function loads the register values into the SDRAM controller block.
 324  */
 325 static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
 326 {
 327         const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
 328         const u32 dram_addrw = sdr_get_addr_rw(cfg);
 329
 330         debug("\nConfiguring CTRLCFG\n");
 331         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 332
 333         debug("Configuring DRAMTIMING1\n");
 334         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 335
 336         debug("Configuring DRAMTIMING2\n");
 337         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 338
 339         debug("Configuring DRAMTIMING3\n");
 340         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 341
 342         debug("Configuring DRAMTIMING4\n");
 343         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 344
 345         debug("Configuring LOWPWRTIMING\n");
 346         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 347
 348         debug("Configuring DRAMADDRW\n");
 349         writel(dram_addrw, &sdr_ctrl->dram_addrw);
 350
 351         debug("Configuring DRAMIFWIDTH\n");
 352         writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
 353
 354         debug("Configuring DRAMDEVWIDTH\n");
 355         writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
 356
 357         debug("Configuring LOWPWREQ\n");
 358         writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
 359
 360         debug("Configuring DRAMINTR\n");
 361         writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
 362
 363         debug("Configuring STATICCFG\n");
 364         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 365
 366         debug("Configuring CTRLWIDTH\n");
 367         writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
 368
 369         debug("Configuring PORTCFG\n");
 370         writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
 371
 372         debug("Configuring FIFOCFG\n");
 373         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 374
 375         debug("Configuring MPPRIORITY\n");
 376         writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
 377
 378         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 379         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 380         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 381         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 382         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 383
 384         debug("Configuring MPPACING_MPPACING_0\n");
 385         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 386         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 387         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 388         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 389
 390         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 391         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 392         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 393         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 394
 395         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 396         writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
 397
 398         debug("Configuring CPORTWIDTH\n");
 399         writel(cfg->cport_width, &sdr_ctrl->cport_width);
 400
 401         debug("Configuring CPORTWMAP\n");
 402         writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
 403
 404         debug("Configuring CPORTRMAP\n");
 405         writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
 406
 407         debug("Configuring RFIFOCMAP\n");
 408         writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
 409
 410         debug("Configuring WFIFOCMAP\n");
 411         writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
 412
 413         debug("Configuring CPORTRDWR\n");
 414         writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
 415
 416         debug("Configuring DRAMODT\n");
 417         writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
 418
 419         debug("Configuring EXTRATIME1\n");
 420         writel(cfg->extratime1, &sdr_ctrl->extratime1);
 421 }
 422
 423 /**
 424  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 425  * @sdr_phy_reg:        Value of the PHY control register 0
 426  *
 427  * Initialize the SDRAM MMR.
 428  */
 429 int sdram_mmr_init_full(unsigned int sdr_phy_reg)
 430 {
 431         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 432         const unsigned int rows =
 433                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 434                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 435         int ret;
 436
 437         writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
 438
 439         sdr_load_regs(cfg);
 440
 441         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 442         writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
 443
 444         /* only enable if the FPGA is programmed */
 445         if (fpgamgr_test_fpga_ready()) {
 446                 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 447                                          cfg->fpgaport_rst);
 448                 if (ret)
 449                         return ret;
 450         }
 451
 452         /* Restore the SDR PHY Register if valid */
 453         if (sdr_phy_reg != 0xffffffff)
 454                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 455
 456         /* Final step - apply configuration changes */
 457         debug("Configuring STATICCFG\n");
 458         clrsetbits_le32(&sdr_ctrl->static_cfg,
 459                         SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 460                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 461
 462         sdram_set_protection_config(0, sdram_calculate_size() - 1);
 463
 464         sdram_dump_protection_config();
 465
 466         return 0;
 467 }
 468
 469 /**
 470  * sdram_calculate_size() - Calculate SDRAM size
 471  *
 472  * Calculate SDRAM device size based on SDRAM controller parameters.
 473  * Size is specified in bytes.
 474  */
 475 unsigned long sdram_calculate_size(void)
 476 {
 477         unsigned long temp;
 478         unsigned long row, bank, col, cs, width;
 479         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 480         const unsigned int csbits =
 481                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 482                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 483         const unsigned int rowbits =
 484                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 485                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 486
 487         temp = readl(&sdr_ctrl->dram_addrw);
 488         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 489                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 490
 491         /*
 492          * SDRAM Failure When Accessing Non-Existent Memory
 493          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 494          * since the FB specifies we modify ROWBITs to work around SDRAM
 495          * controller issue.
 496          */
 497         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 498         if (row == 0)
 499                 row = rowbits;
 500         /*
 501          * If the stored handoff value for rows is greater than
 502          * the field width in the sdr.dramaddrw register then
 503          * something is very wrong. Revert to using the the #define
 504          * value handed off by the SOCEDS tool chain instead of
 505          * using a broken value.
 506          */
 507         if (row > 31)
 508                 row = rowbits;
 509
 510         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 511                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 512
 513         /*
 514          * SDRAM Failure When Accessing Non-Existent Memory
 515          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 516          * since the FB specifies we modify CSBITs to work around SDRAM
 517          * controller issue.
 518          */
 519         cs = csbits;
 520
 521         width = readl(&sdr_ctrl->dram_if_width);
 522
 523         /* ECC would not be calculated as its not addressible */
 524         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 525                 width = 32;
 526         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 527                 width = 16;
 528
 529         /* calculate the SDRAM size base on this info */
 530         temp = 1 << (row + bank + col);
 531         temp = temp * cs * (width  / 8);
 532
 533         debug("%s returns %ld\n", __func__, temp);
 534
 535         return temp;
 536 }