board/atmel/sama5d3_xplained/sama5d3_xplained.c

   1 /*
   2  * Copyright (C) 2014 Atmel Corporation
   3  *                    Bo Shen <[email protected]>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mmc.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/sama5d3_smc.h>
  12 #include <asm/arch/at91_common.h>
  13 #include <asm/arch/at91_pmc.h>
  14 #include <asm/arch/at91_rstc.h>
  15 #include <asm/arch/gpio.h>
  16 #include <asm/arch/clk.h>
  17 #include <atmel_mci.h>
  18 #include <net.h>
  19 #include <netdev.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #ifdef CONFIG_NAND_ATMEL
  24 void sama5d3_xplained_nand_hw_init(void)
  25 {
  26         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  27
  28         at91_periph_clk_enable(ATMEL_ID_SMC);
  29
  30         /* Configure SMC CS3 for NAND/SmartMedia */
  31         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  32                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  33                &smc->cs[3].setup);
  34         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  35                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  36                &smc->cs[3].pulse);
  37         writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  38                &smc->cs[3].cycle);
  39         writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  40                AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
  41                AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  42                AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  43         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  44                AT91_SMC_MODE_EXNW_DISABLE |
  45 #ifdef CONFIG_SYS_NAND_DBW_16
  46                AT91_SMC_MODE_DBW_16 |
  47 #else /* CONFIG_SYS_NAND_DBW_8 */
  48                AT91_SMC_MODE_DBW_8 |
  49 #endif
  50                AT91_SMC_MODE_TDF_CYCLE(3),
  51                &smc->cs[3].mode);
  52 }
  53 #endif
  54
  55 #ifdef CONFIG_CMD_USB
  56 static void sama5d3_xplained_usb_hw_init(void)
  57 {
  58         at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
  59         at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
  60 }
  61 #endif
  62
  63 #ifdef CONFIG_GENERIC_ATMEL_MCI
  64 static void sama5d3_xplained_mci0_hw_init(void)
  65 {
  66         at91_mci_hw_init();
  67
  68         at91_set_pio_output(AT91_PIO_PORTE, 2, 0);      /* MCI0 Power */
  69 }
  70 #endif
  71
  72 int board_early_init_f(void)
  73 {
  74         at91_periph_clk_enable(ATMEL_ID_PIOA);
  75         at91_periph_clk_enable(ATMEL_ID_PIOB);
  76         at91_periph_clk_enable(ATMEL_ID_PIOC);
  77         at91_periph_clk_enable(ATMEL_ID_PIOD);
  78         at91_periph_clk_enable(ATMEL_ID_PIOE);
  79
  80         at91_seriald_hw_init();
  81
  82         return 0;
  83 }
  84
  85 int board_init(void)
  86 {
  87         /* adress of boot parameters */
  88         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  89
  90 #ifdef CONFIG_NAND_ATMEL
  91         sama5d3_xplained_nand_hw_init();
  92 #endif
  93 #ifdef CONFIG_CMD_USB
  94         sama5d3_xplained_usb_hw_init();
  95 #endif
  96 #ifdef CONFIG_GENERIC_ATMEL_MCI
  97         sama5d3_xplained_mci0_hw_init();
  98 #endif
  99 #ifdef CONFIG_MACB
 100         at91_gmac_hw_init();
 101         at91_macb_hw_init();
 102 #endif
 103         return 0;
 104 }
 105
 106 int dram_init(void)
 107 {
 108         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 109                                     CONFIG_SYS_SDRAM_SIZE);
 110
 111         return 0;
 112 }
 113
 114 int board_eth_init(bd_t *bis)
 115 {
 116 #ifdef CONFIG_MACB
 117         macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
 118         macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 119 #endif
 120         return 0;
 121 }
 122
 123 #ifdef CONFIG_GENERIC_ATMEL_MCI
 124 int board_mmc_init(bd_t *bis)
 125 {
 126         atmel_mci_init((void *)ATMEL_BASE_MCI0);
 127
 128         return 0;
 129 }
 130 #endif