1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
9 #include <linux/types.h>
14 * Structure for the cache controller
17 phys_addr_t base; /* Base physical address of cache device. */
22 * get_info() - Get basic cache info
24 * @dev: Device to check (UCLASS_CACHE)
25 * @info: Place to put info
26 * @return 0 if OK, -ve on error
28 int (*get_info)(struct udevice *dev, struct cache_info *info);
31 * enable() - Enable cache
33 * @dev: Device to check (UCLASS_CACHE)
34 * @return 0 if OK, -ve on error
36 int (*enable)(struct udevice *dev);
39 * disable() - Flush and disable cache
41 * @dev: Device to check (UCLASS_CACHE)
42 * @return 0 if OK, -ve on error
44 int (*disable)(struct udevice *dev);
47 #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
50 * cache_get_info() - Get information about a cache controller
52 * @dev: Device to check (UCLASS_CACHE)
53 * @info: Returns cache info
54 * Return: 0 if OK, -ve on error
56 int cache_get_info(struct udevice *dev, struct cache_info *info);
59 * cache_enable() - Enable cache
61 * @dev: Device to check (UCLASS_CACHE)
62 * Return: 0 if OK, -ve on error
64 int cache_enable(struct udevice *dev);
67 * cache_disable() - Flush and disable cache
69 * @dev: Device to check (UCLASS_CACHE)
70 * Return: 0 if OK, -ve on error
72 int cache_disable(struct udevice *dev);