]> Git Repo - J-u-boot.git/blob - configs/chromebook_bob_defconfig
rockchip: rk3288-firefly: Change to use FIT
[J-u-boot.git] / configs / chromebook_bob_defconfig
1 CONFIG_ARM=y
2 CONFIG_SKIP_LOWLEVEL_INIT=y
3 CONFIG_SPL_SYS_DCACHE_OFF=y
4 CONFIG_COUNTER_FREQUENCY=24000000
5 CONFIG_ARCH_ROCKCHIP=y
6 CONFIG_TEXT_BASE=0x00200000
7 CONFIG_SPL_GPIO=y
8 CONFIG_NR_DRAM_BANKS=1
9 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
10 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
11 CONFIG_SF_DEFAULT_SPEED=20000000
12 CONFIG_ENV_OFFSET=0x3F8000
13 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-bob"
14 CONFIG_DM_RESET=y
15 CONFIG_ROCKCHIP_RK3399=y
16 CONFIG_ROCKCHIP_BOOT_MODE_REG=0
17 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
18 # CONFIG_SPL_MMC is not set
19 CONFIG_SPL_STACK=0xff8effff
20 CONFIG_SPL_TEXT_BASE=0xff8c2000
21 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
22 CONFIG_SPL_BSS_START_ADDR=0xff8e0000
23 CONFIG_SPL_BSS_MAX_SIZE=0x10000
24 CONFIG_SPL_STACK_R=y
25 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
26 CONFIG_SYS_LOAD_ADDR=0x800800
27 CONFIG_SF_DEFAULT_BUS=1
28 CONFIG_DEBUG_UART_BASE=0xff1a0000
29 CONFIG_DEBUG_UART_CLOCK=24000000
30 CONFIG_SPL_SPI_FLASH_SUPPORT=y
31 CONFIG_SPL_SPI=y
32 CONFIG_DEBUG_UART=y
33 # CONFIG_SPL_FIT_SIGNATURE is not set
34 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
35 # CONFIG_DISPLAY_CPUINFO is not set
36 CONFIG_DISPLAY_BOARDINFO_LATE=y
37 CONFIG_BOARD_EARLY_INIT_R=y
38 CONFIG_BLOBLIST=y
39 CONFIG_BLOBLIST_ADDR=0x100000
40 CONFIG_BLOBLIST_SIZE=0x1000
41 CONFIG_SPL_MAX_SIZE=0x1e000
42 CONFIG_SPL_PAD_TO=0x7f8000
43 CONFIG_HANDOFF=y
44 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
45 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
46 CONFIG_SPL_SPI_LOAD=y
47 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
48 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
49 CONFIG_CMD_BOOTZ=y
50 CONFIG_CMD_GPIO=y
51 CONFIG_CMD_GPT=y
52 CONFIG_CMD_I2C=y
53 CONFIG_CMD_MMC=y
54 CONFIG_CMD_SF_TEST=y
55 CONFIG_CMD_SPI=y
56 CONFIG_CMD_USB=y
57 # CONFIG_CMD_SETEXPR is not set
58 CONFIG_CMD_TIME=y
59 CONFIG_CMD_PMIC=y
60 CONFIG_CMD_REGULATOR=y
61 CONFIG_CMD_LOG=y
62 CONFIG_SPL_OF_CONTROL=y
63 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
64 CONFIG_ENV_IS_IN_MMC=y
65 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
66 CONFIG_ROCKCHIP_GPIO=y
67 CONFIG_I2C_CROS_EC_TUNNEL=y
68 CONFIG_SYS_I2C_ROCKCHIP=y
69 CONFIG_I2C_MUX=y
70 CONFIG_CROS_EC_KEYB=y
71 CONFIG_ROCKCHIP_IODOMAIN=y
72 CONFIG_CROS_EC=y
73 CONFIG_CROS_EC_SPI=y
74 CONFIG_PWRSEQ=y
75 CONFIG_MMC_PWRSEQ=y
76 CONFIG_MMC_DW=y
77 CONFIG_MMC_DW_ROCKCHIP=y
78 CONFIG_MMC_SDHCI=y
79 CONFIG_MMC_SDHCI_ROCKCHIP=y
80 CONFIG_SPI_FLASH_GIGADEVICE=y
81 CONFIG_SPI_FLASH_WINBOND=y
82 CONFIG_ETH_DESIGNWARE=y
83 CONFIG_GMAC_ROCKCHIP=y
84 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
85 CONFIG_PHY_ROCKCHIP_TYPEC=y
86 CONFIG_PMIC_RK8XX=y
87 CONFIG_REGULATOR_PWM=y
88 CONFIG_DM_REGULATOR_GPIO=y
89 CONFIG_REGULATOR_RK8XX=y
90 CONFIG_PWM_CROS_EC=y
91 CONFIG_PWM_ROCKCHIP=y
92 CONFIG_DEBUG_UART_SHIFT=2
93 CONFIG_SYS_NS16550_MEM32=y
94 CONFIG_ROCKCHIP_SPI=y
95 CONFIG_SYSRESET=y
96 CONFIG_USB=y
97 CONFIG_USB_XHCI_HCD=y
98 CONFIG_USB_EHCI_HCD=y
99 CONFIG_USB_EHCI_GENERIC=y
100 CONFIG_USB_OHCI_HCD=y
101 CONFIG_USB_OHCI_GENERIC=y
102 CONFIG_USB_DWC3=y
103 CONFIG_USB_DWC3_GENERIC=y
104 CONFIG_USB_KEYBOARD=y
105 CONFIG_USB_HOST_ETHER=y
106 CONFIG_USB_ETHER_ASIX=y
107 CONFIG_USB_ETHER_ASIX88179=y
108 CONFIG_USB_ETHER_MCS7830=y
109 CONFIG_USB_ETHER_RTL8152=y
110 CONFIG_USB_ETHER_SMSC95XX=y
111 CONFIG_VIDEO=y
112 CONFIG_DISPLAY=y
113 CONFIG_VIDEO_ROCKCHIP=y
114 CONFIG_VIDEO_ROCKCHIP_MAX_XRES=1280
115 CONFIG_VIDEO_ROCKCHIP_MAX_YRES=800
116 CONFIG_DISPLAY_ROCKCHIP_EDP=y
117 CONFIG_CMD_DHRYSTONE=y
118 CONFIG_ERRNO_STR=y
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