arch/arm/mach-socfpga/wrap_sdram_config.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Marek Vasut <[email protected]>
   4  */
   5
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <asm/arch/sdram.h>
   9
  10 /* Board-specific header. */
  11 #include <qts/sdram_config.h>
  12
  13 static const struct socfpga_sdram_config sdram_config = {
  14         .ctrl_cfg =
  15                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
  16                         SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)                |
  17                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
  18                         SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)                  |
  19                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
  20                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)              |
  21                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
  22                         SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)                  |
  23                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
  24                         SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)              |
  25                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
  26                         SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)              |
  27                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
  28                         SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)            |
  29                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
  30                         SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)               |
  31                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
  32                         SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
  33         .dram_timing1 =
  34                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
  35                         SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)               |
  36                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
  37                         SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)                |
  38                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
  39                         SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)                |
  40                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
  41                         SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)               |
  42                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
  43                         SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)               |
  44                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
  45                         SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
  46         .dram_timing2 =
  47                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
  48                         SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)              |
  49                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
  50                         SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)               |
  51                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
  52                         SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)                |
  53                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
  54                         SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)                |
  55                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
  56                         SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
  57         .dram_timing3 =
  58                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
  59                         SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)               |
  60                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
  61                         SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)               |
  62                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
  63                         SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)                |
  64                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
  65                         SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)               |
  66                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
  67                         SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
  68         .dram_timing4 =
  69                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
  70                         SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)       |
  71                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
  72                         SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
  73         .lowpwr_timing =
  74                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
  75                         SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)      |
  76                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
  77                         SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
  78         .dram_odt =
  79                 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
  80                         SDR_CTRLGRP_DRAMODT_READ_LSB)                   |
  81                 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
  82                         SDR_CTRLGRP_DRAMODT_WRITE_LSB),
  83 #if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)       /* DDR3 */
  84         .extratime1 =
  85                 (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
  86                                 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)            |
  87                 (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
  88                                 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)         |
  89                 (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
  90                                 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
  91 #endif
  92         .dram_addrw =
  93                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
  94                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)              |
  95                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
  96                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)              |
  97                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
  98                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)             |
  99                 ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
 100                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
 101         .dram_if_width =
 102                 (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
 103                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
 104         .dram_dev_width =
 105                 (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
 106                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
 107         .dram_intr =
 108                 (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
 109                         SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
 110         .lowpwr_eq =
 111                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
 112                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
 113         .static_cfg =
 114                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
 115                         SDR_CTRLGRP_STATICCFG_MEMBL_LSB)                |
 116                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
 117                         SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
 118         .ctrl_width =
 119                 (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
 120                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
 121         .cport_width =
 122                 (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
 123                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
 124         .cport_wmap =
 125                 (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
 126                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
 127         .cport_rmap =
 128                 (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
 129                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
 130         .rfifo_cmap =
 131                 (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
 132                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
 133         .wfifo_cmap =
 134                 (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
 135                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
 136         .cport_rdwr =
 137                 (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
 138                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
 139         .port_cfg =
 140                 (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
 141                         SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
 142         .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
 143         .fifo_cfg =
 144                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
 145                         SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)               |
 146                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
 147                         SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
 148         .mp_priority =
 149                 (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
 150                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
 151         .mp_weight0 =
 152                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
 153                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
 154         .mp_weight1 =
 155                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
 156                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
 157                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
 158                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
 159         .mp_weight2 =
 160                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
 161                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
 162         .mp_weight3 =
 163                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
 164                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
 165         .mp_pacing0 =
 166                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
 167                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
 168         .mp_pacing1 =
 169                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
 170                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
 171                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
 172                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
 173         .mp_pacing2 =
 174                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
 175                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
 176         .mp_pacing3 =
 177                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
 178                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
 179         .mp_threshold0 =
 180                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
 181                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
 182         .mp_threshold1 =
 183                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
 184                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
 185         .mp_threshold2 =
 186                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
 187                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
 188         .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
 189 };
 190
 191 static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
 192         .activate_0_and_1               = RW_MGR_ACTIVATE_0_AND_1,
 193         .activate_0_and_1_wait1         = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
 194         .activate_0_and_1_wait2         = RW_MGR_ACTIVATE_0_AND_1_WAIT2,
 195         .clear_dqs_enable               = RW_MGR_CLEAR_DQS_ENABLE,
 196         .guaranteed_read                = RW_MGR_GUARANTEED_READ,
 197         .guaranteed_read_cont           = RW_MGR_GUARANTEED_READ_CONT,
 198         .guaranteed_write               = RW_MGR_GUARANTEED_WRITE,
 199         .guaranteed_write_wait0         = RW_MGR_GUARANTEED_WRITE_WAIT0,
 200         .guaranteed_write_wait1         = RW_MGR_GUARANTEED_WRITE_WAIT1,
 201         .guaranteed_write_wait2         = RW_MGR_GUARANTEED_WRITE_WAIT2,
 202         .guaranteed_write_wait3         = RW_MGR_GUARANTEED_WRITE_WAIT3,
 203         .idle_loop1                     = RW_MGR_IDLE_LOOP1,
 204         .idle_loop2                     = RW_MGR_IDLE_LOOP2,
 205 #if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1)       /* DDR2 */
 206         .emr                            = RW_MGR_EMR,
 207         .emr2                           = RW_MGR_EMR2,
 208         .emr3                           = RW_MGR_EMR3,
 209         .init_reset_0_cke_0             = RW_MGR_INIT_CKE_0,
 210         .nop                            = RW_MGR_NOP,
 211         .refresh                        = RW_MGR_REFRESH,
 212         .mr_calib                       = RW_MGR_MR_CALIB,
 213         .mr_user                        = RW_MGR_MR_USER,
 214         .mr_dll_reset                   = RW_MGR_MR_DLL_RESET,
 215         .emr_ocd_enable                 = RW_MGR_EMR_OCD_ENABLE,
 216 #elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)     /* DDR3 */
 217         .activate_1                     = RW_MGR_ACTIVATE_1,
 218         .idle                           = RW_MGR_IDLE,
 219         .init_reset_0_cke_0             = RW_MGR_INIT_RESET_0_CKE_0,
 220         .init_reset_1_cke_0             = RW_MGR_INIT_RESET_1_CKE_0,
 221         .mrs1                           = RW_MGR_MRS1,
 222         .mrs1_mirr                      = RW_MGR_MRS1_MIRR,
 223         .mrs2                           = RW_MGR_MRS2,
 224         .mrs2_mirr                      = RW_MGR_MRS2_MIRR,
 225         .mrs3                           = RW_MGR_MRS3,
 226         .mrs3_mirr                      = RW_MGR_MRS3_MIRR,
 227         .refresh_all                    = RW_MGR_REFRESH_ALL,
 228         .rreturn                        = RW_MGR_RETURN,
 229         .sgle_read                      = RW_MGR_SGLE_READ,
 230         .zqcl                           = RW_MGR_ZQCL,
 231         .mrs0_dll_reset                 = RW_MGR_MRS0_DLL_RESET,
 232         .mrs0_dll_reset_mirr            = RW_MGR_MRS0_DLL_RESET_MIRR,
 233         .mrs0_user                      = RW_MGR_MRS0_USER,
 234         .mrs0_user_mirr                 = RW_MGR_MRS0_USER_MIRR,
 235 #else
 236 #error LPDDR2 and other DRAM types are not yet supported
 237 #endif
 238         .lfsr_wr_rd_bank_0              = RW_MGR_LFSR_WR_RD_BANK_0,
 239         .lfsr_wr_rd_bank_0_data         = RW_MGR_LFSR_WR_RD_BANK_0_DATA,
 240         .lfsr_wr_rd_bank_0_dqs          = RW_MGR_LFSR_WR_RD_BANK_0_DQS,
 241         .lfsr_wr_rd_bank_0_nop          = RW_MGR_LFSR_WR_RD_BANK_0_NOP,
 242         .lfsr_wr_rd_bank_0_wait         = RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
 243         .lfsr_wr_rd_bank_0_wl_1         = RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
 244         .lfsr_wr_rd_dm_bank_0           = RW_MGR_LFSR_WR_RD_DM_BANK_0,
 245         .lfsr_wr_rd_dm_bank_0_data      = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
 246         .lfsr_wr_rd_dm_bank_0_dqs       = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
 247         .lfsr_wr_rd_dm_bank_0_nop       = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
 248         .lfsr_wr_rd_dm_bank_0_wait      = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
 249         .lfsr_wr_rd_dm_bank_0_wl_1      = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
 250         .precharge_all                  = RW_MGR_PRECHARGE_ALL,
 251         .read_b2b                       = RW_MGR_READ_B2B,
 252         .read_b2b_wait1                 = RW_MGR_READ_B2B_WAIT1,
 253         .read_b2b_wait2                 = RW_MGR_READ_B2B_WAIT2,
 254
 255         .true_mem_data_mask_width       = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
 256         .mem_address_mirroring          = RW_MGR_MEM_ADDRESS_MIRRORING,
 257         .mem_data_mask_width            = RW_MGR_MEM_DATA_MASK_WIDTH,
 258         .mem_data_width                 = RW_MGR_MEM_DATA_WIDTH,
 259         .mem_dq_per_read_dqs            = RW_MGR_MEM_DQ_PER_READ_DQS,
 260         .mem_dq_per_write_dqs           = RW_MGR_MEM_DQ_PER_WRITE_DQS,
 261         .mem_if_read_dqs_width          = RW_MGR_MEM_IF_READ_DQS_WIDTH,
 262         .mem_if_write_dqs_width         = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
 263         .mem_number_of_cs_per_dimm      = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
 264         .mem_number_of_ranks            = RW_MGR_MEM_NUMBER_OF_RANKS,
 265         .mem_virtual_groups_per_read_dqs =
 266                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
 267         .mem_virtual_groups_per_write_dqs =
 268                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
 269 };
 270
 271 static const struct socfpga_sdram_io_config io_config = {
 272         .delay_per_dchain_tap           = IO_DELAY_PER_DCHAIN_TAP,
 273         .delay_per_dqs_en_dchain_tap    = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
 274         .delay_per_opa_tap              = IO_DELAY_PER_OPA_TAP,
 275         .dll_chain_length               = IO_DLL_CHAIN_LENGTH,
 276         .dqdqs_out_phase_max            = IO_DQDQS_OUT_PHASE_MAX,
 277         .dqs_en_delay_max               = IO_DQS_EN_DELAY_MAX,
 278         .dqs_en_delay_offset            = IO_DQS_EN_DELAY_OFFSET,
 279         .dqs_en_phase_max               = IO_DQS_EN_PHASE_MAX,
 280         .dqs_in_delay_max               = IO_DQS_IN_DELAY_MAX,
 281         .dqs_in_reserve                 = IO_DQS_IN_RESERVE,
 282         .dqs_out_reserve                = IO_DQS_OUT_RESERVE,
 283         .io_in_delay_max                = IO_IO_IN_DELAY_MAX,
 284         .io_out1_delay_max              = IO_IO_OUT1_DELAY_MAX,
 285         .io_out2_delay_max              = IO_IO_OUT2_DELAY_MAX,
 286         .shift_dqs_en_when_shift_dqs    = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
 287 };
 288
 289 static const struct socfpga_sdram_misc_config misc_config = {
 290 #if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1)       /* DDR2 */
 291         .afi_clk_freq                   = AFI_CLK_FREQ,
 292 #endif
 293         .afi_rate_ratio                 = AFI_RATE_RATIO,
 294         .calib_lfifo_offset             = CALIB_LFIFO_OFFSET,
 295         .calib_vfifo_offset             = CALIB_VFIFO_OFFSET,
 296         .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
 297         .max_latency_count_width        = MAX_LATENCY_COUNT_WIDTH,
 298         .read_valid_fifo_size           = READ_VALID_FIFO_SIZE,
 299         .reg_file_init_seq_signature    = REG_FILE_INIT_SEQ_SIGNATURE,
 300         .tinit_cntr0_val                = TINIT_CNTR0_VAL,
 301         .tinit_cntr1_val                = TINIT_CNTR1_VAL,
 302         .tinit_cntr2_val                = TINIT_CNTR2_VAL,
 303         .treset_cntr0_val               = TRESET_CNTR0_VAL,
 304         .treset_cntr1_val               = TRESET_CNTR1_VAL,
 305         .treset_cntr2_val               = TRESET_CNTR2_VAL,
 306 };
 307
 308 const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
 309 {
 310         return &sdram_config;
 311 }
 312
 313 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
 314 {
 315         *init = ac_rom_init;
 316         *nelem = ARRAY_SIZE(ac_rom_init);
 317 }
 318
 319 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
 320 {
 321         *init = inst_rom_init;
 322         *nelem = ARRAY_SIZE(inst_rom_init);
 323 }
 324
 325 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
 326 {
 327         return &rw_mgr_config;
 328 }
 329
 330 const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
 331 {
 332         return &io_config;
 333 }
 334
 335 const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
 336 {
 337         return &misc_config;
 338 }