board/freescale/t208xqds/t208xqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2009-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <env.h>
  10 #include <fdt_support.h>
  11 #include <i2c.h>
  12 #include <image.h>
  13 #include <init.h>
  14 #include <netdev.h>
  15 #include <linux/compiler.h>
  16 #include <asm/mmu.h>
  17 #include <asm/processor.h>
  18 #include <asm/immap_85xx.h>
  19 #include <asm/fsl_law.h>
  20 #include <asm/fsl_serdes.h>
  21 #include <asm/fsl_liodn.h>
  22 #include <fm_eth.h>
  23
  24 #include "../common/qixis.h"
  25 #include "../common/vsc3316_3308.h"
  26 #include "../common/vid.h"
  27 #include "t208xqds.h"
  28 #include "t208xqds_qixis.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 int checkboard(void)
  33 {
  34         char buf[64];
  35         u8 sw;
  36         struct cpu_type *cpu = gd->arch.cpu;
  37         static const char *freq[4] = {
  38                 "100.00MHZ(from 8T49N222A)", "125.00MHz",
  39                 "156.25MHZ", "100.00MHz"
  40         };
  41
  42         printf("Board: %sQDS, ", cpu->name);
  43         sw = QIXIS_READ(arch);
  44         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  45         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  46
  47 #ifdef CONFIG_SDCARD
  48         puts("SD/MMC\n");
  49 #elif CONFIG_SPIFLASH
  50         puts("SPI\n");
  51 #else
  52         sw = QIXIS_READ(brdcfg[0]);
  53         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  54
  55         if (sw < 0x8)
  56                 printf("vBank%d\n", sw);
  57         else if (sw == 0x8)
  58                 puts("Promjet\n");
  59         else if (sw == 0x9)
  60                 puts("NAND\n");
  61         else
  62                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  63 #endif
  64
  65         printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  66                qixis_read_tag(buf), (int)qixis_read_minor());
  67         /* the timestamp string contains "\n" at the end */
  68         printf(" on %s", qixis_read_time(buf));
  69
  70         puts("SERDES Reference Clocks:\n");
  71         sw = QIXIS_READ(brdcfg[2]);
  72         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  73                freq[(sw >> 4) & 0x3]);
  74         printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  75                freq[sw & 0x3]);
  76
  77         return 0;
  78 }
  79
  80 int select_i2c_ch_pca9547(u8 ch, int bus_num)
  81 {
  82         int ret;
  83
  84 #ifdef CONFIG_DM_I2C
  85         struct udevice *dev;
  86
  87         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  88         if (ret) {
  89                 printf("%s: Cannot find udev for a bus %d\n", __func__,
  90                        bus_num);
  91                 return ret;
  92         }
  93         ret = dm_i2c_write(dev, 0, &ch, 1);
  94 #else
  95         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  96 #endif
  97         if (ret) {
  98                 puts("PCA: failed to select proper channel\n");
  99                 return ret;
 100         }
 101
 102         return 0;
 103 }
 104
 105 int i2c_multiplexer_select_vid_channel(u8 channel)
 106 {
 107         return select_i2c_ch_pca9547(channel, 0);
 108 }
 109
 110 int brd_mux_lane_to_slot(void)
 111 {
 112         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 113         u32 srds_prtcl_s1;
 114
 115         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 116                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 117         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 118 #if defined(CONFIG_TARGET_T2080QDS)
 119         u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 120                                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 121         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 122 #endif
 123
 124         switch (srds_prtcl_s1) {
 125         case 0:
 126                 /* SerDes1 is not enabled */
 127                 break;
 128 #if defined(CONFIG_TARGET_T2080QDS)
 129         case 0x1b:
 130         case 0x1c:
 131         case 0xa2:
 132                 /* SD1(A:D) => SLOT3 SGMII
 133                  * SD1(G:H) => SLOT1 SGMII
 134                  */
 135                 QIXIS_WRITE(brdcfg[12], 0x1a);
 136                 break;
 137         case 0x94:
 138         case 0x95:
 139                 /* SD1(A:B) => SLOT3 [email protected]
 140                  * SD1(C:D) => SFP Module, [email protected]
 141                  * SD1(E:H) => SLOT1 [email protected]
 142                  */
 143         case 0x96:
 144                 /* SD1(A:B) => SLOT3 [email protected]
 145                  * SD1(C)   => SFP Module, [email protected]
 146                  * SD1(D)   => SFP Module, [email protected]
 147                  * SD1(E:H) => SLOT1 PCIe4 x4
 148                  */
 149                 QIXIS_WRITE(brdcfg[12], 0x3a);
 150                 break;
 151         case 0x50:
 152         case 0x51:
 153                 /* SD1(A:D) => SLOT3 XAUI
 154                  * SD1(E)   => SLOT1 PCIe4
 155                  * SD1(F:H) => SLOT2 SGMII
 156                  */
 157                 QIXIS_WRITE(brdcfg[12], 0x15);
 158                 break;
 159         case 0x66:
 160         case 0x67:
 161                 /* SD1(A:D) => XFI cage
 162                  * SD1(E:H) => SLOT1 PCIe4
 163                  */
 164                 QIXIS_WRITE(brdcfg[12], 0xfe);
 165                 break;
 166         case 0x6a:
 167         case 0x6b:
 168                 /* SD1(A:D) => XFI cage
 169                  * SD1(E)   => SLOT1 PCIe4
 170                  * SD1(F:H) => SLOT2 SGMII
 171                  */
 172                 QIXIS_WRITE(brdcfg[12], 0xf1);
 173                 break;
 174         case 0x6c:
 175         case 0x6d:
 176                 /* SD1(A:B) => XFI cage
 177                  * SD1(C:D) => SLOT3 SGMII
 178                  * SD1(E:H) => SLOT1 PCIe4
 179                  */
 180                 QIXIS_WRITE(brdcfg[12], 0xda);
 181                 break;
 182         case 0x6e:
 183                 /* SD1(A:B) => SFP Module, XFI
 184                  * SD1(C:D) => SLOT3 SGMII
 185                  * SD1(E:F) => SLOT1 PCIe4 x2
 186                  * SD1(G:H) => SLOT2 SGMII
 187                  */
 188                 QIXIS_WRITE(brdcfg[12], 0xd9);
 189                 break;
 190         case 0xda:
 191                 /* SD1(A:H) => SLOT3 PCIe3 x8
 192                  */
 193                  QIXIS_WRITE(brdcfg[12], 0x0);
 194                  break;
 195         case 0xc8:
 196                 /* SD1(A)   => SLOT3 PCIe3 x1
 197                  * SD1(B)   => SFP Module, [email protected]
 198                  * SD1(C:D) => SFP Module, [email protected]
 199                  * SD1(E:F) => SLOT1 PCIe4 x2
 200                  * SD1(G:H) => SLOT2 SGMII
 201                  */
 202                  QIXIS_WRITE(brdcfg[12], 0x79);
 203                  break;
 204         case 0xab:
 205                 /* SD1(A:D) => SLOT3 PCIe3 x4
 206                  * SD1(E:H) => SLOT1 PCIe4 x4
 207                  */
 208                  QIXIS_WRITE(brdcfg[12], 0x1a);
 209                  break;
 210 #elif defined(CONFIG_TARGET_T2081QDS)
 211         case 0x50:
 212         case 0x51:
 213                 /* SD1(A:D) => SLOT2 XAUI
 214                  * SD1(E)   => SLOT1 PCIe4 x1
 215                  * SD1(F:H) => SLOT3 SGMII
 216                  */
 217                 QIXIS_WRITE(brdcfg[12], 0x98);
 218                 QIXIS_WRITE(brdcfg[13], 0x70);
 219                 break;
 220         case 0x6a:
 221         case 0x6b:
 222                 /* SD1(A:D) => XFI SFP Module
 223                  * SD1(E)   => SLOT1 PCIe4 x1
 224                  * SD1(F:H) => SLOT3 SGMII
 225                  */
 226                 QIXIS_WRITE(brdcfg[12], 0x80);
 227                 QIXIS_WRITE(brdcfg[13], 0x70);
 228                 break;
 229         case 0x6c:
 230         case 0x6d:
 231                 /* SD1(A:B) => XFI SFP Module
 232                  * SD1(C:D) => SLOT2 SGMII
 233                  * SD1(E:H) => SLOT1 PCIe4 x4
 234                  */
 235                 QIXIS_WRITE(brdcfg[12], 0xe8);
 236                 QIXIS_WRITE(brdcfg[13], 0x0);
 237                 break;
 238         case 0xaa:
 239         case 0xab:
 240                 /* SD1(A:D) => SLOT2 PCIe3 x4
 241                  * SD1(F:H) => SLOT1 SGMI4 x4
 242                  */
 243                 QIXIS_WRITE(brdcfg[12], 0xf8);
 244                 QIXIS_WRITE(brdcfg[13], 0x0);
 245                 break;
 246         case 0xca:
 247         case 0xcb:
 248                 /* SD1(A)   => SLOT2 PCIe3 x1
 249                  * SD1(B)   => SLOT7 SGMII
 250                  * SD1(C)   => SLOT6 SGMII
 251                  * SD1(D)   => SLOT5 SGMII
 252                  * SD1(E)   => SLOT1 PCIe4 x1
 253                  * SD1(F:H) => SLOT3 SGMII
 254                  */
 255                 QIXIS_WRITE(brdcfg[12], 0x80);
 256                 QIXIS_WRITE(brdcfg[13], 0x70);
 257                 break;
 258         case 0xde:
 259         case 0xdf:
 260                 /* SD1(A:D) => SLOT2 PCIe3 x4
 261                  * SD1(E)   => SLOT1 PCIe4 x1
 262                  * SD1(F)   => SLOT4 PCIe1 x1
 263                  * SD1(G)   => SLOT3 PCIe2 x1
 264                  * SD1(H)   => SLOT7 SGMII
 265                  */
 266                 QIXIS_WRITE(brdcfg[12], 0x98);
 267                 QIXIS_WRITE(brdcfg[13], 0x25);
 268                 break;
 269         case 0xf2:
 270                 /* SD1(A)   => SLOT2 PCIe3 x1
 271                  * SD1(B:D) => SLOT7 SGMII
 272                  * SD1(E)   => SLOT1 PCIe4 x1
 273                  * SD1(F)   => SLOT4 PCIe1 x1
 274                  * SD1(G)   => SLOT3 PCIe2 x1
 275                  * SD1(H)   => SLOT7 SGMII
 276                  */
 277                 QIXIS_WRITE(brdcfg[12], 0x81);
 278                 QIXIS_WRITE(brdcfg[13], 0xa5);
 279                 break;
 280 #endif
 281         default:
 282                 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
 283                        srds_prtcl_s1);
 284                 return -1;
 285         }
 286
 287 #ifdef CONFIG_TARGET_T2080QDS
 288         switch (srds_prtcl_s2) {
 289         case 0:
 290                 /* SerDes2 is not enabled */
 291                 break;
 292         case 0x01:
 293         case 0x02:
 294                 /* SD2(A:H) => SLOT4 PCIe1 */
 295                 QIXIS_WRITE(brdcfg[13], 0x10);
 296                 break;
 297         case 0x15:
 298         case 0x16:
 299                 /*
 300                  * SD2(A:D) => SLOT4 PCIe1
 301                  * SD2(E:F) => SLOT5 PCIe2
 302                  * SD2(G:H) => SATA1,SATA2
 303                  */
 304                 QIXIS_WRITE(brdcfg[13], 0xb0);
 305                 break;
 306         case 0x18:
 307                 /*
 308                  * SD2(A:D) => SLOT4 PCIe1
 309                  * SD2(E:F) => SLOT5 Aurora
 310                  * SD2(G:H) => SATA1,SATA2
 311                  */
 312                 QIXIS_WRITE(brdcfg[13], 0x78);
 313                 break;
 314         case 0x1f:
 315                 /*
 316                  * SD2(A:D) => SLOT4 PCIe1
 317                  * SD2(E:H) => SLOT5 PCIe2
 318                  */
 319                 QIXIS_WRITE(brdcfg[13], 0xa0);
 320                 break;
 321         case 0x29:
 322         case 0x2d:
 323         case 0x2e:
 324                 /*
 325                  * SD2(A:D) => SLOT4 SRIO2
 326                  * SD2(E:H) => SLOT5 SRIO1
 327                  */
 328                 QIXIS_WRITE(brdcfg[13], 0xa0);
 329                 break;
 330         case 0x36:
 331                 /*
 332                  * SD2(A:D) => SLOT4 SRIO2
 333                  * SD2(E:F) => Aurora
 334                  * SD2(G:H) => SATA1,SATA2
 335                  */
 336                 QIXIS_WRITE(brdcfg[13], 0x78);
 337                 break;
 338         default:
 339                 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
 340                        srds_prtcl_s2);
 341                 return -1;
 342         }
 343 #endif
 344         return 0;
 345 }
 346
 347 int board_early_init_r(void)
 348 {
 349         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 350         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 351
 352         /*
 353          * Remap Boot flash + PROMJET region to caching-inhibited
 354          * so that flash can be erased properly.
 355          */
 356
 357         /* Flush d-cache and invalidate i-cache of any FLASH data */
 358         flush_dcache();
 359         invalidate_icache();
 360
 361         if (flash_esel == -1) {
 362                 /* very unlikely unless something is messed up */
 363                 puts("Error: Could not find TLB for FLASH BASE\n");
 364                 flash_esel = 2; /* give our best effort to continue */
 365         } else {
 366                 /* invalidate existing TLB entry for flash + promjet */
 367                 disable_tlb(flash_esel);
 368         }
 369
 370         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 371                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 372                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 373
 374         /* Disable remote I2C connection to qixis fpga */
 375         QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 376
 377         /*
 378          * Adjust core voltage according to voltage ID
 379          * This function changes I2C mux to channel 2.
 380          */
 381         if (adjust_vdd(0))
 382                 printf("Warning: Adjusting core voltage failed.\n");
 383
 384         brd_mux_lane_to_slot();
 385         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 386
 387         return 0;
 388 }
 389
 390 unsigned long get_board_sys_clk(void)
 391 {
 392         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 393 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 394         /* use accurate clock measurement */
 395         int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
 396         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 397         u32 val;
 398
 399         val =  freq * base;
 400         if (val) {
 401                 debug("SYS Clock measurement is: %d\n", val);
 402                 return val;
 403         } else {
 404                 printf("Warning: SYS clock measurement is invalid, ");
 405                 printf("using value from brdcfg1.\n");
 406         }
 407 #endif
 408
 409         switch (sysclk_conf & 0x0F) {
 410         case QIXIS_SYSCLK_83:
 411                 return 83333333;
 412         case QIXIS_SYSCLK_100:
 413                 return 100000000;
 414         case QIXIS_SYSCLK_125:
 415                 return 125000000;
 416         case QIXIS_SYSCLK_133:
 417                 return 133333333;
 418         case QIXIS_SYSCLK_150:
 419                 return 150000000;
 420         case QIXIS_SYSCLK_160:
 421                 return 160000000;
 422         case QIXIS_SYSCLK_166:
 423                 return 166666666;
 424         }
 425         return 66666666;
 426 }
 427
 428 unsigned long get_board_ddr_clk(void)
 429 {
 430         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 431 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 432         /* use accurate clock measurement */
 433         int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
 434         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 435         u32 val;
 436
 437         val =  freq * base;
 438         if (val) {
 439                 debug("DDR Clock measurement is: %d\n", val);
 440                 return val;
 441         } else {
 442                 printf("Warning: DDR clock measurement is invalid, ");
 443                 printf("using value from brdcfg1.\n");
 444         }
 445 #endif
 446
 447         switch ((ddrclk_conf & 0x30) >> 4) {
 448         case QIXIS_DDRCLK_100:
 449                 return 100000000;
 450         case QIXIS_DDRCLK_125:
 451                 return 125000000;
 452         case QIXIS_DDRCLK_133:
 453                 return 133333333;
 454         }
 455         return 66666666;
 456 }
 457
 458 int misc_init_r(void)
 459 {
 460         return 0;
 461 }
 462
 463 int ft_board_setup(void *blob, bd_t *bd)
 464 {
 465         phys_addr_t base;
 466         phys_size_t size;
 467
 468         ft_cpu_setup(blob, bd);
 469
 470         base = env_get_bootm_low();
 471         size = env_get_bootm_size();
 472
 473         fdt_fixup_memory(blob, (u64)base, (u64)size);
 474
 475 #ifdef CONFIG_PCI
 476         pci_of_setup(blob, bd);
 477 #endif
 478
 479         fdt_fixup_liodn(blob);
 480         fsl_fdt_fixup_dr_usb(blob, bd);
 481
 482 #ifdef CONFIG_SYS_DPAA_FMAN
 483         fdt_fixup_fman_ethernet(blob);
 484         fdt_fixup_board_enet(blob);
 485 #endif
 486
 487         return 0;
 488 }