drivers/clk/sunxi/clk_a31.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2018 Amarula Solutions B.V.
   4  * Author: Jagan Teki <[email protected]>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <asm/arch/ccu.h>
  12 #include <dt-bindings/clock/sun6i-a31-ccu.h>
  13 #include <dt-bindings/reset/sun6i-a31-ccu.h>
  14 #include <linux/bitops.h>
  15
  16 static struct ccu_clk_gate a31_gates[] = {
  17         [CLK_AHB1_MMC0]         = GATE(0x060, BIT(8)),
  18         [CLK_AHB1_MMC1]         = GATE(0x060, BIT(9)),
  19         [CLK_AHB1_MMC2]         = GATE(0x060, BIT(10)),
  20         [CLK_AHB1_MMC3]         = GATE(0x060, BIT(11)),
  21         [CLK_AHB1_EMAC]         = GATE(0x060, BIT(17)),
  22         [CLK_AHB1_SPI0]         = GATE(0x060, BIT(20)),
  23         [CLK_AHB1_SPI1]         = GATE(0x060, BIT(21)),
  24         [CLK_AHB1_SPI2]         = GATE(0x060, BIT(22)),
  25         [CLK_AHB1_SPI3]         = GATE(0x060, BIT(23)),
  26         [CLK_AHB1_OTG]          = GATE(0x060, BIT(24)),
  27         [CLK_AHB1_EHCI0]        = GATE(0x060, BIT(26)),
  28         [CLK_AHB1_EHCI1]        = GATE(0x060, BIT(27)),
  29         [CLK_AHB1_OHCI0]        = GATE(0x060, BIT(29)),
  30         [CLK_AHB1_OHCI1]        = GATE(0x060, BIT(30)),
  31         [CLK_AHB1_OHCI2]        = GATE(0x060, BIT(31)),
  32
  33         [CLK_APB2_UART0]        = GATE(0x06c, BIT(16)),
  34         [CLK_APB2_UART1]        = GATE(0x06c, BIT(17)),
  35         [CLK_APB2_UART2]        = GATE(0x06c, BIT(18)),
  36         [CLK_APB2_UART3]        = GATE(0x06c, BIT(19)),
  37         [CLK_APB2_UART4]        = GATE(0x06c, BIT(20)),
  38         [CLK_APB2_UART5]        = GATE(0x06c, BIT(21)),
  39
  40         [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
  41         [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
  42         [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
  43         [CLK_SPI3]              = GATE(0x0ac, BIT(31)),
  44
  45         [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
  46         [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
  47         [CLK_USB_PHY2]          = GATE(0x0cc, BIT(10)),
  48         [CLK_USB_OHCI0]         = GATE(0x0cc, BIT(16)),
  49         [CLK_USB_OHCI1]         = GATE(0x0cc, BIT(17)),
  50         [CLK_USB_OHCI2]         = GATE(0x0cc, BIT(18)),
  51 };
  52
  53 static struct ccu_reset a31_resets[] = {
  54         [RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
  55         [RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
  56         [RST_USB_PHY2]          = RESET(0x0cc, BIT(2)),
  57
  58         [RST_AHB1_MMC0]         = RESET(0x2c0, BIT(8)),
  59         [RST_AHB1_MMC1]         = RESET(0x2c0, BIT(9)),
  60         [RST_AHB1_MMC2]         = RESET(0x2c0, BIT(10)),
  61         [RST_AHB1_MMC3]         = RESET(0x2c0, BIT(11)),
  62         [RST_AHB1_EMAC]         = RESET(0x2c0, BIT(17)),
  63         [RST_AHB1_SPI0]         = RESET(0x2c0, BIT(20)),
  64         [RST_AHB1_SPI1]         = RESET(0x2c0, BIT(21)),
  65         [RST_AHB1_SPI2]         = RESET(0x2c0, BIT(22)),
  66         [RST_AHB1_SPI3]         = RESET(0x2c0, BIT(23)),
  67         [RST_AHB1_OTG]          = RESET(0x2c0, BIT(24)),
  68         [RST_AHB1_EHCI0]        = RESET(0x2c0, BIT(26)),
  69         [RST_AHB1_EHCI1]        = RESET(0x2c0, BIT(27)),
  70         [RST_AHB1_OHCI0]        = RESET(0x2c0, BIT(29)),
  71         [RST_AHB1_OHCI1]        = RESET(0x2c0, BIT(30)),
  72         [RST_AHB1_OHCI2]        = RESET(0x2c0, BIT(31)),
  73
  74         [RST_APB2_UART0]        = RESET(0x2d8, BIT(16)),
  75         [RST_APB2_UART1]        = RESET(0x2d8, BIT(17)),
  76         [RST_APB2_UART2]        = RESET(0x2d8, BIT(18)),
  77         [RST_APB2_UART3]        = RESET(0x2d8, BIT(19)),
  78         [RST_APB2_UART4]        = RESET(0x2d8, BIT(20)),
  79         [RST_APB2_UART5]        = RESET(0x2d8, BIT(21)),
  80 };
  81
  82 static const struct ccu_desc a31_ccu_desc = {
  83         .gates = a31_gates,
  84         .resets = a31_resets,
  85 };
  86
  87 static int a31_clk_bind(struct udevice *dev)
  88 {
  89         return sunxi_reset_bind(dev, ARRAY_SIZE(a31_resets));
  90 }
  91
  92 static const struct udevice_id a31_clk_ids[] = {
  93         { .compatible = "allwinner,sun6i-a31-ccu",
  94           .data = (ulong)&a31_ccu_desc },
  95         { }
  96 };
  97
  98 U_BOOT_DRIVER(clk_sun6i_a31) = {
  99         .name           = "sun6i_a31_ccu",
 100         .id             = UCLASS_CLK,
 101         .of_match       = a31_clk_ids,
 102         .priv_auto      = sizeof(struct ccu_priv),
 103         .ops            = &sunxi_clk_ops,
 104         .probe          = sunxi_clk_probe,
 105         .bind           = a31_clk_bind,
 106 };