include/configs/hrcon.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, [email protected]
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  16 #define CONFIG_HRCON            1 /* HRCON board specific */
  17
  18 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  19
  20 /*
  21  * System Clock Setup
  22  */
  23 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  24 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  25
  26 /*
  27  * Hardware Reset Configuration Word
  28  * if CLKIN is 66.66MHz, then
  29  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  30  * We choose the A type silicon as default, so the core is 400Mhz.
  31  */
  32 #define CONFIG_SYS_HRCW_LOW (\
  33         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  34         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  35         HRCWL_SVCOD_DIV_2 |\
  36         HRCWL_CSB_TO_CLKIN_4X1 |\
  37         HRCWL_CORE_TO_CSB_3X1)
  38 /*
  39  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  40  * in 8308's HRCWH according to the manual, but original Freescale's
  41  * code has them and I've expirienced some problems using the board
  42  * with BDI3000 attached when I've tried to set these bits to zero
  43  * (UART doesn't work after the 'reset run' command).
  44  */
  45 #define CONFIG_SYS_HRCW_HIGH (\
  46         HRCWH_PCI_HOST |\
  47         HRCWH_PCI1_ARBITER_ENABLE |\
  48         HRCWH_CORE_ENABLE |\
  49         HRCWH_FROM_0XFFF00100 |\
  50         HRCWH_BOOTSEQ_DISABLE |\
  51         HRCWH_SW_WATCHDOG_DISABLE |\
  52         HRCWH_ROM_LOC_LOCAL_16BIT |\
  53         HRCWH_RL_EXT_LEGACY |\
  54         HRCWH_TSEC1M_IN_RGMII |\
  55         HRCWH_TSEC2M_IN_RGMII |\
  56         HRCWH_BIG_ENDIAN)
  57
  58 /*
  59  * System IO Config
  60  */
  61 #define CONFIG_SYS_SICRH (\
  62         SICRH_ESDHC_A_SD |\
  63         SICRH_ESDHC_B_SD |\
  64         SICRH_ESDHC_C_SD |\
  65         SICRH_GPIO_A_GPIO |\
  66         SICRH_GPIO_B_GPIO |\
  67         SICRH_IEEE1588_A_GPIO |\
  68         SICRH_USB |\
  69         SICRH_GTM_GPIO |\
  70         SICRH_IEEE1588_B_GPIO |\
  71         SICRH_ETSEC2_GPIO |\
  72         SICRH_GPIOSEL_1 |\
  73         SICRH_TMROBI_V3P3 |\
  74         SICRH_TSOBI1_V2P5 |\
  75         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
  76 #define CONFIG_SYS_SICRL (\
  77         SICRL_SPI_PF0 |\
  78         SICRL_UART_PF0 |\
  79         SICRL_IRQ_PF0 |\
  80         SICRL_I2C2_PF0 |\
  81         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
  82
  83 /*
  84  * IMMR new address
  85  */
  86 #define CONFIG_SYS_IMMR         0xE0000000
  87
  88 /*
  89  * SERDES
  90  */
  91 #define CONFIG_FSL_SERDES
  92 #define CONFIG_FSL_SERDES1      0xe3000
  93
  94 /*
  95  * Arbiter Setup
  96  */
  97 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  98 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  99 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 100
 101 /*
 102  * DDR Setup
 103  */
 104 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 105 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 106 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 107 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 108 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 109                                 | DDRCDR_PZ_LOZ \
 110                                 | DDRCDR_NZ_LOZ \
 111                                 | DDRCDR_ODT \
 112                                 | DDRCDR_Q_DRN)
 113                                 /* 0x7b880001 */
 114 /*
 115  * Manually set up DDR parameters
 116  * consist of one chip NT5TU64M16HG from NANYA
 117  */
 118
 119 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 120
 121 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 122 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 123                                 | CSCONFIG_ODT_RD_NEVER \
 124                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 125                                 | CSCONFIG_BANK_BIT_3 \
 126                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 127                                 /* 0x80010102 */
 128 #define CONFIG_SYS_DDR_TIMING_3 0
 129 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 130                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 131                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 132                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 133                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 134                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 135                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 136                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 137                                 /* 0x00260802 */
 138 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 139                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 140                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 141                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 142                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
 143                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 144                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 145                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 146                                 /* 0x26279222 */
 147 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 148                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 149                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 150                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 151                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 152                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 153                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 154                                 /* 0x021848c5 */
 155 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 156                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 157                                 /* 0x08240100 */
 158 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 159                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 160                                 | SDRAM_CFG_DBW_16)
 161                                 /* 0x43100000 */
 162
 163 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 164 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 165                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 166                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 167 #define CONFIG_SYS_DDR_MODE2            0x00000000
 168
 169 /*
 170  * Memory test
 171  */
 172 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 173 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 174
 175 /*
 176  * The reserved memory
 177  */
 178 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 179
 180 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 181 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 182
 183 /*
 184  * Initial RAM Base Address Setup
 185  */
 186 #define CONFIG_SYS_INIT_RAM_LOCK        1
 187 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 188 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 189 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 190         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 191
 192 /*
 193  * Local Bus Configuration & Clock Setup
 194  */
 195 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 196 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 197 #define CONFIG_SYS_LBC_LBCR             0x00040000
 198
 199 /*
 200  * FLASH on the Local Bus
 201  */
 202 #if 1
 203 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 204 #define CONFIG_FLASH_CFI_LEGACY
 205 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 206 #endif
 207
 208 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 209 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 210
 211 /* Window base at flash base */
 212 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 213 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 214
 215 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 216                                 | BR_PS_16      /* 16 bit port */ \
 217                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 218                                 | BR_V)         /* valid */
 219 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 220                                 | OR_UPM_XAM \
 221                                 | OR_GPCM_CSNT \
 222                                 | OR_GPCM_ACS_DIV2 \
 223                                 | OR_GPCM_XACS \
 224                                 | OR_GPCM_SCY_15 \
 225                                 | OR_GPCM_TRLX_SET \
 226                                 | OR_GPCM_EHTR_SET)
 227
 228 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 229 #define CONFIG_SYS_MAX_FLASH_SECT       135
 230
 231 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 232 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 233
 234 /*
 235  * FPGA
 236  */
 237 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 238 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 239
 240 /* Window base at FPGA base */
 241 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA0_BASE
 242 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_1MB)
 243
 244 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
 245                                 | BR_PS_16      /* 16 bit port */ \
 246                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 247                                 | BR_V)         /* valid */
 248 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
 249                                 | OR_UPM_XAM \
 250                                 | OR_GPCM_CSNT \
 251                                 | OR_GPCM_ACS_DIV2 \
 252                                 | OR_GPCM_XACS \
 253                                 | OR_GPCM_SCY_15 \
 254                                 | OR_GPCM_TRLX_SET \
 255                                 | OR_GPCM_EHTR_SET)
 256
 257 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 258 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 259
 260 #define CONFIG_SYS_FPGA_COUNT           1
 261
 262 #define CONFIG_SYS_MCLINK_MAX           3
 263
 264 #define CONFIG_SYS_FPGA_PTR \
 265         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 266
 267 /*
 268  * Serial Port
 269  */
 270 #define CONFIG_SYS_NS16550_SERIAL
 271 #define CONFIG_SYS_NS16550_REG_SIZE     1
 272 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 273
 274 #define CONFIG_SYS_BAUDRATE_TABLE  \
 275         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 276
 277 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 278 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 279
 280 /* Pass open firmware flat tree */
 281
 282 /* I2C */
 283 #define CONFIG_SYS_I2C
 284 #define CONFIG_SYS_I2C_FSL
 285 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 286 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 287 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 288
 289 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 290 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 291
 292 #define CONFIG_SYS_I2C_IHS
 293 #define CONFIG_SYS_I2C_IHS_CH0
 294 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 295 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 296 #define CONFIG_SYS_I2C_IHS_CH1
 297 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 298 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 299 #define CONFIG_SYS_I2C_IHS_CH2
 300 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 301 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 302 #define CONFIG_SYS_I2C_IHS_CH3
 303 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 304 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 305
 306 #ifdef CONFIG_HRCON_DH
 307 #define CONFIG_SYS_I2C_IHS_DUAL
 308 #define CONFIG_SYS_I2C_IHS_CH0_1
 309 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 310 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 311 #define CONFIG_SYS_I2C_IHS_CH1_1
 312 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 313 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 314 #define CONFIG_SYS_I2C_IHS_CH2_1
 315 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 316 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 317 #define CONFIG_SYS_I2C_IHS_CH3_1
 318 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 319 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 320 #endif
 321
 322 /*
 323  * Software (bit-bang) I2C driver configuration
 324  */
 325 #define CONFIG_SYS_I2C_SOFT
 326 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 327 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 328 #define I2C_SOFT_DECLARATIONS2
 329 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 330 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 331 #define I2C_SOFT_DECLARATIONS3
 332 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 333 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 334 #define I2C_SOFT_DECLARATIONS4
 335 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 336 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 337 #define I2C_SOFT_DECLARATIONS5
 338 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 339 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 340 #define I2C_SOFT_DECLARATIONS6
 341 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 342 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 343 #define I2C_SOFT_DECLARATIONS7
 344 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 345 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 346 #define I2C_SOFT_DECLARATIONS8
 347 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 348 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 349
 350 #ifdef CONFIG_HRCON_DH
 351 #define I2C_SOFT_DECLARATIONS9
 352 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 353 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 354 #define I2C_SOFT_DECLARATIONS10
 355 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 356 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 357 #define I2C_SOFT_DECLARATIONS11
 358 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 359 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 360 #define I2C_SOFT_DECLARATIONS12
 361 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 362 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 363 #endif
 364
 365 #ifdef CONFIG_HRCON_DH
 366 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 367 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 368 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 369                                                   {12, 0x4c} }
 370 #else
 371 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 372 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 373 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 374                                                   {8, 0x4c} }
 375 #endif
 376
 377 #ifndef __ASSEMBLY__
 378 void fpga_gpio_set(unsigned int bus, int pin);
 379 void fpga_gpio_clear(unsigned int bus, int pin);
 380 int fpga_gpio_get(unsigned int bus, int pin);
 381 void fpga_control_set(unsigned int bus, int pin);
 382 void fpga_control_clear(unsigned int bus, int pin);
 383 #endif
 384
 385 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 386 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 387 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 388
 389 #ifdef CONFIG_HRCON_DH
 390 #define I2C_ACTIVE \
 391         do { \
 392                 if (I2C_ADAP_HWNR > 7) \
 393                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 394                 else \
 395                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 396         } while (0)
 397 #else
 398 #define I2C_ACTIVE      { }
 399 #endif
 400 #define I2C_TRISTATE    { }
 401 #define I2C_READ \
 402         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 403 #define I2C_SDA(bit) \
 404         do { \
 405                 if (bit) \
 406                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 407                 else \
 408                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 409         } while (0)
 410 #define I2C_SCL(bit) \
 411         do { \
 412                 if (bit) \
 413                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 414                 else \
 415                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 416         } while (0)
 417 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 418
 419 /*
 420  * Software (bit-bang) MII driver configuration
 421  */
 422 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 423 #define CONFIG_BITBANGMII_MULTI
 424
 425 /*
 426  * OSD Setup
 427  */
 428 #define CONFIG_SYS_OSD_SCREENS          1
 429 #define CONFIG_SYS_DP501_DIFFERENTIAL
 430 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 431
 432 #ifdef CONFIG_HRCON_DH
 433 #define CONFIG_SYS_OSD_DH
 434 #endif
 435
 436 /*
 437  * General PCI
 438  * Addresses are mapped 1-1.
 439  */
 440 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 441 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 442 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 443 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 444 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 445 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 446 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 447 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 448 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 449
 450 /* enable PCIE clock */
 451 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 452
 453 #define CONFIG_PCI_INDIRECT_BRIDGE
 454 #define CONFIG_PCIE
 455
 456 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 457 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 458
 459 /*
 460  * TSEC
 461  */
 462 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 463 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 464
 465 /*
 466  * TSEC ethernet configuration
 467  */
 468 #define CONFIG_TSEC1
 469 #define CONFIG_TSEC1_NAME       "eTSEC0"
 470 #define TSEC1_PHY_ADDR          1
 471 #define TSEC1_PHYIDX            0
 472 #define TSEC1_FLAGS             TSEC_GIGABIT
 473
 474 /* Options are: eTSEC[0-1] */
 475 #define CONFIG_ETHPRIME         "eTSEC0"
 476
 477 /*
 478  * Environment
 479  */
 480 #if 1
 481 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 482                                  CONFIG_SYS_MONITOR_LEN)
 483 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 484 #define CONFIG_ENV_SIZE         0x2000
 485 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 486 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 487 #else
 488 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 489 #endif
 490
 491 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 492 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 493
 494 /*
 495  * Command line configuration.
 496  */
 497
 498 /*
 499  * Miscellaneous configurable options
 500  */
 501 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 502 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 503
 504 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 505
 506 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 507
 508 /*
 509  * For booting Linux, the board info and command line data
 510  * have to be in the first 256 MB of memory, since this is
 511  * the maximum mapped by the Linux kernel during initialization.
 512  */
 513 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 514
 515 /*
 516  * Core HID Setup
 517  */
 518 #define CONFIG_SYS_HID0_INIT    0x000000000
 519 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 520                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 521                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 522 #define CONFIG_SYS_HID2         HID2_HBE
 523
 524 /*
 525  * MMU Setup
 526  */
 527
 528 /* DDR: cache cacheable */
 529 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 530                                         BATL_MEMCOHERENCE)
 531 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 532                                         BATU_VS | BATU_VP)
 533 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 534 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 535
 536 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
 537 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 538                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 539 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 540                                         BATU_VP)
 541 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 542 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 543
 544 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 545 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 546                                         BATL_MEMCOHERENCE)
 547 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 548                                         BATU_VS | BATU_VP)
 549 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 550                                         BATL_CACHEINHIBIT | \
 551                                         BATL_GUARDEDSTORAGE)
 552 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 553
 554 /* Stack in dcache: cacheable, no memory coherence */
 555 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 556 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 557                                         BATU_VS | BATU_VP)
 558 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 559 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 560
 561 /*
 562  * Environment Configuration
 563  */
 564
 565 #define CONFIG_ENV_OVERWRITE
 566
 567 #if defined(CONFIG_TSEC_ENET)
 568 #define CONFIG_HAS_ETH0
 569 #endif
 570
 571 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 572
 573
 574 #define CONFIG_HOSTNAME         "hrcon"
 575 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 576 #define CONFIG_BOOTFILE         "uImage"
 577
 578 #define CONFIG_PREBOOT          /* enable preboot variable */
 579
 580 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 581         "netdev=eth0\0"                                                 \
 582         "consoledev=ttyS1\0"                                            \
 583         "u-boot=u-boot.bin\0"                                           \
 584         "kernel_addr=1000000\0"                                 \
 585         "fdt_addr=C00000\0"                                             \
 586         "fdtfile=hrcon.dtb\0"                           \
 587         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 588         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 589                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 590                 " +${filesize};cp.b ${fileaddr} "                       \
 591                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 592         "upd=run load update\0"                                         \
 593
 594 #define CONFIG_NFSBOOTCOMMAND                                           \
 595         "setenv bootargs root=/dev/nfs rw "                             \
 596         "nfsroot=$serverip:$rootpath "                                  \
 597         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 598         "console=$consoledev,$baudrate $othbootargs;"                   \
 599         "tftp ${kernel_addr} $bootfile;"                                \
 600         "tftp ${fdt_addr} $fdtfile;"                                    \
 601         "bootm ${kernel_addr} - ${fdt_addr}"
 602
 603 #define CONFIG_MMCBOOTCOMMAND                                           \
 604         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 605         "console=$consoledev,$baudrate $othbootargs;"                   \
 606         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 607         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 608         "bootm ${kernel_addr} - ${fdt_addr}"
 609
 610 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 611
 612 #endif  /* __CONFIG_H */