drivers/net/sni_netsec.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /**
   3  * netsec.c - Socionext Synquacer Netsec driver
   4  * Copyright 2021 Linaro Ltd.
   5  */
   6
   7 #include <clk.h>
   8 #include <cpu_func.h>
   9 #include <dm.h>
  10 #include <fdt_support.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <miiphy.h>
  14 #include <net.h>
  15 #include <regmap.h>
  16 #include <reset.h>
  17 #include <syscon.h>
  18 #include <asm/cache.h>
  19 #include <asm/global_data.h>
  20 #include <dm/device_compat.h>
  21 #include <linux/bitops.h>
  22 #include <linux/delay.h>
  23 #include <linux/err.h>
  24 #include <linux/io.h>
  25 #include <linux/iopoll.h>
  26 #include <spi.h>
  27 #include <spi_flash.h>
  28
  29 #define NETSEC_REG_SOFT_RST                     0x104
  30 #define NETSEC_REG_COM_INIT                     0x120
  31
  32 #define NETSEC_REG_TOP_STATUS                   0x200
  33 #define NETSEC_IRQ_RX                           BIT(1)
  34 #define NETSEC_IRQ_TX                           BIT(0)
  35
  36 #define NETSEC_REG_TOP_INTEN                    0x204
  37 #define NETSEC_REG_INTEN_SET                    0x234
  38 #define NETSEC_REG_INTEN_CLR                    0x238
  39
  40 #define NETSEC_REG_NRM_TX_STATUS                0x400
  41 #define NETSEC_REG_NRM_TX_INTEN                 0x404
  42 #define NETSEC_REG_NRM_TX_INTEN_SET             0x428
  43 #define NETSEC_REG_NRM_TX_INTEN_CLR             0x42c
  44 #define NRM_TX_ST_NTOWNR        BIT(17)
  45 #define NRM_TX_ST_TR_ERR        BIT(16)
  46 #define NRM_TX_ST_TXDONE        BIT(15)
  47 #define NRM_TX_ST_TMREXP        BIT(14)
  48
  49 #define NETSEC_REG_NRM_RX_STATUS                0x440
  50 #define NETSEC_REG_NRM_RX_INTEN                 0x444
  51 #define NETSEC_REG_NRM_RX_INTEN_SET             0x468
  52 #define NETSEC_REG_NRM_RX_INTEN_CLR             0x46c
  53 #define NRM_RX_ST_RC_ERR        BIT(16)
  54 #define NRM_RX_ST_PKTCNT        BIT(15)
  55 #define NRM_RX_ST_TMREXP        BIT(14)
  56
  57 #define NETSEC_REG_PKT_CMD_BUF                  0xd0
  58
  59 #define NETSEC_REG_CLK_EN                       0x100
  60
  61 #define NETSEC_REG_PKT_CTRL                     0x140
  62
  63 #define NETSEC_REG_DMA_TMR_CTRL                 0x20c
  64 #define NETSEC_REG_F_TAIKI_MC_VER               0x22c
  65 #define NETSEC_REG_F_TAIKI_VER                  0x230
  66 #define NETSEC_REG_DMA_HM_CTRL                  0x214
  67 #define NETSEC_REG_DMA_MH_CTRL                  0x220
  68 #define NETSEC_REG_ADDR_DIS_CORE                0x218
  69 #define NETSEC_REG_DMAC_HM_CMD_BUF              0x210
  70 #define NETSEC_REG_DMAC_MH_CMD_BUF              0x21c
  71
  72 #define NETSEC_REG_NRM_TX_PKTCNT                0x410
  73
  74 #define NETSEC_REG_NRM_TX_DONE_PKTCNT           0x414
  75 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT     0x418
  76
  77 #define NETSEC_REG_NRM_TX_TMR                   0x41c
  78
  79 #define NETSEC_REG_NRM_RX_PKTCNT                0x454
  80 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT          0x458
  81 #define NETSEC_REG_NRM_TX_TXINT_TMR             0x420
  82 #define NETSEC_REG_NRM_RX_RXINT_TMR             0x460
  83
  84 #define NETSEC_REG_NRM_RX_TMR                   0x45c
  85
  86 #define NETSEC_REG_NRM_TX_DESC_START_UP         0x434
  87 #define NETSEC_REG_NRM_TX_DESC_START_LW         0x408
  88 #define NETSEC_REG_NRM_RX_DESC_START_UP         0x474
  89 #define NETSEC_REG_NRM_RX_DESC_START_LW         0x448
  90
  91 #define NETSEC_REG_NRM_TX_CONFIG                0x430
  92 #define NETSEC_REG_NRM_RX_CONFIG                0x470
  93
  94 #define MAC_REG_STATUS                          0x1024
  95 #define MAC_REG_DATA                            0x11c0
  96 #define MAC_REG_CMD                             0x11c4
  97 #define MAC_REG_FLOW_TH                         0x11cc
  98 #define MAC_REG_INTF_SEL                        0x11d4
  99 #define MAC_REG_DESC_INIT                       0x11fc
 100 #define MAC_REG_DESC_SOFT_RST                   0x1204
 101 #define NETSEC_REG_MODE_TRANS_COMP_STATUS       0x500
 102
 103 #define GMAC_REG_MCR                            0x0000
 104 #define GMAC_REG_MFFR                           0x0004
 105 #define GMAC_REG_GAR                            0x0010
 106 #define GMAC_REG_GDR                            0x0014
 107 #define GMAC_REG_FCR                            0x0018
 108 #define GMAC_REG_BMR                            0x1000
 109 #define GMAC_REG_RDLAR                          0x100c
 110 #define GMAC_REG_TDLAR                          0x1010
 111 #define GMAC_REG_OMR                            0x1018
 112
 113 #define MHZ(n)          ((n) * 1000 * 1000)
 114
 115 #define NETSEC_TX_SHIFT_OWN_FIELD               31
 116 #define NETSEC_TX_SHIFT_LD_FIELD                30
 117 #define NETSEC_TX_SHIFT_DRID_FIELD              24
 118 #define NETSEC_TX_SHIFT_PT_FIELD                21
 119 #define NETSEC_TX_SHIFT_TDRID_FIELD             16
 120 #define NETSEC_TX_SHIFT_CC_FIELD                15
 121 #define NETSEC_TX_SHIFT_FS_FIELD                9
 122 #define NETSEC_TX_LAST                          8
 123 #define NETSEC_TX_SHIFT_CO                      7
 124 #define NETSEC_TX_SHIFT_SO                      6
 125 #define NETSEC_TX_SHIFT_TRS_FIELD               4
 126
 127 #define NETSEC_RX_PKT_OWN_FIELD                 31
 128 #define NETSEC_RX_PKT_LD_FIELD                  30
 129 #define NETSEC_RX_PKT_SDRID_FIELD               24
 130 #define NETSEC_RX_PKT_FR_FIELD                  23
 131 #define NETSEC_RX_PKT_ER_FIELD                  21
 132 #define NETSEC_RX_PKT_ERR_FIELD                 16
 133 #define NETSEC_RX_PKT_TDRID_FIELD               12
 134 #define NETSEC_RX_PKT_FS_FIELD                  9
 135 #define NETSEC_RX_PKT_LS_FIELD                  8
 136 #define NETSEC_RX_PKT_CO_FIELD                  6
 137
 138 #define NETSEC_RX_PKT_ERR_MASK                  3
 139
 140 #define NETSEC_MAX_TX_PKT_LEN                   1518
 141 #define NETSEC_MAX_TX_JUMBO_PKT_LEN             9018
 142
 143 #define NETSEC_RING_GMAC                        15
 144 #define NETSEC_RING_MAX                         2
 145
 146 #define NETSEC_TCP_SEG_LEN_MAX                  1460
 147 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX            8960
 148
 149 #define NETSEC_RX_CKSUM_NOTAVAIL                0
 150 #define NETSEC_RX_CKSUM_OK                      1
 151 #define NETSEC_RX_CKSUM_NG                      2
 152
 153 #define NETSEC_TOP_IRQ_REG_ME_START                     BIT(20)
 154 #define NETSEC_IRQ_TRANSITION_COMPLETE          BIT(4)
 155
 156 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T          BIT(20)
 157 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N          BIT(19)
 158
 159 #define NETSEC_INT_PKTCNT_MAX                   2047
 160
 161 #define NETSEC_FLOW_START_TH_MAX                95
 162 #define NETSEC_FLOW_STOP_TH_MAX                 95
 163 #define NETSEC_FLOW_PAUSE_TIME_MIN              5
 164
 165 #define NETSEC_CLK_EN_REG_DOM_ALL               0x3f
 166
 167 #define NETSEC_PKT_CTRL_REG_MODE_NRM            BIT(28)
 168 #define NETSEC_PKT_CTRL_REG_EN_JUMBO            BIT(27)
 169 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER       BIT(3)
 170 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE   BIT(2)
 171 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER           BIT(1)
 172 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH        BIT(0)
 173
 174 #define NETSEC_CLK_EN_REG_DOM_G                 BIT(5)
 175 #define NETSEC_CLK_EN_REG_DOM_C                 BIT(1)
 176 #define NETSEC_CLK_EN_REG_DOM_D                 BIT(0)
 177
 178 #define NETSEC_COM_INIT_REG_DB                  BIT(2)
 179 #define NETSEC_COM_INIT_REG_CLS                 BIT(1)
 180 #define NETSEC_COM_INIT_REG_ALL                 (NETSEC_COM_INIT_REG_CLS | \
 181                                                  NETSEC_COM_INIT_REG_DB)
 182
 183 #define NETSEC_SOFT_RST_REG_RESET               0
 184 #define NETSEC_SOFT_RST_REG_RUN                 BIT(31)
 185
 186 #define NETSEC_DMA_CTRL_REG_STOP                1
 187 #define MH_CTRL__MODE_TRANS                     BIT(20)
 188
 189 #define NETSEC_GMAC_CMD_ST_READ                 0
 190 #define NETSEC_GMAC_CMD_ST_WRITE                BIT(28)
 191 #define NETSEC_GMAC_CMD_ST_BUSY                 BIT(31)
 192
 193 #define NETSEC_GMAC_BMR_REG_COMMON              0x00412080
 194 #define NETSEC_GMAC_BMR_REG_RESET               0x00020181
 195 #define NETSEC_GMAC_BMR_REG_SWR                 0x00000001
 196
 197 #define NETSEC_GMAC_OMR_REG_ST                  BIT(13)
 198 #define NETSEC_GMAC_OMR_REG_SR                  BIT(1)
 199
 200 #define NETSEC_GMAC_MCR_REG_IBN                 BIT(30)
 201 #define NETSEC_GMAC_MCR_REG_CST                 BIT(25)
 202 #define NETSEC_GMAC_MCR_REG_JE                  BIT(20)
 203 #define NETSEC_MCR_PS                           BIT(15)
 204 #define NETSEC_GMAC_MCR_REG_FES                 BIT(14)
 205 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON  0x0000280c
 206 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON  0x0001a00c
 207
 208 #define NETSEC_FCR_RFE                          BIT(2)
 209 #define NETSEC_FCR_TFE                          BIT(1)
 210
 211 #define NETSEC_GMAC_GAR_REG_GW                  BIT(1)
 212 #define NETSEC_GMAC_GAR_REG_GB                  BIT(0)
 213
 214 #define NETSEC_GMAC_GAR_REG_SHIFT_PA            11
 215 #define NETSEC_GMAC_GAR_REG_SHIFT_GR            6
 216 #define GMAC_REG_SHIFT_CR_GAR                   2
 217
 218 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ        2
 219 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ        3
 220 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ       0
 221 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ      1
 222 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ      4
 223 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ      5
 224
 225 #define NETSEC_GMAC_RDLAR_REG_COMMON            0x18000
 226 #define NETSEC_GMAC_TDLAR_REG_COMMON            0x1c000
 227
 228 #define NETSEC_REG_NETSEC_VER_F_TAIKI           0x50000
 229
 230 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP      BIT(31)
 231 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST      BIT(30)
 232 #define NETSEC_REG_DESC_TMR_MODE                4
 233 #define NETSEC_REG_DESC_ENDIAN                  0
 234
 235 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST       1
 236 #define NETSEC_MAC_DESC_INIT_REG_INIT           1
 237
 238 #define NETSEC_EEPROM_MAC_ADDRESS               0x00
 239 #define NETSEC_EEPROM_HM_ME_ADDRESS_H           0x08
 240 #define NETSEC_EEPROM_HM_ME_ADDRESS_L           0x0C
 241 #define NETSEC_EEPROM_HM_ME_SIZE                0x10
 242 #define NETSEC_EEPROM_MH_ME_ADDRESS_H           0x14
 243 #define NETSEC_EEPROM_MH_ME_ADDRESS_L           0x18
 244 #define NETSEC_EEPROM_MH_ME_SIZE                0x1C
 245 #define NETSEC_EEPROM_PKT_ME_ADDRESS            0x20
 246 #define NETSEC_EEPROM_PKT_ME_SIZE               0x24
 247
 248 #define DESC_SZ sizeof(struct netsec_de)
 249
 250 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x)        ((x) & 0xffff0000)
 251
 252 #define EERPROM_MAP_OFFSET      0x8000000
 253 #define NOR_BLOCK       1024
 254
 255 struct netsec_de { /* Netsec Descriptor layout */
 256         u32 attr;
 257         u32 data_buf_addr_up;
 258         u32 data_buf_addr_lw;
 259         u32 buf_len_info;
 260 };
 261
 262 struct netsec_priv {
 263         struct netsec_de rxde[PKTBUFSRX];
 264         struct netsec_de txde[1];
 265         u16 rxat;
 266
 267         phys_addr_t eeprom_base;
 268         phys_addr_t ioaddr;
 269
 270         struct mii_dev *bus;
 271         struct phy_device *phydev;
 272         u32 phy_addr, freq;
 273         int phy_mode;
 274         int max_speed;
 275 };
 276
 277 struct netsec_tx_pkt_ctrl {
 278         u16 tcp_seg_len;
 279         bool tcp_seg_offload_flag;
 280         bool cksum_offload_flag;
 281 };
 282
 283 struct netsec_rx_pkt_info {
 284         int rx_cksum_result;
 285         int err_code;
 286         bool err_flag;
 287 };
 288
 289 static int netsec_reset_hardware(struct netsec_priv *priv, bool load_ucode);
 290
 291 static void netsec_write_reg(struct netsec_priv *priv, u32 reg_addr, u32 val)
 292 {
 293         writel(val, priv->ioaddr + reg_addr);
 294 }
 295
 296 static u32 netsec_read_reg(struct netsec_priv *priv, u32 reg_addr)
 297 {
 298         return readl(priv->ioaddr + reg_addr);
 299 }
 300
 301 /************* MDIO BUS OPS FOLLOW *************/
 302
 303 #define TIMEOUT_SPINS_MAC               1000
 304 #define TIMEOUT_SECONDARY_MS_MAC        100
 305
 306 static u32 netsec_clk_type(u32 freq)
 307 {
 308         if (freq < MHZ(35))
 309                 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
 310         if (freq < MHZ(60))
 311                 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
 312         if (freq < MHZ(100))
 313                 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
 314         if (freq < MHZ(150))
 315                 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
 316         if (freq < MHZ(250))
 317                 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
 318
 319         return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
 320 }
 321
 322 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
 323 {
 324         u32 timeout = TIMEOUT_SPINS_MAC;
 325
 326         while (--timeout && netsec_read_reg(priv, addr) & mask)
 327                 cpu_relax();
 328         if (timeout)
 329                 return 0;
 330
 331         timeout = TIMEOUT_SECONDARY_MS_MAC;
 332         while (--timeout && netsec_read_reg(priv, addr) & mask)
 333                 udelay(2000);
 334
 335         if (timeout)
 336                 return 0;
 337
 338         pr_err("%s: timeout\n", __func__);
 339
 340         return -ETIMEDOUT;
 341 }
 342
 343 static int netsec_set_mac_reg(struct netsec_priv *priv, u32 addr, u32 value)
 344 {
 345         netsec_write_reg(priv, MAC_REG_DATA, value);
 346         netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
 347         return netsec_wait_while_busy(priv,
 348                                       MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
 349 }
 350
 351 static int netsec_get_mac_reg(struct netsec_priv *priv, u32 addr, u32 *read)
 352 {
 353         int ret;
 354
 355         netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
 356         ret = netsec_wait_while_busy(priv,
 357                                      MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
 358         if (ret)
 359                 return ret;
 360
 361         *read = netsec_read_reg(priv, MAC_REG_DATA);
 362
 363         return 0;
 364 }
 365
 366 static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
 367                                       u32 addr, u32 mask)
 368 {
 369         u32 timeout = TIMEOUT_SPINS_MAC;
 370         u32 data;
 371         int ret;
 372
 373         do {
 374                 ret = netsec_get_mac_reg(priv, addr, &data);
 375                 if (ret)
 376                         break;
 377                 udelay(1);
 378         } while (--timeout && (data & mask));
 379
 380         if (timeout)
 381                 return 0;
 382
 383         timeout = TIMEOUT_SECONDARY_MS_MAC;
 384         do {
 385                 udelay(2000);
 386
 387                 ret = netsec_get_mac_reg(priv, addr, &data);
 388                 if (ret)
 389                         break;
 390                 cpu_relax();
 391         } while (--timeout && (data & mask));
 392
 393         if (timeout && !ret)
 394                 return 0;
 395
 396         return -ETIMEDOUT;
 397 }
 398
 399 static void netsec_cache_invalidate(uintptr_t vaddr, int len)
 400 {
 401         invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
 402                                 roundup(vaddr + len, ARCH_DMA_MINALIGN));
 403 }
 404
 405 static void netsec_cache_flush(uintptr_t vaddr, int len)
 406 {
 407         flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
 408                            roundup(vaddr + len, ARCH_DMA_MINALIGN));
 409 }
 410
 411 static void netsec_set_rx_de(struct netsec_priv *priv, u16 idx, void *addr)
 412 {
 413         struct netsec_de *de = &priv->rxde[idx];
 414         u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
 415                    (1 << NETSEC_RX_PKT_FS_FIELD) |
 416                    (1 << NETSEC_RX_PKT_LS_FIELD);
 417
 418         if (idx == PKTBUFSRX - 1)
 419                 attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
 420
 421         de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
 422         de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
 423         de->buf_len_info = PKTSIZE;
 424         de->attr = attr;
 425         dmb();
 426         netsec_cache_flush((uintptr_t)de, sizeof(*de));
 427 }
 428
 429 static void netsec_set_tx_de(struct netsec_priv *priv, void *addr, int len)
 430 {
 431         struct netsec_de *de = &priv->txde[0];
 432         u32 attr;
 433
 434         attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
 435                (1 << NETSEC_TX_SHIFT_PT_FIELD) |
 436                (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
 437                (1 << NETSEC_TX_SHIFT_FS_FIELD) |
 438                (1 << NETSEC_TX_LAST) |
 439                (1 << NETSEC_TX_SHIFT_TRS_FIELD) |
 440                         (1 << NETSEC_TX_SHIFT_LD_FIELD);
 441
 442         de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
 443         de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
 444         de->buf_len_info = len;
 445         de->attr = attr;
 446         dmb();
 447         netsec_cache_flush((uintptr_t)de, sizeof(*de));
 448 }
 449
 450 static int netsec_get_phy_reg(struct netsec_priv *priv,
 451                               int phy_addr, int reg_addr)
 452 {
 453         u32 data;
 454         int ret;
 455
 456         if (phy_addr != 7)
 457                 return -EINVAL;
 458
 459         if (netsec_set_mac_reg(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
 460                                phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
 461                                reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
 462                                (netsec_clk_type(priv->freq) <<
 463                                 GMAC_REG_SHIFT_CR_GAR)))
 464                 return -ETIMEDOUT;
 465
 466         ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
 467                                          NETSEC_GMAC_GAR_REG_GB);
 468         if (ret)
 469                 return ret;
 470
 471         ret = netsec_get_mac_reg(priv, GMAC_REG_GDR, &data);
 472         if (ret)
 473                 return ret;
 474
 475         return data;
 476 }
 477
 478 static int netsec_set_phy_reg(struct netsec_priv *priv,
 479                               int phy_addr, int reg_addr, u16 val)
 480 {
 481         int ret;
 482
 483         if (phy_addr != 7)
 484                 return -EINVAL;
 485         if (netsec_set_mac_reg(priv, GMAC_REG_GDR, val))
 486                 return -ETIMEDOUT;
 487
 488         if (netsec_set_mac_reg(priv, GMAC_REG_GAR,
 489                                phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
 490                                reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
 491                                NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
 492                                (netsec_clk_type(priv->freq) <<
 493                                 GMAC_REG_SHIFT_CR_GAR)))
 494                 return -ETIMEDOUT;
 495
 496         ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
 497                                          NETSEC_GMAC_GAR_REG_GB);
 498
 499         /* Developerbox implements RTL8211E PHY and there is
 500          * a compatibility problem with F_GMAC4.
 501          * RTL8211E expects MDC clock must be kept toggling for several
 502          * clock cycle with MDIO high before entering the IDLE state.
 503          * To meet this requirement, netsec driver needs to issue dummy
 504          * read(e.g. read PHYID1(offset 0x2) register) right after write.
 505          */
 506         netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1);
 507
 508         return ret;
 509 }
 510
 511 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
 512 {
 513         struct phy_device *phydev = priv->phydev;
 514         u32 value = 0;
 515
 516         value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
 517                                  NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
 518
 519         if (phydev->speed != SPEED_1000)
 520                 value |= NETSEC_MCR_PS;
 521
 522         if (phydev->interface != PHY_INTERFACE_MODE_GMII &&
 523             phydev->speed == SPEED_100)
 524                 value |= NETSEC_GMAC_MCR_REG_FES;
 525
 526         value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
 527
 528         if (phy_interface_is_rgmii(phydev))
 529                 value |= NETSEC_GMAC_MCR_REG_IBN;
 530
 531         if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
 532                 return -ETIMEDOUT;
 533
 534         return 0;
 535 }
 536
 537 static int netsec_reset_gmac(struct netsec_priv *priv)
 538 {
 539         u32 value = 0;
 540         int ret;
 541
 542         if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
 543                                NETSEC_GMAC_BMR_REG_RESET))
 544                 return -ETIMEDOUT;
 545
 546         /* Wait soft reset */
 547         mdelay(5);
 548
 549         ret = netsec_get_mac_reg(priv, GMAC_REG_BMR, &value);
 550         if (ret)
 551                 return ret;
 552
 553         if (value & NETSEC_GMAC_BMR_REG_SWR)
 554                 return -EAGAIN;
 555
 556         /**
 557          * NETSEC GMAC sometimes shows the peculiar behaviour where
 558          * MAC_REG_DESC_SOFT_RST never been cleared, resulting in the loss of
 559          * sending packets.
 560          *
 561          * Workaround:
 562          *   Restart NETSEC and PHY, retry again.
 563          */
 564         netsec_write_reg(priv, MAC_REG_DESC_SOFT_RST, 1);
 565         udelay(1000);
 566         if (netsec_read_reg(priv, MAC_REG_DESC_SOFT_RST)) {
 567                 phy_shutdown(priv->phydev);
 568                 netsec_reset_hardware(priv, false);
 569                 phy_startup(priv->phydev);
 570                 return -EAGAIN;
 571         }
 572         return 0;
 573 }
 574
 575 static int netsec_start_gmac(struct netsec_priv *priv)
 576 {
 577         u32 value = 0;
 578         u32 failure = 0;
 579         int ret;
 580
 581         if (priv->max_speed != SPEED_1000)
 582                 value = (NETSEC_GMAC_MCR_REG_CST |
 583                          NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
 584
 585         if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
 586                 return -ETIMEDOUT;
 587
 588         /* Reset GMAC */
 589         while ((ret = netsec_reset_gmac(priv)) == -EAGAIN && ++failure < 3)
 590                 ;
 591
 592         if (ret) {
 593                 pr_err("%s: failed to reset gmac(err=%d).\n", __func__, ret);
 594                 return ret;
 595         }
 596
 597         netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
 598         if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
 599                 return -ETIMEDOUT;
 600
 601         if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
 602                                NETSEC_GMAC_BMR_REG_COMMON))
 603                 return -ETIMEDOUT;
 604
 605         if (netsec_set_mac_reg(priv, GMAC_REG_RDLAR,
 606                                NETSEC_GMAC_RDLAR_REG_COMMON))
 607                 return -ETIMEDOUT;
 608
 609         if (netsec_set_mac_reg(priv, GMAC_REG_TDLAR,
 610                                NETSEC_GMAC_TDLAR_REG_COMMON))
 611                 return -ETIMEDOUT;
 612
 613         if (netsec_set_mac_reg(priv, GMAC_REG_MFFR, 0x80000001))
 614                 return -ETIMEDOUT;
 615
 616         ret = netsec_mac_update_to_phy_state(priv);
 617         if (ret)
 618                 return ret;
 619
 620         ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
 621         if (ret)
 622                 return ret;
 623
 624         value |= NETSEC_GMAC_OMR_REG_SR;
 625         value |= NETSEC_GMAC_OMR_REG_ST;
 626
 627         netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
 628         netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
 629
 630         if (netsec_set_mac_reg(priv, GMAC_REG_OMR, value))
 631                 return -ETIMEDOUT;
 632
 633         return 0;
 634 }
 635
 636 static int netsec_stop_gmac(struct netsec_priv *priv)
 637 {
 638         u32 value;
 639         int ret;
 640
 641         ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
 642         if (ret)
 643                 return ret;
 644         value &= ~NETSEC_GMAC_OMR_REG_SR;
 645         value &= ~NETSEC_GMAC_OMR_REG_ST;
 646
 647         /* disable all interrupts */
 648         netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
 649         netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
 650
 651         return netsec_set_mac_reg(priv, GMAC_REG_OMR, value);
 652 }
 653
 654 static void netsec_spi_read(char *buf, loff_t len, loff_t offset)
 655 {
 656         struct spi_flash *flash;
 657
 658         flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
 659                                 CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
 660
 661         spi_flash_read(flash, offset, len, buf);
 662 }
 663
 664 static int netsec_read_rom_hwaddr(struct udevice *dev)
 665 {
 666         struct netsec_priv *priv = dev_get_priv(dev);
 667         struct eth_pdata *pdata = dev_get_plat(dev);
 668         char macp[NOR_BLOCK];
 669
 670         netsec_spi_read(macp, sizeof(macp), priv->eeprom_base);
 671
 672         pdata->enetaddr[0] = readb(macp + 3);
 673         pdata->enetaddr[1] = readb(macp + 2);
 674         pdata->enetaddr[2] = readb(macp + 1);
 675         pdata->enetaddr[3] = readb(macp + 0);
 676         pdata->enetaddr[4] = readb(macp + 7);
 677         pdata->enetaddr[5] = readb(macp + 6);
 678         return 0;
 679 }
 680
 681 static int netsec_send(struct udevice *dev, void *packet, int length)
 682 {
 683         struct netsec_priv *priv = dev_get_priv(dev);
 684         u32 val, tout;
 685
 686         val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_STATUS);
 687         netsec_cache_flush((uintptr_t)packet, length);
 688         netsec_set_tx_de(priv, packet, length);
 689         netsec_write_reg(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
 690
 691         val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
 692
 693         tout = 10000;
 694         do {
 695                 val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
 696                 udelay(2);
 697         } while (--tout && !val);
 698
 699         if (!tout) {
 700                 val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
 701                 pr_err("%s: ETIMEDOUT:  %dpackets\n", __func__, val);
 702                 return -ETIMEDOUT;
 703         }
 704
 705         return 0;
 706 }
 707
 708 static int netsec_free_packet(struct udevice *dev, uchar *packet, int length)
 709 {
 710         struct netsec_priv *priv = dev_get_priv(dev);
 711
 712         netsec_set_rx_de(priv, priv->rxat, net_rx_packets[priv->rxat]);
 713
 714         priv->rxat++;
 715         if (priv->rxat == PKTBUFSRX)
 716                 priv->rxat = 0;
 717
 718         return 0;
 719 }
 720
 721 static int netsec_recv(struct udevice *dev, int flags, uchar **packetp)
 722 {
 723         struct netsec_priv *priv = dev_get_priv(dev);
 724         int idx = priv->rxat;
 725         uchar *ptr = net_rx_packets[idx];
 726         struct netsec_de *de = &priv->rxde[idx];
 727         int length = 0;
 728
 729         netsec_cache_invalidate((uintptr_t)de, sizeof(*de));
 730
 731         if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD))
 732                 return -EAGAIN;
 733
 734         length = de->buf_len_info >> 16;
 735
 736         /* invalidate after DMA is done */
 737         netsec_cache_invalidate((uintptr_t)ptr, length);
 738         *packetp = ptr;
 739
 740         return length;
 741 }
 742
 743 static int _netsec_get_phy_reg(struct mii_dev *bus,
 744                                int phy_addr, int devad, int reg_addr)
 745 {
 746         return netsec_get_phy_reg(bus->priv, phy_addr, reg_addr);
 747 }
 748
 749 static int _netsec_set_phy_reg(struct mii_dev *bus,
 750                                int phy_addr, int devad, int reg_addr, u16 val)
 751 {
 752         return netsec_set_phy_reg(bus->priv, phy_addr, reg_addr, val);
 753 }
 754
 755 static int netsec_mdiobus_init(struct netsec_priv *priv, const char *name)
 756 {
 757         struct mii_dev *bus = mdio_alloc();
 758
 759         if (!bus)
 760                 return -ENOMEM;
 761
 762         bus->read = _netsec_get_phy_reg;
 763         bus->write = _netsec_set_phy_reg;
 764         snprintf(bus->name, sizeof(bus->name), "%s", name);
 765         bus->priv = priv;
 766
 767         return mdio_register(bus);
 768 }
 769
 770 static int netsec_phy_init(struct netsec_priv *priv, void *dev)
 771 {
 772         struct phy_device *phydev;
 773         int ret;
 774
 775         phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
 776
 777         phydev->supported &= PHY_GBIT_FEATURES;
 778         if (priv->max_speed) {
 779                 ret = phy_set_supported(phydev, priv->max_speed);
 780                 if (ret)
 781                         return ret;
 782         }
 783         phydev->advertising = phydev->supported;
 784
 785         priv->phydev = phydev;
 786         phy_config(phydev);
 787
 788         return 0;
 789 }
 790
 791 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
 792                                            u32 addr_h, u32 addr_l, u32 size)
 793 {
 794         u64 base = ((u64)addr_h << 32 | addr_l) - EERPROM_MAP_OFFSET;
 795
 796         while (size > 0) {
 797                 char buf[NOR_BLOCK];
 798                 u32 *ucode = (u32 *)buf;
 799                 u64 off;
 800                 int i;
 801
 802                 off = base % NOR_BLOCK;
 803                 base -= off;
 804                 netsec_spi_read(buf, sizeof(buf), base);
 805
 806                 for (i = off / 4; i < sizeof(buf) / 4 && size > 0; i++, size--)
 807                         netsec_write_reg(priv, reg, ucode[i]);
 808                 base += NOR_BLOCK;
 809         }
 810
 811         return 0;
 812 }
 813
 814 static int netsec_netdev_load_microcode(struct netsec_priv *priv)
 815 {
 816         u32 addr_h, addr_l, size;
 817         char buf[NOR_BLOCK];
 818         u32 *ucinfo = (u32 *)buf;
 819         int err;
 820
 821         netsec_spi_read(buf, sizeof(buf), priv->eeprom_base);
 822
 823         addr_h = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_H >> 2];
 824         addr_l = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_L >> 2];
 825         size = ucinfo[NETSEC_EEPROM_HM_ME_SIZE >> 2];
 826
 827         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
 828                                               addr_h, addr_l, size);
 829         if (err)
 830                 return err;
 831
 832         addr_h = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_H >> 2];
 833         addr_l = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_L >> 2];
 834         size = ucinfo[NETSEC_EEPROM_MH_ME_SIZE >> 2];
 835
 836         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
 837                                               addr_h, addr_l, size);
 838         if (err)
 839                 return err;
 840
 841         addr_h = 0;
 842         addr_l = ucinfo[NETSEC_EEPROM_PKT_ME_ADDRESS >> 2];
 843         size = ucinfo[NETSEC_EEPROM_PKT_ME_SIZE >> 2];
 844
 845         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
 846                                               addr_h, addr_l, size);
 847         if (err)
 848                 return err;
 849
 850         return 0;
 851 }
 852
 853 void netsec_pre_init_microengine(struct netsec_priv *priv)
 854 {
 855         u32 data;
 856
 857         /* Remove dormant settings */
 858         data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
 859         data &= ~BMCR_PDOWN;
 860         data |= BMCR_ISOLATE;
 861         netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
 862         mdelay(100);
 863
 864         /* Put phy in loopback mode to guarantee RXCLK input */
 865         data |= BMCR_LOOPBACK;
 866         netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
 867         mdelay(100);
 868 }
 869
 870 void netsec_post_init_microengine(struct netsec_priv *priv)
 871 {
 872         u32 data;
 873
 874         /* Get phy back to normal operation */
 875         data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
 876         data &= ~BMCR_LOOPBACK;
 877         netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
 878         mdelay(100);
 879
 880         /* Apply software reset */
 881         data |= BMCR_RESET;
 882         netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
 883         mdelay(100);
 884 }
 885
 886 static int netsec_reset_hardware(struct netsec_priv *priv, bool load_ucode)
 887 {
 888         u32 value;
 889         int err;
 890
 891         netsec_write_reg(priv, NETSEC_REG_CLK_EN, 0x24);
 892
 893         /* stop DMA engines */
 894         if (!netsec_read_reg(priv, NETSEC_REG_ADDR_DIS_CORE)) {
 895                 netsec_write_reg(priv, NETSEC_REG_DMA_HM_CTRL,
 896                                  NETSEC_DMA_CTRL_REG_STOP);
 897                 netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL,
 898                                  NETSEC_DMA_CTRL_REG_STOP);
 899
 900                 value = 100;
 901                 while (netsec_read_reg(priv, NETSEC_REG_DMA_HM_CTRL) &
 902                        NETSEC_DMA_CTRL_REG_STOP) {
 903                         udelay(1000);
 904                         if (--value == 0) {
 905                                 pr_err("%s:%d timeout!\n", __func__, __LINE__);
 906                                 break;
 907                         }
 908                 }
 909
 910                 value = 100;
 911                 while (netsec_read_reg(priv, NETSEC_REG_DMA_MH_CTRL) &
 912                        NETSEC_DMA_CTRL_REG_STOP) {
 913                         udelay(1000);
 914                         if (--value == 0) {
 915                                 pr_err("%s:%d timeout!\n", __func__, __LINE__);
 916                                 break;
 917                         }
 918                 }
 919         }
 920
 921         netsec_set_mac_reg(priv, GMAC_REG_BMR, NETSEC_GMAC_BMR_REG_RESET);
 922
 923         netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
 924         netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
 925         netsec_write_reg(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
 926
 927         value = 100;
 928         while (netsec_read_reg(priv, NETSEC_REG_COM_INIT) != 0) {
 929                 udelay(1000);
 930                 if (--value == 0) {
 931                         pr_err("%s:%d COM_INIT timeout!\n", __func__, __LINE__);
 932                         break;
 933                 }
 934         }
 935
 936         /* MAC desc init */
 937         netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
 938         netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1);
 939         /* set MAC_INTF_SEL */
 940         netsec_write_reg(priv, MAC_REG_INTF_SEL, 1);
 941
 942         netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
 943
 944         /* set desc_start addr */
 945         netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
 946                          upper_32_bits((dma_addr_t)priv->rxde));
 947         netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
 948                          lower_32_bits((dma_addr_t)priv->rxde));
 949
 950         netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
 951                          upper_32_bits((dma_addr_t)priv->txde));
 952         netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
 953                          lower_32_bits((dma_addr_t)priv->txde));
 954
 955         /* set normal tx dring ring config */
 956         netsec_write_reg(priv, NETSEC_REG_NRM_TX_CONFIG,
 957                          1 << NETSEC_REG_DESC_ENDIAN);
 958         netsec_write_reg(priv, NETSEC_REG_NRM_RX_CONFIG,
 959                          1 << NETSEC_REG_DESC_ENDIAN);
 960
 961         if (load_ucode) {
 962                 err = netsec_netdev_load_microcode(priv);
 963                 if (err) {
 964                         pr_err("%s: failed to load microcode (%d)\n",
 965                                __func__, err);
 966                         return err;
 967                 }
 968         }
 969
 970         /* set desc_start addr */
 971         netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
 972                          upper_32_bits((dma_addr_t)priv->rxde));
 973         netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
 974                          lower_32_bits((dma_addr_t)priv->rxde));
 975
 976         netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
 977                          upper_32_bits((dma_addr_t)priv->txde));
 978         netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
 979                          lower_32_bits((dma_addr_t)priv->txde));
 980
 981         netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
 982
 983         /* start DMA engines */
 984         netsec_write_reg(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
 985
 986         netsec_pre_init_microengine(priv);
 987
 988         netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
 989
 990         mdelay(100);
 991
 992         if (!(netsec_read_reg(priv, NETSEC_REG_TOP_STATUS) &
 993               NETSEC_TOP_IRQ_REG_ME_START)) {
 994                 pr_err("microengine start failed\n");
 995                 return -ENXIO;
 996         }
 997
 998         netsec_post_init_microengine(priv);
 999
1000         /* clear microcode load end status */
1001         netsec_write_reg(priv, NETSEC_REG_TOP_STATUS,
1002                          NETSEC_TOP_IRQ_REG_ME_START);
1003
1004         netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
1005
1006         value = netsec_read_reg(priv, NETSEC_REG_PKT_CTRL);
1007         value |= NETSEC_PKT_CTRL_REG_MODE_NRM;
1008         /* change to normal mode */
1009         netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
1010         netsec_write_reg(priv, NETSEC_REG_PKT_CTRL, value);
1011
1012         value = 100;
1013         while ((netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
1014                 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) {
1015                 udelay(1000);
1016                 if (--value == 0) {
1017                         value = netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS);
1018                         pr_err("%s:%d timeout! val=%x\n", __func__, __LINE__, value);
1019                         break;
1020                 }
1021         }
1022
1023         /* clear any pending EMPTY/ERR irq status */
1024         netsec_write_reg(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
1025
1026         /* Disable TX & RX intr */
1027         netsec_write_reg(priv, NETSEC_REG_INTEN_CLR, ~0);
1028
1029         return 0;
1030 }
1031
1032 static void netsec_stop(struct udevice *dev)
1033 {
1034         struct netsec_priv *priv = dev_get_priv(dev);
1035
1036         netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 7);
1037         netsec_stop_gmac(priv);
1038         phy_shutdown(priv->phydev);
1039         netsec_reset_hardware(priv, false);
1040 }
1041
1042 static int netsec_start(struct udevice *dev)
1043 {
1044         struct netsec_priv *priv = dev_get_priv(dev);
1045         int i;
1046
1047         phy_startup(priv->phydev);
1048         netsec_start_gmac(priv);
1049
1050         priv->rxat = 0;
1051         for (i = 0; i < PKTBUFSRX; i++)
1052                 netsec_set_rx_de(priv, i, net_rx_packets[i]);
1053
1054         return 0;
1055 }
1056
1057 static int netsec_of_to_plat(struct udevice *dev)
1058 {
1059         struct eth_pdata *pdata = dev_get_plat(dev);
1060         struct netsec_priv *priv = dev_get_priv(dev);
1061         struct ofnode_phandle_args phandle_args;
1062
1063         pdata->iobase = dev_read_addr_index(dev, 0);
1064         priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
1065
1066         pdata->phy_interface = dev_read_phy_mode(dev);
1067         if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
1068                 return -EINVAL;
1069
1070         if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1071                                         &phandle_args))
1072                 priv->phy_addr = ofnode_read_u32_default(phandle_args.node, "reg", 7);
1073         else
1074                 priv->phy_addr = 7;
1075
1076         pdata->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
1077
1078         priv->ioaddr = pdata->iobase;
1079         priv->phy_mode = pdata->phy_interface;
1080         priv->max_speed = pdata->max_speed;
1081         priv->freq = 250000000UL;
1082
1083         return 0;
1084 }
1085
1086 static int netsec_probe(struct udevice *dev)
1087 {
1088         struct netsec_priv *priv = dev_get_priv(dev);
1089         int ret;
1090
1091         netsec_reset_hardware(priv, true);
1092
1093         ret = netsec_mdiobus_init(priv, dev->name);
1094         if (ret) {
1095                 pr_err("Failed to initialize mdiobus: %d\n", ret);
1096                 return ret;
1097         }
1098
1099         priv->bus = miiphy_get_dev_by_name(dev->name);
1100
1101         ret = netsec_phy_init(priv, dev);
1102         if (ret) {
1103                 pr_err("Failed to initialize phy: %d\n", ret);
1104                 goto out_mdiobus_release;
1105         }
1106
1107         return 0;
1108 out_mdiobus_release:
1109         mdio_unregister(priv->bus);
1110         mdio_free(priv->bus);
1111         return ret;
1112 }
1113
1114 static int netsec_remove(struct udevice *dev)
1115 {
1116         struct netsec_priv *priv = dev_get_priv(dev);
1117
1118         free(priv->phydev);
1119         mdio_unregister(priv->bus);
1120         mdio_free(priv->bus);
1121
1122         return 0;
1123 }
1124
1125 static const struct eth_ops netsec_ops = {
1126         .start        = netsec_start,
1127         .stop         = netsec_stop,
1128         .send         = netsec_send,
1129         .recv         = netsec_recv,
1130         .free_pkt     = netsec_free_packet,
1131         .read_rom_hwaddr = netsec_read_rom_hwaddr,
1132 };
1133
1134 static const struct udevice_id netsec_ids[] = {
1135         {
1136                 .compatible = "socionext,synquacer-netsec",
1137         },
1138         {}
1139 };
1140
1141 U_BOOT_DRIVER(ave) = {
1142         .name     = "synquacer_netsec",
1143         .id       = UCLASS_ETH,
1144         .of_match = netsec_ids,
1145         .probe    = netsec_probe,
1146         .remove   = netsec_remove,
1147         .of_to_plat = netsec_of_to_plat,
1148         .ops      = &netsec_ops,
1149         .priv_auto      = sizeof(struct netsec_priv),
1150         .plat_auto      = sizeof(struct eth_pdata),
1151 };