1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the WB45N CPU Module.
9 #include <asm/hardware.h>
10 #include <linux/stringify.h>
12 /* ARM asynchronous clock */
13 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
14 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
16 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
17 #define CONFIG_SETUP_MEMORY_TAGS
18 #define CONFIG_INITRD_TAG
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 /* general purpose I/O */
22 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
25 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
26 #define CONFIG_USART_ID ATMEL_ID_SYS
31 #define CONFIG_BOOTP_BOOTFILESIZE
34 #define CONFIG_SYS_SDRAM_BASE 0x20000000
35 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */
37 #define CONFIG_SYS_INIT_SP_ADDR \
38 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
41 #define CONFIG_SYS_MAX_NAND_DEVICE 1
42 #define CONFIG_SYS_NAND_BASE 0x40000000
44 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
46 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
47 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
48 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
55 #define CONFIG_NET_RETRY_COUNT 20
56 #define CONFIG_MACB_SEARCH_PHY
57 #define CONFIG_ETHADDR C0:EE:40:00:00:00
58 #define CONFIG_ENV_OVERWRITE 1
61 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
63 #ifdef CONFIG_SYS_USE_NANDFLASH
64 /* bootstrap + u-boot + env + linux in nandflash */
66 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \
69 #define MTDIDS_DEFAULT "nand0=atmel_nand"
70 #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \
83 #error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH'
86 #define CONFIG_EXTRA_ENV_SETTINGS \
87 "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \
90 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
93 #define CONFIG_SYS_CBSIZE 256
94 #define CONFIG_SYS_MAXARGS 16
97 * Size of malloc() pool
99 #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
102 #define CONFIG_SPL_MAX_SIZE 0x6000
103 #define CONFIG_SPL_STACK 0x308000
105 #define CONFIG_SPL_BSS_START_ADDR 0x20000000
106 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
107 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
108 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
110 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
112 #define CONFIG_SYS_MASTER_CLOCK 132096000
113 #define CONFIG_SYS_AT91_PLLA 0x20c73f03
114 #define CONFIG_SYS_MCKR 0x1301
115 #define CONFIG_SYS_MCKR_CSS 0x1302
117 #define CONFIG_SPL_NAND_DRIVERS
118 #define CONFIG_SPL_NAND_BASE
119 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
120 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
121 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
122 #define CONFIG_SYS_NAND_PAGE_COUNT 64
123 #define CONFIG_SYS_NAND_OOBSIZE 64
124 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
125 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
127 #endif /* __CONFIG_H__ */