drivers/spi/spi-aspeed-smc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * ASPEED FMC/SPI Controller driver
   4  *
   5  * Copyright (c) 2022 ASPEED Corporation.
   6  * Copyright (c) 2022 IBM Corporation.
   7  *
   8  * Author:
   9  *     Chin-Ting Kuo <[email protected]>
  10  *     Cedric Le Goater <[email protected]>
  11  */
  12
  13 #include <asm/io.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/bitops.h>
  18 #include <linux/bug.h>
  19 #include <linux/err.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mtd/spi-nor.h>
  23 #include <linux/sizes.h>
  24 #include <malloc.h>
  25 #include <spi.h>
  26 #include <spi-mem.h>
  27
  28 #define ASPEED_SPI_MAX_CS       5
  29
  30 #define CTRL_IO_SINGLE_DATA     0
  31 #define CTRL_IO_QUAD_DATA       BIT(30)
  32 #define CTRL_IO_DUAL_DATA       BIT(29)
  33
  34 #define CTRL_IO_MODE_USER       GENMASK(1, 0)
  35 #define CTRL_IO_MODE_CMD_READ   BIT(0)
  36 #define CTRL_IO_MODE_CMD_WRITE  BIT(1)
  37 #define CTRL_STOP_ACTIVE        BIT(2)
  38
  39 struct aspeed_spi_regs {
  40         u32 conf;                       /* 0x00 CE Type Setting */
  41         u32 ctrl;                       /* 0x04 CE Control */
  42         u32 intr_ctrl;                  /* 0x08 Interrupt Control and Status */
  43         u32 cmd_ctrl;                   /* 0x0c Command Control */
  44         u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x20 CEx Control */
  45         u32 _reserved0[3];              /* .. */
  46         u32 segment_addr[ASPEED_SPI_MAX_CS]; /* 0x30 .. 0x40 Segment Address */
  47         u32 _reserved1[3];              /* .. */
  48         u32 soft_rst_cmd_ctrl;          /* 0x50 Auto Soft-Reset Command Control */
  49         u32 _reserved2[11];             /* .. */
  50         u32 dma_ctrl;                   /* 0x80 DMA Control/Status */
  51         u32 dma_flash_addr;             /* 0x84 DMA Flash Side Address */
  52         u32 dma_dram_addr;              /* 0x88 DMA DRAM Side Address */
  53         u32 dma_len;                    /* 0x8c DMA Length Register */
  54         u32 dma_checksum;               /* 0x90 Checksum Calculation Result */
  55         u32 timings[ASPEED_SPI_MAX_CS]; /* 0x94 Read Timing Compensation */
  56 };
  57
  58 struct aspeed_spi_plat {
  59         u8 max_cs;
  60         void __iomem *ahb_base; /* AHB address base for all flash devices. */
  61         fdt_size_t ahb_sz; /* Overall AHB window size for all flash device. */
  62         u32 hclk_rate; /* AHB clock rate */
  63 };
  64
  65 struct aspeed_spi_flash {
  66         void __iomem *ahb_base;
  67         u32 ahb_decoded_sz;
  68         u32 ce_ctrl_user;
  69         u32 ce_ctrl_read;
  70         u32 max_freq;
  71 };
  72
  73 struct aspeed_spi_priv {
  74         u32 num_cs;
  75         struct aspeed_spi_regs *regs;
  76         struct aspeed_spi_info *info;
  77         struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS];
  78         bool fixed_decoded_range;
  79 };
  80
  81 struct aspeed_spi_info {
  82         u32 io_mode_mask;
  83         u32 max_bus_width;
  84         u32 min_decoded_sz;
  85         u32 clk_ctrl_mask;
  86         void (*set_4byte)(struct udevice *bus, u32 cs);
  87         u32 (*segment_start)(struct udevice *bus, u32 reg);
  88         u32 (*segment_end)(struct udevice *bus, u32 reg);
  89         u32 (*segment_reg)(u32 start, u32 end);
  90         int (*adjust_decoded_sz)(struct udevice *bus);
  91         u32 (*get_clk_setting)(struct udevice *dev, uint hz);
  92 };
  93
  94 struct aspeed_spi_decoded_range {
  95         u32 cs;
  96         u32 ahb_base;
  97         u32 sz;
  98 };
  99
 100 static const struct aspeed_spi_info ast2400_spi_info;
 101 static const struct aspeed_spi_info ast2500_fmc_info;
 102 static const struct aspeed_spi_info ast2500_spi_info;
 103 static int aspeed_spi_decoded_range_config(struct udevice *bus);
 104 static int aspeed_spi_trim_decoded_size(struct udevice *bus);
 105
 106 static u32 aspeed_spi_get_io_mode(u32 bus_width)
 107 {
 108         switch (bus_width) {
 109         case 1:
 110                 return CTRL_IO_SINGLE_DATA;
 111         case 2:
 112                 return CTRL_IO_DUAL_DATA;
 113         case 4:
 114                 return CTRL_IO_QUAD_DATA;
 115         default:
 116                 /* keep in default value */
 117                 return CTRL_IO_SINGLE_DATA;
 118         }
 119 }
 120
 121 static u32 ast2400_spi_segment_start(struct udevice *bus, u32 reg)
 122 {
 123         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 124         u32 start_offset = ((reg >> 16) & 0xff) << 23;
 125
 126         if (start_offset == 0)
 127                 return (u32)plat->ahb_base;
 128
 129         return (u32)plat->ahb_base + start_offset;
 130 }
 131
 132 static u32 ast2400_spi_segment_end(struct udevice *bus, u32 reg)
 133 {
 134         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 135         u32 end_offset = ((reg >> 24) & 0xff) << 23;
 136
 137         /* Meaningless end_offset, set to physical ahb base. */
 138         if (end_offset == 0)
 139                 return (u32)plat->ahb_base;
 140
 141         return (u32)plat->ahb_base + end_offset;
 142 }
 143
 144 static u32 ast2400_spi_segment_reg(u32 start, u32 end)
 145 {
 146         if (start == end)
 147                 return 0;
 148
 149         return ((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24);
 150 }
 151
 152 static void ast2400_fmc_chip_set_4byte(struct udevice *bus, u32 cs)
 153 {
 154         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 155         u32 reg_val;
 156
 157         reg_val = readl(&priv->regs->ctrl);
 158         reg_val |= 0x1 << cs;
 159         writel(reg_val, &priv->regs->ctrl);
 160 }
 161
 162 static void ast2400_spi_chip_set_4byte(struct udevice *bus, u32 cs)
 163 {
 164         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 165         struct aspeed_spi_flash *flash = &priv->flashes[cs];
 166
 167         flash->ce_ctrl_read |= BIT(13);
 168         writel(flash->ce_ctrl_read, &priv->regs->ctrl);
 169 }
 170
 171 /* Transfer maximum clock frequency to register setting */
 172 static u32 ast2400_get_clk_setting(struct udevice *dev, uint max_hz)
 173 {
 174         struct aspeed_spi_plat *plat = dev_get_plat(dev->parent);
 175         struct aspeed_spi_priv *priv = dev_get_priv(dev->parent);
 176         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 177         u32 hclk_clk = plat->hclk_rate;
 178         u32 hclk_div = 0x0000; /* default value */
 179         u32 i;
 180         bool found = false;
 181         /* HCLK/1 ..    HCLK/16 */
 182         u32 hclk_masks[] = {15, 7, 14, 6, 13, 5, 12, 4,
 183                             11, 3, 10, 2, 9,  1, 8,  0};
 184
 185         /* FMC/SPIR10[11:8] */
 186         for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) {
 187                 if (hclk_clk / (i + 1) <= max_hz) {
 188                         found = true;
 189                         break;
 190                 }
 191         }
 192
 193         if (found) {
 194                 hclk_div = hclk_masks[i] << 8;
 195                 priv->flashes[slave_plat->cs[0]].max_freq = hclk_clk / (i + 1);
 196         }
 197
 198         dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", found ? "yes" : "no",
 199                 hclk_clk, max_hz);
 200
 201         if (found) {
 202                 dev_dbg(dev, "h_div: %d (mask %x), speed: %d\n",
 203                         i + 1, hclk_masks[i], priv->flashes[slave_plat->cs[0]].max_freq);
 204         }
 205
 206         return hclk_div;
 207 }
 208
 209 static u32 ast2500_spi_segment_start(struct udevice *bus, u32 reg)
 210 {
 211         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 212         u32 start_offset = ((reg >> 16) & 0xff) << 23;
 213
 214         if (start_offset == 0)
 215                 return (u32)plat->ahb_base;
 216
 217         return (u32)plat->ahb_base + start_offset;
 218 }
 219
 220 static u32 ast2500_spi_segment_end(struct udevice *bus, u32 reg)
 221 {
 222         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 223         u32 end_offset = ((reg >> 24) & 0xff) << 23;
 224
 225         /* Meaningless end_offset, set to physical ahb base. */
 226         if (end_offset == 0)
 227                 return (u32)plat->ahb_base;
 228
 229         return (u32)plat->ahb_base + end_offset;
 230 }
 231
 232 static u32 ast2500_spi_segment_reg(u32 start, u32 end)
 233 {
 234         if (start == end)
 235                 return 0;
 236
 237         return ((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24);
 238 }
 239
 240 static void ast2500_spi_chip_set_4byte(struct udevice *bus, u32 cs)
 241 {
 242         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 243         u32 reg_val;
 244
 245         reg_val = readl(&priv->regs->ctrl);
 246         reg_val |= 0x1 << cs;
 247         writel(reg_val, &priv->regs->ctrl);
 248 }
 249
 250 /*
 251  * For AST2500, the minimum address decoded size for each CS
 252  * is 8MB instead of zero. This address decoded size is
 253  * mandatory for each CS no matter whether it will be used.
 254  * This is a HW limitation.
 255  */
 256 static int ast2500_adjust_decoded_size(struct udevice *bus)
 257 {
 258         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 259         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 260         struct aspeed_spi_flash *flashes = &priv->flashes[0];
 261         int ret;
 262         int i;
 263         int cs;
 264         u32 pre_sz;
 265         u32 lack_sz;
 266
 267         /* Assign min_decoded_sz to unused CS. */
 268         for (cs = priv->num_cs; cs < plat->max_cs; cs++)
 269                 flashes[cs].ahb_decoded_sz = priv->info->min_decoded_sz;
 270
 271         /*
 272          * If command mode or normal mode is used, the start address of a
 273          * decoded range should be multiple of its related flash size.
 274          * Namely, the total decoded size from flash 0 to flash N should
 275          * be multiple of the size of flash (N + 1).
 276          */
 277         for (cs = priv->num_cs - 1; cs >= 0; cs--) {
 278                 pre_sz = 0;
 279                 for (i = 0; i < cs; i++)
 280                         pre_sz += flashes[i].ahb_decoded_sz;
 281
 282                 if (flashes[cs].ahb_decoded_sz != 0 &&
 283                     (pre_sz % flashes[cs].ahb_decoded_sz) != 0) {
 284                         lack_sz = flashes[cs].ahb_decoded_sz -
 285                                   (pre_sz % flashes[cs].ahb_decoded_sz);
 286                         flashes[0].ahb_decoded_sz += lack_sz;
 287                 }
 288         }
 289
 290         ret = aspeed_spi_trim_decoded_size(bus);
 291         if (ret != 0)
 292                 return ret;
 293
 294         return 0;
 295 }
 296
 297 static u32 ast2500_get_clk_setting(struct udevice *dev, uint max_hz)
 298 {
 299         struct aspeed_spi_plat *plat = dev_get_plat(dev->parent);
 300         struct aspeed_spi_priv *priv = dev_get_priv(dev->parent);
 301         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 302         u32 hclk_clk = plat->hclk_rate;
 303         u32 hclk_div = 0x0000; /* default value */
 304         u32 i;
 305         bool found = false;
 306         /* HCLK/1 ..    HCLK/16 */
 307         u32 hclk_masks[] = {15, 7, 14, 6, 13, 5, 12, 4,
 308                             11, 3, 10, 2, 9,  1, 8,  0};
 309
 310         /* FMC/SPIR10[11:8] */
 311         for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) {
 312                 if (hclk_clk / (i + 1) <= max_hz) {
 313                         found = true;
 314                         priv->flashes[slave_plat->cs[0]].max_freq =
 315                                                         hclk_clk / (i + 1);
 316                         break;
 317                 }
 318         }
 319
 320         if (found) {
 321                 hclk_div = hclk_masks[i] << 8;
 322                 goto end;
 323         }
 324
 325         for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) {
 326                 if (hclk_clk / ((i + 1) * 4) <= max_hz) {
 327                         found = true;
 328                         priv->flashes[slave_plat->cs[0]].max_freq =
 329                                                 hclk_clk / ((i + 1) * 4);
 330                         break;
 331                 }
 332         }
 333
 334         if (found)
 335                 hclk_div = BIT(13) | (hclk_masks[i] << 8);
 336
 337 end:
 338         dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", found ? "yes" : "no",
 339                 hclk_clk, max_hz);
 340
 341         if (found) {
 342                 dev_dbg(dev, "h_div: %d (mask %x), speed: %d\n",
 343                         i + 1, hclk_masks[i], priv->flashes[slave_plat->cs[0]].max_freq);
 344         }
 345
 346         return hclk_div;
 347 }
 348
 349 static u32 ast2600_spi_segment_start(struct udevice *bus, u32 reg)
 350 {
 351         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 352         u32 start_offset = (reg << 16) & 0x0ff00000;
 353
 354         if (start_offset == 0)
 355                 return (u32)plat->ahb_base;
 356
 357         return (u32)plat->ahb_base + start_offset;
 358 }
 359
 360 static u32 ast2600_spi_segment_end(struct udevice *bus, u32 reg)
 361 {
 362         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 363         u32 end_offset = reg & 0x0ff00000;
 364
 365         /* Meaningless end_offset, set to physical ahb base. */
 366         if (end_offset == 0)
 367                 return (u32)plat->ahb_base;
 368
 369         return (u32)plat->ahb_base + end_offset + 0x100000;
 370 }
 371
 372 static u32 ast2600_spi_segment_reg(u32 start, u32 end)
 373 {
 374         if (start == end)
 375                 return 0;
 376
 377         return ((start & 0x0ff00000) >> 16) | ((end - 0x100000) & 0x0ff00000);
 378 }
 379
 380 static void ast2600_spi_chip_set_4byte(struct udevice *bus, u32 cs)
 381 {
 382         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 383         u32 reg_val;
 384
 385         reg_val = readl(&priv->regs->ctrl);
 386         reg_val |= 0x11 << cs;
 387         writel(reg_val, &priv->regs->ctrl);
 388 }
 389
 390 static int ast2600_adjust_decoded_size(struct udevice *bus)
 391 {
 392         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 393         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 394         struct aspeed_spi_flash *flashes = &priv->flashes[0];
 395         int ret;
 396         int i;
 397         int cs;
 398         u32 pre_sz;
 399         u32 lack_sz;
 400
 401         /* Close unused CS. */
 402         for (cs = priv->num_cs; cs < plat->max_cs; cs++)
 403                 flashes[cs].ahb_decoded_sz = 0;
 404
 405         /*
 406          * If command mode or normal mode is used, the start address of a
 407          * decoded range should be multiple of its related flash size.
 408          * Namely, the total decoded size from flash 0 to flash N should
 409          * be multiple of the size of flash (N + 1).
 410          */
 411         for (cs = priv->num_cs - 1; cs >= 0; cs--) {
 412                 pre_sz = 0;
 413                 for (i = 0; i < cs; i++)
 414                         pre_sz += flashes[i].ahb_decoded_sz;
 415
 416                 if (flashes[cs].ahb_decoded_sz != 0 &&
 417                     (pre_sz % flashes[cs].ahb_decoded_sz) != 0) {
 418                         lack_sz = flashes[cs].ahb_decoded_sz -
 419                                   (pre_sz % flashes[cs].ahb_decoded_sz);
 420                         flashes[0].ahb_decoded_sz += lack_sz;
 421                 }
 422         }
 423
 424         ret = aspeed_spi_trim_decoded_size(bus);
 425         if (ret != 0)
 426                 return ret;
 427
 428         return 0;
 429 }
 430
 431 static u32 ast2600_get_clk_setting(struct udevice *dev, uint max_hz)
 432 {
 433         struct aspeed_spi_plat *plat = dev_get_plat(dev->parent);
 434         struct aspeed_spi_priv *priv = dev_get_priv(dev->parent);
 435         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 436         u32 hclk_clk = plat->hclk_rate;
 437         u32 hclk_div = 0x0400; /* default value */
 438         u32 i, j;
 439         bool found = false;
 440         /* HCLK/1 ..    HCLK/16 */
 441         u32 hclk_masks[] = {15, 7, 14, 6, 13, 5, 12, 4,
 442                             11, 3, 10, 2, 9,  1, 8,  0};
 443
 444         /* FMC/SPIR10[27:24] */
 445         for (j = 0; j < 0xf; j++) {
 446                 /* FMC/SPIR10[11:8] */
 447                 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) {
 448                         if (i == 0 && j == 0)
 449                                 continue;
 450
 451                         if (hclk_clk / (i + 1 + (j * 16)) <= max_hz) {
 452                                 found = true;
 453                                 break;
 454                         }
 455                 }
 456
 457                 if (found) {
 458                         hclk_div = ((j << 24) | hclk_masks[i] << 8);
 459                         priv->flashes[slave_plat->cs[0]].max_freq =
 460                                                 hclk_clk / (i + 1 + j * 16);
 461                         break;
 462                 }
 463         }
 464
 465         dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", found ? "yes" : "no",
 466                 hclk_clk, max_hz);
 467
 468         if (found) {
 469                 dev_dbg(dev, "base_clk: %d, h_div: %d (mask %x), speed: %d\n",
 470                         j, i + 1, hclk_masks[i], priv->flashes[slave_plat->cs[0]].max_freq);
 471         }
 472
 473         return hclk_div;
 474 }
 475
 476 /*
 477  * As the flash size grows up, we need to trim some decoded
 478  * size if needed for the sake of conforming the maximum
 479  * decoded size. We trim the decoded size from the largest
 480  * CS in order to avoid affecting the default boot up sequence
 481  * from CS0 where command mode or normal mode is used.
 482  * Notice, if a CS decoded size is trimmed, command mode may
 483  * not work perfectly on that CS.
 484  */
 485 static int aspeed_spi_trim_decoded_size(struct udevice *bus)
 486 {
 487         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 488         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 489         struct aspeed_spi_flash *flashes = &priv->flashes[0];
 490         u32 total_sz;
 491         int cs = plat->max_cs - 1;
 492         u32 i;
 493
 494         do {
 495                 total_sz = 0;
 496                 for (i = 0; i < plat->max_cs; i++)
 497                         total_sz += flashes[i].ahb_decoded_sz;
 498
 499                 if (flashes[cs].ahb_decoded_sz <= priv->info->min_decoded_sz)
 500                         cs--;
 501
 502                 if (cs < 0)
 503                         return -ENOMEM;
 504
 505                 if (total_sz > plat->ahb_sz) {
 506                         flashes[cs].ahb_decoded_sz -=
 507                                         priv->info->min_decoded_sz;
 508                         total_sz -= priv->info->min_decoded_sz;
 509                 }
 510         } while (total_sz > plat->ahb_sz);
 511
 512         return 0;
 513 }
 514
 515 static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf,
 516                                     size_t len)
 517 {
 518         size_t offset = 0;
 519
 520         if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) &&
 521             IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
 522                 readsl(ahb_base, buf, len >> 2);
 523                 offset = len & ~0x3;
 524                 len -= offset;
 525         }
 526
 527         readsb(ahb_base, (u8 *)buf + offset, len);
 528
 529         return 0;
 530 }
 531
 532 static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf,
 533                                    size_t len)
 534 {
 535         size_t offset = 0;
 536
 537         if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) &&
 538             IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
 539                 writesl(ahb_base, buf, len >> 2);
 540                 offset = len & ~0x3;
 541                 len -= offset;
 542         }
 543
 544         writesb(ahb_base, (u8 *)buf + offset, len);
 545
 546         return 0;
 547 }
 548
 549 /*
 550  * Currently, only support 1-1-1, 1-1-2 or 1-1-4
 551  * SPI NOR flash operation format.
 552  */
 553 static bool aspeed_spi_supports_op(struct spi_slave *slave,
 554                                    const struct spi_mem_op *op)
 555 {
 556         struct udevice *bus = slave->dev->parent;
 557         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 558
 559         if (op->cmd.buswidth > 1)
 560                 return false;
 561
 562         if (op->addr.nbytes != 0) {
 563                 if (op->addr.buswidth > 1)
 564                         return false;
 565                 if (op->addr.nbytes < 3 || op->addr.nbytes > 4)
 566                         return false;
 567         }
 568
 569         if (op->dummy.nbytes != 0) {
 570                 if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
 571                         return false;
 572         }
 573
 574         if (op->data.nbytes != 0 &&
 575             op->data.buswidth > priv->info->max_bus_width)
 576                 return false;
 577
 578         if (!spi_mem_default_supports_op(slave, op))
 579                 return false;
 580
 581         return true;
 582 }
 583
 584 static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave,
 585                                         const struct spi_mem_op *op)
 586 {
 587         struct udevice *dev = slave->dev;
 588         struct udevice *bus = dev->parent;
 589         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 590         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev);
 591         u32 cs = slave_plat->cs[0];
 592         u32 ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs];
 593         u32 ce_ctrl_val;
 594         struct aspeed_spi_flash *flash = &priv->flashes[cs];
 595         u8 dummy_data[16] = {0};
 596         u8 addr[4] = {0};
 597         int i;
 598
 599         dev_dbg(dev, "cmd:%x(%d),addr:%llx(%d),dummy:%d(%d),data_len:0x%x(%d)\n",
 600                 op->cmd.opcode, op->cmd.buswidth, op->addr.val,
 601                 op->addr.buswidth, op->dummy.nbytes, op->dummy.buswidth,
 602                 op->data.nbytes, op->data.buswidth);
 603
 604         if (priv->info == &ast2400_spi_info)
 605                 ce_ctrl_reg = (u32)&priv->regs->ctrl;
 606
 607         /*
 608          * Set controller to 4-byte address mode
 609          * if flash is in 4-byte address mode.
 610          */
 611         if (op->cmd.opcode == SPINOR_OP_EN4B)
 612                 priv->info->set_4byte(bus, cs);
 613
 614         /* Start user mode */
 615         ce_ctrl_val = flash->ce_ctrl_user;
 616         writel(ce_ctrl_val, ce_ctrl_reg);
 617         ce_ctrl_val &= (~CTRL_STOP_ACTIVE);
 618         writel(ce_ctrl_val, ce_ctrl_reg);
 619
 620         /* Send command */
 621         aspeed_spi_write_to_ahb(flash->ahb_base, &op->cmd.opcode, 1);
 622
 623         /* Send address */
 624         for (i = op->addr.nbytes; i > 0; i--) {
 625                 addr[op->addr.nbytes - i] =
 626                         ((u32)op->addr.val >> ((i - 1) * 8)) & 0xff;
 627         }
 628
 629         /* Change io_mode */
 630         ce_ctrl_val &= ~priv->info->io_mode_mask;
 631         ce_ctrl_val |= aspeed_spi_get_io_mode(op->addr.buswidth);
 632         writel(ce_ctrl_val, ce_ctrl_reg);
 633         aspeed_spi_write_to_ahb(flash->ahb_base, addr, op->addr.nbytes);
 634
 635         /* Send dummy cycles */
 636         aspeed_spi_write_to_ahb(flash->ahb_base, dummy_data, op->dummy.nbytes);
 637
 638         /* Change io_mode */
 639         ce_ctrl_val &= ~priv->info->io_mode_mask;
 640         ce_ctrl_val |= aspeed_spi_get_io_mode(op->data.buswidth);
 641         writel(ce_ctrl_val, ce_ctrl_reg);
 642
 643         /* Send data */
 644         if (op->data.dir == SPI_MEM_DATA_OUT) {
 645                 aspeed_spi_write_to_ahb(flash->ahb_base, op->data.buf.out,
 646                                         op->data.nbytes);
 647         } else {
 648                 aspeed_spi_read_from_ahb(flash->ahb_base, op->data.buf.in,
 649                                          op->data.nbytes);
 650         }
 651
 652         ce_ctrl_val |= CTRL_STOP_ACTIVE;
 653         writel(ce_ctrl_val, ce_ctrl_reg);
 654
 655         /* Restore controller setting. */
 656         writel(flash->ce_ctrl_read, ce_ctrl_reg);
 657
 658         return 0;
 659 }
 660
 661 static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
 662 {
 663         int ret = 0;
 664         struct udevice *dev = desc->slave->dev;
 665         struct udevice *bus = dev->parent;
 666         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 667         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 668         const struct aspeed_spi_info *info = priv->info;
 669         struct spi_mem_op op_tmpl = desc->info.op_tmpl;
 670         u32 i;
 671         u32 cs = slave_plat->cs[0];
 672         u32 cmd_io_conf;
 673         u32 ce_ctrl_reg;
 674
 675         if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) {
 676                 /*
 677                  * dirmap_write is not supported currently due to a HW
 678                  * limitation for command write mode: The written data
 679                  * length should be multiple of 4-byte.
 680                  */
 681                 return -EOPNOTSUPP;
 682         }
 683
 684         ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs];
 685         if (info == &ast2400_spi_info)
 686                 ce_ctrl_reg = (u32)&priv->regs->ctrl;
 687
 688         if (desc->info.length > 0x1000000)
 689                 priv->info->set_4byte(bus, cs);
 690
 691         /* AST2400 SPI1 doesn't have decoded address segment register. */
 692         if (info != &ast2400_spi_info) {
 693                 priv->flashes[cs].ahb_decoded_sz = desc->info.length;
 694
 695                 for (i = 0; i < priv->num_cs; i++) {
 696                         dev_dbg(dev, "cs: %d, sz: 0x%x\n", i,
 697                                 priv->flashes[cs].ahb_decoded_sz);
 698                 }
 699
 700                 ret = aspeed_spi_decoded_range_config(bus);
 701                 if (ret)
 702                         return ret;
 703         }
 704
 705         cmd_io_conf = aspeed_spi_get_io_mode(op_tmpl.data.buswidth) |
 706                       op_tmpl.cmd.opcode << 16 |
 707                       ((op_tmpl.dummy.nbytes) & 0x3) << 6 |
 708                       ((op_tmpl.dummy.nbytes) & 0x4) << 14 |
 709                       CTRL_IO_MODE_CMD_READ;
 710
 711         priv->flashes[cs].ce_ctrl_read &= priv->info->clk_ctrl_mask;
 712         priv->flashes[cs].ce_ctrl_read |= cmd_io_conf;
 713
 714         writel(priv->flashes[cs].ce_ctrl_read, ce_ctrl_reg);
 715
 716         dev_dbg(dev, "read bus width: %d ce_ctrl_val: 0x%08x\n",
 717                 op_tmpl.data.buswidth, priv->flashes[cs].ce_ctrl_read);
 718
 719         return ret;
 720 }
 721
 722 static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
 723                                       u64 offs, size_t len, void *buf)
 724 {
 725         struct udevice *dev = desc->slave->dev;
 726         struct aspeed_spi_priv *priv = dev_get_priv(dev->parent);
 727         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 728         u32 cs = slave_plat->cs[0];
 729         int ret;
 730
 731         dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n",
 732                 desc->info.op_tmpl.cmd.opcode, offs, len);
 733
 734         if (priv->flashes[cs].ahb_decoded_sz < offs + len ||
 735             (offs % 4) != 0) {
 736                 ret = aspeed_spi_exec_op_user_mode(desc->slave,
 737                                                    &desc->info.op_tmpl);
 738                 if (ret != 0)
 739                         return 0;
 740         } else {
 741                 memcpy_fromio(buf, priv->flashes[cs].ahb_base + offs, len);
 742         }
 743
 744         return len;
 745 }
 746
 747 static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev)
 748 {
 749         struct udevice *bus = dev->parent;
 750         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 751         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 752         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 753         u32 cs = slave_plat->cs[0];
 754
 755         if (cs >= plat->max_cs) {
 756                 dev_err(dev, "invalid CS %u\n", cs);
 757                 return NULL;
 758         }
 759
 760         return &priv->flashes[cs];
 761 }
 762
 763 static void aspeed_spi_decoded_base_calculate(struct udevice *bus)
 764 {
 765         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 766         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 767         u32 cs;
 768
 769         if (priv->fixed_decoded_range)
 770                 return;
 771
 772         priv->flashes[0].ahb_base = plat->ahb_base;
 773
 774         for (cs = 1; cs < plat->max_cs; cs++) {
 775                 priv->flashes[cs].ahb_base =
 776                                 priv->flashes[cs - 1].ahb_base +
 777                                 priv->flashes[cs - 1].ahb_decoded_sz;
 778         }
 779 }
 780
 781 static void aspeed_spi_decoded_range_set(struct udevice *bus)
 782 {
 783         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 784         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 785         u32 decoded_reg_val;
 786         u32 start_addr, end_addr;
 787         u32 cs;
 788
 789         for (cs = 0; cs < plat->max_cs; cs++) {
 790                 start_addr = (u32)priv->flashes[cs].ahb_base;
 791                 end_addr = (u32)priv->flashes[cs].ahb_base +
 792                            priv->flashes[cs].ahb_decoded_sz;
 793
 794                 decoded_reg_val = priv->info->segment_reg(start_addr, end_addr);
 795
 796                 writel(decoded_reg_val, &priv->regs->segment_addr[cs]);
 797
 798                 dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%x, end: 0x%x\n",
 799                         cs, decoded_reg_val, start_addr, end_addr);
 800         }
 801 }
 802
 803 static int aspeed_spi_decoded_range_config(struct udevice *bus)
 804 {
 805         int ret = 0;
 806         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 807
 808         if (priv->info->adjust_decoded_sz &&
 809             !priv->fixed_decoded_range) {
 810                 ret = priv->info->adjust_decoded_sz(bus);
 811                 if (ret != 0)
 812                         return ret;
 813         }
 814
 815         aspeed_spi_decoded_base_calculate(bus);
 816         aspeed_spi_decoded_range_set(bus);
 817
 818         return ret;
 819 }
 820
 821 static int aspeed_spi_decoded_ranges_sanity(struct udevice *bus)
 822 {
 823         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 824         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 825         u32 cs;
 826         u32 total_sz = 0;
 827
 828         /* Check overall size. */
 829         for (cs = 0; cs < plat->max_cs; cs++)
 830                 total_sz += priv->flashes[cs].ahb_decoded_sz;
 831
 832         if (total_sz > plat->ahb_sz) {
 833                 dev_err(bus, "invalid total size 0x%08x\n", total_sz);
 834                 return -EINVAL;
 835         }
 836
 837         /* Check each decoded range size for AST2500. */
 838         if (priv->info == &ast2500_fmc_info ||
 839             priv->info == &ast2500_spi_info) {
 840                 for (cs = 0; cs < plat->max_cs; cs++) {
 841                         if (priv->flashes[cs].ahb_decoded_sz <
 842                             priv->info->min_decoded_sz) {
 843                                 dev_err(bus, "insufficient decoded range.\n");
 844                                 return -EINVAL;
 845                         }
 846                 }
 847         }
 848
 849         /*
 850          * Check overlay. Here, we assume the deccded ranges and
 851          * address base are monotonic increasing with CE#.
 852          */
 853         for (cs = plat->max_cs - 1; cs > 0; cs--) {
 854                 if ((u32)priv->flashes[cs].ahb_base != 0 &&
 855                     (u32)priv->flashes[cs].ahb_base <
 856                     (u32)priv->flashes[cs - 1].ahb_base +
 857                     priv->flashes[cs - 1].ahb_decoded_sz) {
 858                         dev_err(bus, "decoded range overlay 0x%08x 0x%08x\n",
 859                                 (u32)priv->flashes[cs].ahb_base,
 860                                 (u32)priv->flashes[cs - 1].ahb_base);
 861                         return -EINVAL;
 862                 }
 863         }
 864
 865         return 0;
 866 }
 867
 868 static int aspeed_spi_read_fixed_decoded_ranges(struct udevice *bus)
 869 {
 870         int ret = 0;
 871         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 872         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 873         const char *range_prop = "decoded-ranges";
 874         struct aspeed_spi_decoded_range ranges[ASPEED_SPI_MAX_CS];
 875         const struct property *prop;
 876         u32 prop_sz;
 877         u32 count;
 878         u32 i;
 879
 880         priv->fixed_decoded_range = false;
 881
 882         prop = dev_read_prop(bus, range_prop, &prop_sz);
 883         if (!prop)
 884                 return 0;
 885
 886         count = prop_sz / sizeof(struct aspeed_spi_decoded_range);
 887         if (count > plat->max_cs || count < priv->num_cs) {
 888                 dev_err(bus, "invalid '%s' property %d %d\n",
 889                         range_prop, count, priv->num_cs);
 890                 return -EINVAL;
 891         }
 892
 893         ret = dev_read_u32_array(bus, range_prop, (u32 *)ranges, count * 3);
 894         if (ret)
 895                 return ret;
 896
 897         for (i = 0; i < count; i++) {
 898                 priv->flashes[ranges[i].cs].ahb_base =
 899                                 (void __iomem *)ranges[i].ahb_base;
 900                 priv->flashes[ranges[i].cs].ahb_decoded_sz =
 901                                 ranges[i].sz;
 902         }
 903
 904         for (i = 0; i < plat->max_cs; i++) {
 905                 dev_dbg(bus, "ahb_base: 0x%p, size: 0x%08x\n",
 906                         priv->flashes[i].ahb_base,
 907                         priv->flashes[i].ahb_decoded_sz);
 908         }
 909
 910         ret = aspeed_spi_decoded_ranges_sanity(bus);
 911         if (ret != 0)
 912                 return ret;
 913
 914         priv->fixed_decoded_range = true;
 915
 916         return 0;
 917 }
 918
 919 /*
 920  * Initialize SPI controller for each chip select.
 921  * Here, only the minimum decode range is configured
 922  * in order to get device (SPI NOR flash) information
 923  * at the early stage.
 924  */
 925 static int aspeed_spi_ctrl_init(struct udevice *bus)
 926 {
 927         int ret;
 928         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 929         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 930         u32 cs;
 931         u32 reg_val;
 932         u32 decoded_sz;
 933
 934         /* Enable write capability for all CS. */
 935         reg_val = readl(&priv->regs->conf);
 936         if (priv->info == &ast2400_spi_info) {
 937                 writel(reg_val | BIT(0), &priv->regs->conf);
 938         } else {
 939                 writel(reg_val | (GENMASK(plat->max_cs - 1, 0) << 16),
 940                        &priv->regs->conf);
 941         }
 942
 943         memset(priv->flashes, 0x0,
 944                sizeof(struct aspeed_spi_flash) * ASPEED_SPI_MAX_CS);
 945
 946         /* Initial user mode. */
 947         for (cs = 0; cs < priv->num_cs; cs++) {
 948                 priv->flashes[cs].ce_ctrl_user &= priv->info->clk_ctrl_mask;
 949                 priv->flashes[cs].ce_ctrl_user |=
 950                                 (CTRL_STOP_ACTIVE | CTRL_IO_MODE_USER);
 951         }
 952
 953         /*
 954          * SPI1 on AST2400 only supports CS0.
 955          * It is unnecessary to configure segment address register.
 956          */
 957         if (priv->info == &ast2400_spi_info) {
 958                 priv->flashes[cs].ahb_base = plat->ahb_base;
 959                 priv->flashes[cs].ahb_decoded_sz = 0x10000000;
 960                 return 0;
 961         }
 962
 963         ret = aspeed_spi_read_fixed_decoded_ranges(bus);
 964         if (ret != 0)
 965                 return ret;
 966
 967         if (!priv->fixed_decoded_range) {
 968                 /* Assign basic AHB decoded size for each CS. */
 969                 for (cs = 0; cs < plat->max_cs; cs++) {
 970                         reg_val = readl(&priv->regs->segment_addr[cs]);
 971                         decoded_sz = priv->info->segment_end(bus, reg_val) -
 972                                      priv->info->segment_start(bus, reg_val);
 973
 974                         if (decoded_sz < priv->info->min_decoded_sz)
 975                                 decoded_sz = priv->info->min_decoded_sz;
 976
 977                         priv->flashes[cs].ahb_decoded_sz = decoded_sz;
 978                 }
 979         }
 980
 981         ret = aspeed_spi_decoded_range_config(bus);
 982
 983         return ret;
 984 }
 985
 986 static const struct aspeed_spi_info ast2400_fmc_info = {
 987         .io_mode_mask = 0x70000000,
 988         .max_bus_width = 2,
 989         .min_decoded_sz = 0x800000,
 990         .clk_ctrl_mask = 0x00002f00,
 991         .set_4byte = ast2400_fmc_chip_set_4byte,
 992         .segment_start = ast2400_spi_segment_start,
 993         .segment_end = ast2400_spi_segment_end,
 994         .segment_reg = ast2400_spi_segment_reg,
 995         .get_clk_setting = ast2400_get_clk_setting,
 996 };
 997
 998 static const struct aspeed_spi_info ast2400_spi_info = {
 999         .io_mode_mask = 0x70000000,
1000         .max_bus_width = 2,
1001         .min_decoded_sz = 0x800000,
1002         .clk_ctrl_mask = 0x00000f00,
1003         .set_4byte = ast2400_spi_chip_set_4byte,
1004         .segment_start = ast2400_spi_segment_start,
1005         .segment_end = ast2400_spi_segment_end,
1006         .segment_reg = ast2400_spi_segment_reg,
1007         .get_clk_setting = ast2400_get_clk_setting,
1008 };
1009
1010 static const struct aspeed_spi_info ast2500_fmc_info = {
1011         .io_mode_mask = 0x70000000,
1012         .max_bus_width = 2,
1013         .min_decoded_sz = 0x800000,
1014         .clk_ctrl_mask = 0x00002f00,
1015         .set_4byte = ast2500_spi_chip_set_4byte,
1016         .segment_start = ast2500_spi_segment_start,
1017         .segment_end = ast2500_spi_segment_end,
1018         .segment_reg = ast2500_spi_segment_reg,
1019         .adjust_decoded_sz = ast2500_adjust_decoded_size,
1020         .get_clk_setting = ast2500_get_clk_setting,
1021 };
1022
1023 /*
1024  * There are some different between FMC and SPI controllers.
1025  * For example, DMA operation, but this isn't implemented currently.
1026  */
1027 static const struct aspeed_spi_info ast2500_spi_info = {
1028         .io_mode_mask = 0x70000000,
1029         .max_bus_width = 2,
1030         .min_decoded_sz = 0x800000,
1031         .clk_ctrl_mask = 0x00002f00,
1032         .set_4byte = ast2500_spi_chip_set_4byte,
1033         .segment_start = ast2500_spi_segment_start,
1034         .segment_end = ast2500_spi_segment_end,
1035         .segment_reg = ast2500_spi_segment_reg,
1036         .adjust_decoded_sz = ast2500_adjust_decoded_size,
1037         .get_clk_setting = ast2500_get_clk_setting,
1038 };
1039
1040 static const struct aspeed_spi_info ast2600_fmc_info = {
1041         .io_mode_mask = 0xf0000000,
1042         .max_bus_width = 4,
1043         .min_decoded_sz = 0x200000,
1044         .clk_ctrl_mask = 0x0f000f00,
1045         .set_4byte = ast2600_spi_chip_set_4byte,
1046         .segment_start = ast2600_spi_segment_start,
1047         .segment_end = ast2600_spi_segment_end,
1048         .segment_reg = ast2600_spi_segment_reg,
1049         .adjust_decoded_sz = ast2600_adjust_decoded_size,
1050         .get_clk_setting = ast2600_get_clk_setting,
1051 };
1052
1053 static const struct aspeed_spi_info ast2600_spi_info = {
1054         .io_mode_mask = 0xf0000000,
1055         .max_bus_width = 4,
1056         .min_decoded_sz = 0x200000,
1057         .clk_ctrl_mask = 0x0f000f00,
1058         .set_4byte = ast2600_spi_chip_set_4byte,
1059         .segment_start = ast2600_spi_segment_start,
1060         .segment_end = ast2600_spi_segment_end,
1061         .segment_reg = ast2600_spi_segment_reg,
1062         .adjust_decoded_sz = ast2600_adjust_decoded_size,
1063         .get_clk_setting = ast2600_get_clk_setting,
1064 };
1065
1066 static int aspeed_spi_claim_bus(struct udevice *dev)
1067 {
1068         struct udevice *bus = dev->parent;
1069         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
1070         struct aspeed_spi_priv *priv = dev_get_priv(dev->parent);
1071         struct aspeed_spi_flash *flash = &priv->flashes[slave_plat->cs[0]];
1072         u32 clk_setting;
1073
1074         dev_dbg(bus, "%s: claim bus CS%u\n", bus->name, slave_plat->cs[0]);
1075
1076         if (flash->max_freq == 0) {
1077                 clk_setting = priv->info->get_clk_setting(dev, slave_plat->max_hz);
1078                 flash->ce_ctrl_user &= ~(priv->info->clk_ctrl_mask);
1079                 flash->ce_ctrl_user |= clk_setting;
1080                 flash->ce_ctrl_read &= ~(priv->info->clk_ctrl_mask);
1081                 flash->ce_ctrl_read |= clk_setting;
1082         }
1083
1084         return 0;
1085 }
1086
1087 static int aspeed_spi_release_bus(struct udevice *dev)
1088 {
1089         struct udevice *bus = dev->parent;
1090         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
1091
1092         dev_dbg(bus, "%s: release bus CS%u\n", bus->name, slave_plat->cs[0]);
1093
1094         if (!aspeed_spi_get_flash(dev))
1095                 return -ENODEV;
1096
1097         return 0;
1098 }
1099
1100 static int aspeed_spi_set_mode(struct udevice *bus, uint mode)
1101 {
1102         dev_dbg(bus, "%s: setting mode to %x\n", bus->name, mode);
1103
1104         return 0;
1105 }
1106
1107 static int aspeed_spi_set_speed(struct udevice *bus, uint hz)
1108 {
1109         dev_dbg(bus, "%s: setting speed to %u\n", bus->name, hz);
1110         /*
1111          * ASPEED SPI controller supports multiple CS with different
1112          * clock frequency. We cannot distinguish which CS here.
1113          * Thus, the related implementation is postponed to claim_bus.
1114          */
1115
1116         return 0;
1117 }
1118
1119 static int apseed_spi_of_to_plat(struct udevice *bus)
1120 {
1121         struct aspeed_spi_plat *plat = dev_get_plat(bus);
1122         struct aspeed_spi_priv *priv = dev_get_priv(bus);
1123         int ret;
1124         struct clk hclk;
1125
1126         priv->regs = devfdt_get_addr_index_ptr(bus, 0);
1127         if (!priv->regs) {
1128                 dev_err(bus, "wrong ctrl base\n");
1129                 return -EINVAL;
1130         }
1131
1132         plat->ahb_base = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahb_sz);
1133         if (!plat->ahb_base) {
1134                 dev_err(bus, "wrong AHB base\n");
1135                 return -EINVAL;
1136         }
1137
1138         plat->max_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS);
1139         if (plat->max_cs > ASPEED_SPI_MAX_CS)
1140                 return -EINVAL;
1141
1142         ret = clk_get_by_index(bus, 0, &hclk);
1143         if (ret < 0) {
1144                 dev_err(bus, "%s could not get clock: %d\n", bus->name, ret);
1145                 return ret;
1146         }
1147
1148         plat->hclk_rate = clk_get_rate(&hclk);
1149
1150         dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%llx\n",
1151                 (u32)priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz);
1152         dev_dbg(bus, "hclk = %dMHz, max_cs = %d\n",
1153                 plat->hclk_rate / 1000000, plat->max_cs);
1154
1155         return 0;
1156 }
1157
1158 static int aspeed_spi_probe(struct udevice *bus)
1159 {
1160         int ret;
1161         struct aspeed_spi_priv *priv = dev_get_priv(bus);
1162         struct udevice *dev;
1163
1164         priv->info = (struct aspeed_spi_info *)dev_get_driver_data(bus);
1165
1166         priv->num_cs = 0;
1167         for (device_find_first_child(bus, &dev); dev;
1168              device_find_next_child(&dev)) {
1169                 priv->num_cs++;
1170         }
1171
1172         if (priv->num_cs > ASPEED_SPI_MAX_CS)
1173                 return -EINVAL;
1174
1175         ret = aspeed_spi_ctrl_init(bus);
1176
1177         return ret;
1178 }
1179
1180 static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
1181         .supports_op = aspeed_spi_supports_op,
1182         .exec_op = aspeed_spi_exec_op_user_mode,
1183         .dirmap_create = aspeed_spi_dirmap_create,
1184         .dirmap_read = aspeed_spi_dirmap_read,
1185 };
1186
1187 static const struct dm_spi_ops aspeed_spi_ops = {
1188         .claim_bus = aspeed_spi_claim_bus,
1189         .release_bus = aspeed_spi_release_bus,
1190         .set_speed = aspeed_spi_set_speed,
1191         .set_mode = aspeed_spi_set_mode,
1192         .mem_ops = &aspeed_spi_mem_ops,
1193 };
1194
1195 static const struct udevice_id aspeed_spi_ids[] = {
1196         { .compatible = "aspeed,ast2400-fmc", .data = (ulong)&ast2400_fmc_info, },
1197         { .compatible = "aspeed,ast2400-spi", .data = (ulong)&ast2400_spi_info, },
1198         { .compatible = "aspeed,ast2500-fmc", .data = (ulong)&ast2500_fmc_info, },
1199         { .compatible = "aspeed,ast2500-spi", .data = (ulong)&ast2500_spi_info, },
1200         { .compatible = "aspeed,ast2600-fmc", .data = (ulong)&ast2600_fmc_info, },
1201         { .compatible = "aspeed,ast2600-spi", .data = (ulong)&ast2600_spi_info, },
1202         { }
1203 };
1204
1205 U_BOOT_DRIVER(aspeed_spi) = {
1206         .name = "aspeed_spi_smc",
1207         .id = UCLASS_SPI,
1208         .of_match = aspeed_spi_ids,
1209         .ops = &aspeed_spi_ops,
1210         .of_to_plat = apseed_spi_of_to_plat,
1211         .plat_auto = sizeof(struct aspeed_spi_plat),
1212         .priv_auto = sizeof(struct aspeed_spi_priv),
1213         .probe = aspeed_spi_probe,
1214 };