include/configs/M5235EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF5329 FireEngine board.
   4  *
   5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6  * TsiChung Liew ([email protected])
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M5235EVB_H
  14 #define _M5235EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  24
  25 /* I2C */
  26 #define CONFIG_SYS_I2C_PINMUX_REG       (gpio->par_qspi)
  27 #define CONFIG_SYS_I2C_PINMUX_CLR       ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
  28 #define CONFIG_SYS_I2C_PINMUX_SET       (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
  29
  30 /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
  31 #ifdef CONFIG_MCFFEC
  32 #       define CONFIG_IPADDR    192.162.1.2
  33 #       define CONFIG_NETMASK   255.255.255.0
  34 #       define CONFIG_SERVERIP  192.162.1.1
  35 #       define CONFIG_GATEWAYIP 192.162.1.1
  36 #endif                          /* FEC_ENET */
  37
  38 #define CONFIG_HOSTNAME         "M5235EVB"
  39 #define CONFIG_EXTRA_ENV_SETTINGS               \
  40         "netdev=eth0\0"                         \
  41         "loadaddr=10000\0"                      \
  42         "u-boot=u-boot.bin\0"                   \
  43         "load=tftp ${loadaddr) ${u-boot}\0"     \
  44         "upd=run load; run prog\0"              \
  45         "prog=prot off ffe00000 ffe3ffff;"      \
  46         "era ffe00000 ffe3ffff;"                \
  47         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  48         "save\0"                                \
  49         ""
  50
  51 #define CONFIG_PRAM             512     /* 512 KB */
  52
  53 #define CONFIG_SYS_CLK                  75000000
  54 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 2
  55
  56 #define CONFIG_SYS_MBAR         0x40000000
  57
  58 /*
  59  * Low Level Configuration Settings
  60  * (address mappings, register initial values, etc.)
  61  * You should know what you are doing if you make changes here.
  62  */
  63 /*-----------------------------------------------------------------------
  64  * Definitions for initial stack pointer and data area (in DPRAM)
  65  */
  66 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  67 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
  68 #define CONFIG_SYS_INIT_RAM_CTRL        0x21
  69
  70 /*-----------------------------------------------------------------------
  71  * Start addresses for the final memory configuration
  72  * (Set up by the startup code)
  73  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  74  */
  75 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  76 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
  77
  78 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
  79
  80 /*
  81  * For booting Linux, the board info and command line data
  82  * have to be in the first 8 MB of memory, since this is
  83  * the maximum mapped by the Linux kernel during initialization ??
  84  */
  85 /* Initial Memory map for Linux */
  86 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  87
  88 /*-----------------------------------------------------------------------
  89  * FLASH organization
  90  */
  91 #ifdef CONFIG_SYS_FLASH_CFI
  92 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
  93 #endif
  94
  95 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
  96
  97 /* Configuration for environment
  98  * Environment is embedded in u-boot in the second sector of the flash
  99  */
 100
 101 #define LDS_BOARD_TEXT \
 102         . = DEFINED(env_offset) ? env_offset : .; \
 103         env/embedded.o(.text);
 104
 105 /*-----------------------------------------------------------------------
 106  * Cache Configuration
 107  */
 108
 109 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 110                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 111 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 112                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 113 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV)
 114 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 115                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 116                                          CF_ACR_EN | CF_ACR_SM_ALL)
 117 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 118                                          CF_CACR_CEIB | CF_CACR_DCM | \
 119                                          CF_CACR_EUSP)
 120
 121 /*-----------------------------------------------------------------------
 122  * Chipselect bank definitions
 123  */
 124 /*
 125  * CS0 - NOR Flash 1, 2, 4, or 8MB
 126  * CS1 - Available
 127  * CS2 - Available
 128  * CS3 - Available
 129  * CS4 - Available
 130  * CS5 - Available
 131  * CS6 - Available
 132  * CS7 - Available
 133  */
 134 #ifdef CONFIG_NORFLASH_PS32BIT
 135 #       define CONFIG_SYS_CS0_BASE      0xFFC00000
 136 #       define CONFIG_SYS_CS0_MASK      0x003f0001
 137 #       define CONFIG_SYS_CS0_CTRL      0x00001D00
 138 #else
 139 #       define CONFIG_SYS_CS0_BASE      0xFFE00000
 140 #       define CONFIG_SYS_CS0_MASK      0x001f0001
 141 #       define CONFIG_SYS_CS0_CTRL      0x00001D80
 142 #endif
 143
 144 #endif                          /* _M5329EVB_H */