board/freescale/ls1043aqds/ls1043aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  * Copyright 2019-2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <asm/global_data.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/fsl_serdes.h>
  17 #include <asm/arch/ppa.h>
  18 #include <asm/arch/fdt.h>
  19 #include <asm/arch/mmu.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/soc.h>
  22 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  23 #include <ahci.h>
  24 #include <hwconfig.h>
  25 #include <mmc.h>
  26 #include <scsi.h>
  27 #include <fm_eth.h>
  28 #include <fsl_esdhc.h>
  29 #include <fsl_ifc.h>
  30 #include <spl.h>
  31
  32 #include "../common/qixis.h"
  33 #include "ls1043aqds_qixis.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 enum {
  38         MUX_TYPE_GPIO,
  39 };
  40
  41 /* LS1043AQDS serdes mux */
  42 #define CFG_SD_MUX1_SLOT2       0x0 /* SLOT2 TX/RX0 */
  43 #define CFG_SD_MUX1_SLOT1       0x1 /* SLOT1 TX/RX1 */
  44 #define CFG_SD_MUX2_SLOT3       0x0 /* SLOT3 TX/RX0 */
  45 #define CFG_SD_MUX2_SLOT1       0x1 /* SLOT1 TX/RX2 */
  46 #define CFG_SD_MUX3_SLOT4       0x0 /* SLOT4 TX/RX0 */
  47 #define CFG_SD_MUX3_MUX4        0x1 /* MUX4 */
  48 #define CFG_SD_MUX4_SLOT3       0x0 /* SLOT3 TX/RX1 */
  49 #define CFG_SD_MUX4_SLOT1       0x1 /* SLOT1 TX/RX3 */
  50 #define CFG_UART_MUX_MASK       0x6
  51 #define CFG_UART_MUX_SHIFT      1
  52 #define CFG_LPUART_EN           0x1
  53
  54 #ifdef CONFIG_SYS_I2C_EARLY_INIT
  55 void i2c_early_init_f(void);
  56 #endif
  57
  58 #ifdef CONFIG_TFABOOT
  59 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  60         {
  61                 "nor0",
  62                 CONFIG_SYS_NOR0_CSPR,
  63                 CONFIG_SYS_NOR0_CSPR_EXT,
  64                 CONFIG_SYS_NOR_AMASK,
  65                 CONFIG_SYS_NOR_CSOR,
  66                 {
  67                         CONFIG_SYS_NOR_FTIM0,
  68                         CONFIG_SYS_NOR_FTIM1,
  69                         CONFIG_SYS_NOR_FTIM2,
  70                         CONFIG_SYS_NOR_FTIM3
  71                 },
  72
  73         },
  74         {
  75                 "nor1",
  76                 CONFIG_SYS_NOR1_CSPR,
  77                 CONFIG_SYS_NOR1_CSPR_EXT,
  78                 CONFIG_SYS_NOR_AMASK,
  79                 CONFIG_SYS_NOR_CSOR,
  80                 {
  81                         CONFIG_SYS_NOR_FTIM0,
  82                         CONFIG_SYS_NOR_FTIM1,
  83                         CONFIG_SYS_NOR_FTIM2,
  84                         CONFIG_SYS_NOR_FTIM3
  85                 },
  86         },
  87         {
  88                 "nand",
  89                 CONFIG_SYS_NAND_CSPR,
  90                 CONFIG_SYS_NAND_CSPR_EXT,
  91                 CONFIG_SYS_NAND_AMASK,
  92                 CONFIG_SYS_NAND_CSOR,
  93                 {
  94                         CONFIG_SYS_NAND_FTIM0,
  95                         CONFIG_SYS_NAND_FTIM1,
  96                         CONFIG_SYS_NAND_FTIM2,
  97                         CONFIG_SYS_NAND_FTIM3
  98                 },
  99         },
 100         {
 101                 "fpga",
 102                 CONFIG_SYS_FPGA_CSPR,
 103                 CONFIG_SYS_FPGA_CSPR_EXT,
 104                 CONFIG_SYS_FPGA_AMASK,
 105                 CONFIG_SYS_FPGA_CSOR,
 106                 {
 107                         CONFIG_SYS_FPGA_FTIM0,
 108                         CONFIG_SYS_FPGA_FTIM1,
 109                         CONFIG_SYS_FPGA_FTIM2,
 110                         CONFIG_SYS_FPGA_FTIM3
 111                 },
 112         }
 113 };
 114
 115 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 116         {
 117                 "nand",
 118                 CONFIG_SYS_NAND_CSPR,
 119                 CONFIG_SYS_NAND_CSPR_EXT,
 120                 CONFIG_SYS_NAND_AMASK,
 121                 CONFIG_SYS_NAND_CSOR,
 122                 {
 123                         CONFIG_SYS_NAND_FTIM0,
 124                         CONFIG_SYS_NAND_FTIM1,
 125                         CONFIG_SYS_NAND_FTIM2,
 126                         CONFIG_SYS_NAND_FTIM3
 127                 },
 128         },
 129         {
 130                 "nor0",
 131                 CONFIG_SYS_NOR0_CSPR,
 132                 CONFIG_SYS_NOR0_CSPR_EXT,
 133                 CONFIG_SYS_NOR_AMASK,
 134                 CONFIG_SYS_NOR_CSOR,
 135                 {
 136                         CONFIG_SYS_NOR_FTIM0,
 137                         CONFIG_SYS_NOR_FTIM1,
 138                         CONFIG_SYS_NOR_FTIM2,
 139                         CONFIG_SYS_NOR_FTIM3
 140                 },
 141         },
 142         {
 143                 "nor1",
 144                 CONFIG_SYS_NOR1_CSPR,
 145                 CONFIG_SYS_NOR1_CSPR_EXT,
 146                 CONFIG_SYS_NOR_AMASK,
 147                 CONFIG_SYS_NOR_CSOR,
 148                 {
 149                         CONFIG_SYS_NOR_FTIM0,
 150                         CONFIG_SYS_NOR_FTIM1,
 151                         CONFIG_SYS_NOR_FTIM2,
 152                         CONFIG_SYS_NOR_FTIM3
 153                 },
 154         },
 155         {
 156                 "fpga",
 157                 CONFIG_SYS_FPGA_CSPR,
 158                 CONFIG_SYS_FPGA_CSPR_EXT,
 159                 CONFIG_SYS_FPGA_AMASK,
 160                 CONFIG_SYS_FPGA_CSOR,
 161                 {
 162                         CONFIG_SYS_FPGA_FTIM0,
 163                         CONFIG_SYS_FPGA_FTIM1,
 164                         CONFIG_SYS_FPGA_FTIM2,
 165                         CONFIG_SYS_FPGA_FTIM3
 166                 },
 167         }
 168 };
 169
 170 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 171 {
 172         enum boot_src src = get_boot_src();
 173
 174         if (src == BOOT_SOURCE_IFC_NAND)
 175                 regs_info->regs = ifc_cfg_nand_boot;
 176         else
 177                 regs_info->regs = ifc_cfg_nor_boot;
 178         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 179 }
 180 #endif
 181
 182 int checkboard(void)
 183 {
 184 #ifdef CONFIG_TFABOOT
 185         enum boot_src src = get_boot_src();
 186 #endif
 187         char buf[64];
 188 #ifndef CONFIG_SD_BOOT
 189         u8 sw;
 190 #endif
 191
 192         puts("Board: LS1043AQDS, boot from ");
 193
 194 #ifdef CONFIG_TFABOOT
 195         if (src == BOOT_SOURCE_SD_MMC)
 196                 puts("SD\n");
 197         else {
 198 #endif
 199
 200 #ifdef CONFIG_SD_BOOT
 201         puts("SD\n");
 202 #else
 203         sw = QIXIS_READ(brdcfg[0]);
 204         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 205
 206         if (sw < 0x8)
 207                 printf("vBank: %d\n", sw);
 208         else if (sw == 0x8)
 209                 puts("PromJet\n");
 210         else if (sw == 0x9)
 211                 puts("NAND\n");
 212         else if (sw == 0xF)
 213                 printf("QSPI\n");
 214         else
 215                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 216 #endif
 217
 218 #ifdef CONFIG_TFABOOT
 219         }
 220 #endif
 221         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 222                QIXIS_READ(id), QIXIS_READ(arch));
 223
 224         printf("FPGA:  v%d (%s), build %d\n",
 225                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 226                (int)qixis_read_minor());
 227
 228         return 0;
 229 }
 230
 231 bool if_board_diff_clk(void)
 232 {
 233         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 234
 235         return diff_conf & 0x40;
 236 }
 237
 238 unsigned long get_board_sys_clk(void)
 239 {
 240         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 241
 242         switch (sysclk_conf & 0x0f) {
 243         case QIXIS_SYSCLK_64:
 244                 return 64000000;
 245         case QIXIS_SYSCLK_83:
 246                 return 83333333;
 247         case QIXIS_SYSCLK_100:
 248                 return 100000000;
 249         case QIXIS_SYSCLK_125:
 250                 return 125000000;
 251         case QIXIS_SYSCLK_133:
 252                 return 133333333;
 253         case QIXIS_SYSCLK_150:
 254                 return 150000000;
 255         case QIXIS_SYSCLK_160:
 256                 return 160000000;
 257         case QIXIS_SYSCLK_166:
 258                 return 166666666;
 259         }
 260
 261         return 66666666;
 262 }
 263
 264 unsigned long get_board_ddr_clk(void)
 265 {
 266         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 267
 268         if (if_board_diff_clk())
 269                 return get_board_sys_clk();
 270         switch ((ddrclk_conf & 0x30) >> 4) {
 271         case QIXIS_DDRCLK_100:
 272                 return 100000000;
 273         case QIXIS_DDRCLK_125:
 274                 return 125000000;
 275         case QIXIS_DDRCLK_133:
 276                 return 133333333;
 277         }
 278
 279         return 66666666;
 280 }
 281
 282 int select_i2c_ch_pca9547(u8 ch, int bus_num)
 283 {
 284         int ret;
 285
 286 #ifdef CONFIG_DM_I2C
 287         struct udevice *dev;
 288
 289         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
 290                                       1, &dev);
 291         if (ret) {
 292                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 293                        bus_num);
 294                 return ret;
 295         }
 296         ret = dm_i2c_write(dev, 0, &ch, 1);
 297 #else
 298         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 299 #endif
 300         if (ret) {
 301                 puts("PCA: failed to select proper channel\n");
 302                 return ret;
 303         }
 304
 305         return 0;
 306 }
 307
 308 int dram_init(void)
 309 {
 310         /*
 311          * When resuming from deep sleep, the I2C channel may not be
 312          * in the default channel. So, switch to the default channel
 313          * before accessing DDR SPD.
 314          *
 315          * PCA9547 mount on I2C1 bus
 316          */
 317         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 318         fsl_initdram();
 319 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 320         defined(CONFIG_SPL_BUILD)
 321         /* This will break-before-make MMU for DDR */
 322         update_early_mmu_table();
 323 #endif
 324
 325         return 0;
 326 }
 327
 328 int i2c_multiplexer_select_vid_channel(u8 channel)
 329 {
 330         return select_i2c_ch_pca9547(channel, 0);
 331 }
 332
 333 void board_retimer_init(void)
 334 {
 335         u8 reg;
 336         int bus_num = 0;
 337
 338         /* Retimer is connected to I2C1_CH7_CH5 */
 339         select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
 340         reg = I2C_MUX_CH5;
 341 #ifdef CONFIG_DM_I2C
 342         struct udevice *dev;
 343         int ret;
 344
 345         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
 346                                       1, &dev);
 347         if (ret) {
 348                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 349                        bus_num);
 350                 return;
 351         }
 352         dm_i2c_write(dev, 0, &reg, 1);
 353
 354         /* Access to Control/Shared register */
 355         ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
 356                                       1, &dev);
 357         if (ret) {
 358                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 359                        bus_num);
 360                 return;
 361         }
 362
 363         reg = 0x0;
 364         dm_i2c_write(dev, 0xff, &reg, 1);
 365
 366         /* Read device revision and ID */
 367         dm_i2c_read(dev, 1, &reg, 1);
 368         debug("Retimer version id = 0x%x\n", reg);
 369
 370         /* Enable Broadcast. All writes target all channel register sets */
 371         reg = 0x0c;
 372         dm_i2c_write(dev, 0xff, &reg, 1);
 373
 374         /* Reset Channel Registers */
 375         dm_i2c_read(dev, 0, &reg, 1);
 376         reg |= 0x4;
 377         dm_i2c_write(dev, 0, &reg, 1);
 378
 379         /* Enable override divider select and Enable Override Output Mux */
 380         dm_i2c_read(dev, 9, &reg, 1);
 381         reg |= 0x24;
 382         dm_i2c_write(dev, 9, &reg, 1);
 383
 384         /* Select VCO Divider to full rate (000) */
 385         dm_i2c_read(dev, 0x18, &reg, 1);
 386         reg &= 0x8f;
 387         dm_i2c_write(dev, 0x18, &reg, 1);
 388
 389         /* Selects active PFD MUX Input as Re-timed Data (001) */
 390         dm_i2c_read(dev, 0x1e, &reg, 1);
 391         reg &= 0x3f;
 392         reg |= 0x20;
 393         dm_i2c_write(dev, 0x1e, &reg, 1);
 394
 395         /* Set data rate as 10.3125 Gbps */
 396         reg = 0x0;
 397         dm_i2c_write(dev, 0x60, &reg, 1);
 398         reg = 0xb2;
 399         dm_i2c_write(dev, 0x61, &reg, 1);
 400         reg = 0x90;
 401         dm_i2c_write(dev, 0x62, &reg, 1);
 402         reg = 0xb3;
 403         dm_i2c_write(dev, 0x63, &reg, 1);
 404         reg = 0xcd;
 405         dm_i2c_write(dev, 0x64, &reg, 1);
 406 #else
 407         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 408
 409         /* Access to Control/Shared register */
 410         reg = 0x0;
 411         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 412
 413         /* Read device revision and ID */
 414         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 415         debug("Retimer version id = 0x%x\n", reg);
 416
 417         /* Enable Broadcast. All writes target all channel register sets */
 418         reg = 0x0c;
 419         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 420
 421         /* Reset Channel Registers */
 422         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 423         reg |= 0x4;
 424         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 425
 426         /* Enable override divider select and Enable Override Output Mux */
 427         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 428         reg |= 0x24;
 429         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 430
 431         /* Select VCO Divider to full rate (000) */
 432         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 433         reg &= 0x8f;
 434         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 435
 436         /* Selects active PFD MUX Input as Re-timed Data (001) */
 437         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 438         reg &= 0x3f;
 439         reg |= 0x20;
 440         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 441
 442         /* Set data rate as 10.3125 Gbps */
 443         reg = 0x0;
 444         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 445         reg = 0xb2;
 446         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 447         reg = 0x90;
 448         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 449         reg = 0xb3;
 450         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 451         reg = 0xcd;
 452         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 453 #endif
 454
 455         /* Return the default channel */
 456         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
 457 }
 458
 459 int board_early_init_f(void)
 460 {
 461         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 462 #ifdef CONFIG_HAS_FSL_XHCI_USB
 463         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 464         u32 usb_pwrfault;
 465 #endif
 466 #ifdef CONFIG_LPUART
 467         u8 uart;
 468 #endif
 469
 470         /*
 471          * Enable secure system counter for timer
 472          */
 473         out_le32(cntcr, 0x1);
 474
 475 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 476         i2c_early_init_f();
 477 #endif
 478         fsl_lsch2_early_init_f();
 479
 480 #ifdef CONFIG_HAS_FSL_XHCI_USB
 481         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 482         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 483         usb_pwrfault =
 484                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
 485                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 486                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 487         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 488 #endif
 489
 490 #ifdef CONFIG_LPUART
 491         /* We use lpuart0 as system console */
 492         uart = QIXIS_READ(brdcfg[14]);
 493         uart &= ~CFG_UART_MUX_MASK;
 494         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 495         QIXIS_WRITE(brdcfg[14], uart);
 496 #endif
 497
 498         return 0;
 499 }
 500
 501 #ifdef CONFIG_FSL_DEEP_SLEEP
 502 /* determine if it is a warm boot */
 503 bool is_warm_boot(void)
 504 {
 505 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 506         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 507
 508         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 509                 return 1;
 510
 511         return 0;
 512 }
 513 #endif
 514
 515 int config_board_mux(int ctrl_type)
 516 {
 517         u8 reg14;
 518
 519         reg14 = QIXIS_READ(brdcfg[14]);
 520
 521         switch (ctrl_type) {
 522         case MUX_TYPE_GPIO:
 523                 reg14 = (reg14 & (~0x30)) | 0x20;
 524                 break;
 525         default:
 526                 puts("Unsupported mux interface type\n");
 527                 return -1;
 528         }
 529
 530         QIXIS_WRITE(brdcfg[14], reg14);
 531
 532         return 0;
 533 }
 534
 535 int config_serdes_mux(void)
 536 {
 537         return 0;
 538 }
 539
 540
 541 #ifdef CONFIG_MISC_INIT_R
 542 int misc_init_r(void)
 543 {
 544         if (hwconfig("gpio"))
 545                 config_board_mux(MUX_TYPE_GPIO);
 546
 547         return 0;
 548 }
 549 #endif
 550
 551 int board_init(void)
 552 {
 553 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 554         erratum_a010315();
 555 #endif
 556
 557         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 558         board_retimer_init();
 559
 560 #ifdef CONFIG_SYS_FSL_SERDES
 561         config_serdes_mux();
 562 #endif
 563
 564 #ifdef CONFIG_FSL_LS_PPA
 565         ppa_init();
 566 #endif
 567
 568         return 0;
 569 }
 570
 571 #ifdef CONFIG_OF_BOARD_SETUP
 572 int ft_board_setup(void *blob, struct bd_info *bd)
 573 {
 574         u64 base[CONFIG_NR_DRAM_BANKS];
 575         u64 size[CONFIG_NR_DRAM_BANKS];
 576         u8 reg;
 577
 578         /* fixup DT for the two DDR banks */
 579         base[0] = gd->bd->bi_dram[0].start;
 580         size[0] = gd->bd->bi_dram[0].size;
 581         base[1] = gd->bd->bi_dram[1].start;
 582         size[1] = gd->bd->bi_dram[1].size;
 583
 584         fdt_fixup_memory_banks(blob, base, size, 2);
 585         ft_cpu_setup(blob, bd);
 586
 587 #ifdef CONFIG_SYS_DPAA_FMAN
 588 #ifndef CONFIG_DM_ETH
 589         fdt_fixup_fman_ethernet(blob);
 590 #endif
 591         fdt_fixup_board_enet(blob);
 592 #endif
 593
 594         fdt_fixup_icid(blob);
 595
 596         reg = QIXIS_READ(brdcfg[0]);
 597         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 598
 599         /* Disable IFC if QSPI is enabled */
 600         if (reg == 0xF)
 601                 do_fixup_by_compat(blob, "fsl,ifc",
 602                                    "status", "disabled", 8 + 1, 1);
 603
 604         return 0;
 605 }
 606 #endif
 607
 608 u8 flash_read8(void *addr)
 609 {
 610         return __raw_readb(addr + 1);
 611 }
 612
 613 void flash_write16(u16 val, void *addr)
 614 {
 615         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 616
 617         __raw_writew(shftval, addr);
 618 }
 619
 620 u16 flash_read16(void *addr)
 621 {
 622         u16 val = __raw_readw(addr);
 623
 624         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 625 }
 626
 627 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 628 void *env_sf_get_env_addr(void)
 629 {
 630         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 631 }
 632 #endif