arch/powerpc/cpu/mpc8xxx/law.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, [email protected].
   7  */
   8
   9 #include <common.h>
  10 #include <asm/bitops.h>
  11 #include <asm/global_data.h>
  12 #include <linux/compiler.h>
  13 #include <asm/fsl_law.h>
  14 #include <asm/io.h>
  15 #include <linux/log2.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
  20
  21 #ifdef CONFIG_FSL_CORENET
  22 #define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
  23 #define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
  24 #define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
  25 #define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
  26 #define LAWBAR_SHIFT 0
  27 #else
  28 #define LAW_BASE (CONFIG_SYS_IMMR + 0xc08)
  29 #define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2)
  30 #define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x)
  31 #define LAWBAR_SHIFT 12
  32 #endif
  33
  34
  35 static inline phys_addr_t get_law_base_addr(int idx)
  36 {
  37 #ifdef CONFIG_FSL_CORENET
  38         return (phys_addr_t)
  39                 ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) |
  40                 in_be32(LAWBARL_ADDR(idx));
  41 #else
  42         return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
  43 #endif
  44 }
  45
  46 static inline void set_law_base_addr(int idx, phys_addr_t addr)
  47 {
  48 #ifdef CONFIG_FSL_CORENET
  49         out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff);
  50         out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32);
  51 #else
  52         out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
  53 #endif
  54 }
  55
  56 void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
  57 {
  58         gd->arch.used_laws |= (1 << idx);
  59
  60         out_be32(LAWAR_ADDR(idx), 0);
  61         set_law_base_addr(idx, addr);
  62         out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
  63
  64         /* Read back so that we sync the writes */
  65         in_be32(LAWAR_ADDR(idx));
  66 }
  67
  68 void disable_law(u8 idx)
  69 {
  70         gd->arch.used_laws &= ~(1 << idx);
  71
  72         out_be32(LAWAR_ADDR(idx), 0);
  73         set_law_base_addr(idx, 0);
  74
  75         /* Read back so that we sync the writes */
  76         in_be32(LAWAR_ADDR(idx));
  77
  78         return;
  79 }
  80
  81 #if !defined(CONFIG_NAND_SPL) && \
  82         (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
  83 static int get_law_entry(u8 i, struct law_entry *e)
  84 {
  85         u32 lawar;
  86
  87         lawar = in_be32(LAWAR_ADDR(i));
  88
  89         if (!(lawar & LAW_EN))
  90                 return 0;
  91
  92         e->addr = get_law_base_addr(i);
  93         e->size = lawar & 0x3f;
  94         e->trgt_id = (lawar >> 20) & 0xff;
  95
  96         return 1;
  97 }
  98 #endif
  99
 100 int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 101 {
 102         u32 idx = ffz(gd->arch.used_laws);
 103
 104         if (idx >= FSL_HW_NUM_LAWS)
 105                 return -1;
 106
 107         set_law(idx, addr, sz, id);
 108
 109         return idx;
 110 }
 111
 112 #if !defined(CONFIG_NAND_SPL) && \
 113         (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
 114 int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 115 {
 116         u32 idx;
 117
 118         /* we have no LAWs free */
 119         if (gd->arch.used_laws == -1)
 120                 return -1;
 121
 122         /* grab the last free law */
 123         idx = __ilog2(~(gd->arch.used_laws));
 124
 125         if (idx >= FSL_HW_NUM_LAWS)
 126                 return -1;
 127
 128         set_law(idx, addr, sz, id);
 129
 130         return idx;
 131 }
 132
 133 struct law_entry find_law(phys_addr_t addr)
 134 {
 135         struct law_entry entry;
 136         int i;
 137
 138         entry.index = -1;
 139         entry.addr = 0;
 140         entry.size = 0;
 141         entry.trgt_id = 0;
 142
 143         for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
 144                 u64 upper;
 145
 146                 if (!get_law_entry(i, &entry))
 147                         continue;
 148
 149                 upper = entry.addr + (2ull << entry.size);
 150                 if ((addr >= entry.addr) && (addr < upper)) {
 151                         entry.index = i;
 152                         break;
 153                 }
 154         }
 155
 156         return entry;
 157 }
 158
 159 void print_laws(void)
 160 {
 161         int i;
 162         u32 lawar;
 163
 164         printf("\nLocal Access Window Configuration\n");
 165         for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
 166                 lawar = in_be32(LAWAR_ADDR(i));
 167 #ifdef CONFIG_FSL_CORENET
 168                 printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
 169                        i, in_be32(LAWBARH_ADDR(i)),
 170                        i, in_be32(LAWBARL_ADDR(i)));
 171 #else
 172                 printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
 173 #endif
 174                 printf(" LAWAR%02d: 0x%08x\n", i, lawar);
 175                 printf("\t(EN: %d TGT: 0x%02x SIZE: ",
 176                        (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
 177                 print_size(lawar_size(lawar), ")\n");
 178         }
 179
 180         return;
 181 }
 182
 183 /* use up to 2 LAWs for DDR, used the last available LAWs */
 184 int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 185 {
 186         u64 start_align, law_sz;
 187         int law_sz_enc;
 188
 189         if (start == 0)
 190                 start_align = 1ull << (LAW_SIZE_32G + 1);
 191         else
 192                 start_align = 1ull << (__ffs64(start));
 193         law_sz = min(start_align, sz);
 194         law_sz_enc = __ilog2_u64(law_sz) - 1;
 195
 196         if (set_last_law(start, law_sz_enc, id) < 0)
 197                 return -1;
 198
 199         /* recalculate size based on what was actually covered by the law */
 200         law_sz = 1ull << __ilog2_u64(law_sz);
 201
 202         /* do we still have anything to map */
 203         sz = sz - law_sz;
 204         if (sz) {
 205                 start += law_sz;
 206
 207                 start_align = 1ull << (__ffs64(start));
 208                 law_sz = min(start_align, sz);
 209                 law_sz_enc = __ilog2_u64(law_sz) - 1;
 210
 211                 if (set_last_law(start, law_sz_enc, id) < 0)
 212                         return -1;
 213         } else {
 214                 return 0;
 215         }
 216
 217         /* do we still have anything to map */
 218         sz = sz - law_sz;
 219         if (sz)
 220                 return 1;
 221
 222         return 0;
 223 }
 224 #endif /* not SPL */
 225
 226 void disable_non_ddr_laws(void)
 227 {
 228         int i;
 229         int id;
 230         for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
 231                 u32 lawar = in_be32(LAWAR_ADDR(i));
 232
 233                 if (lawar & LAW_EN) {
 234                         id = (lawar & ~LAW_EN) >> 20;
 235                         switch (id) {
 236                         case LAW_TRGT_IF_DDR_1:
 237                         case LAW_TRGT_IF_DDR_2:
 238                         case LAW_TRGT_IF_DDR_3:
 239                         case LAW_TRGT_IF_DDR_4:
 240                         case LAW_TRGT_IF_DDR_INTRLV:
 241                         case LAW_TRGT_IF_DDR_INTLV_34:
 242                         case LAW_TRGT_IF_DDR_INTLV_123:
 243                         case LAW_TRGT_IF_DDR_INTLV_1234:
 244                                                 continue;
 245                         default:
 246                                                 disable_law(i);
 247                         }
 248                 }
 249         }
 250 }
 251
 252 void init_laws(void)
 253 {
 254         int i;
 255
 256 #if FSL_HW_NUM_LAWS < 32
 257         gd->arch.used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
 258 #elif FSL_HW_NUM_LAWS == 32
 259         gd->arch.used_laws = 0;
 260 #else
 261 #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
 262 #endif
 263
 264 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500) && \
 265                                                 !defined(CONFIG_E500MC)
 266         /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms,
 267          * which is not disabled before transferring the control to uboot.
 268          * Disable the LAW 0 entry here.
 269          */
 270         disable_law(0);
 271 #endif
 272
 273 #if !defined(CONFIG_NXP_ESBC)
 274         /*
 275          * if any non DDR LAWs has been created earlier, remove them before
 276          * LAW table is parsed.
 277         */
 278         disable_non_ddr_laws();
 279 #endif
 280
 281         /*
 282          * Any LAWs that were set up before we booted assume they are meant to
 283          * be around and mark them used.
 284          */
 285         for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
 286                 u32 lawar = in_be32(LAWAR_ADDR(i));
 287
 288                 if (lawar & LAW_EN)
 289                         gd->arch.used_laws |= (1 << i);
 290         }
 291
 292         for (i = 0; i < num_law_entries; i++) {
 293                 if (law_table[i].index == -1)
 294                         set_next_law(law_table[i].addr, law_table[i].size,
 295                                         law_table[i].trgt_id);
 296                 else
 297                         set_law(law_table[i].index, law_table[i].addr,
 298                                 law_table[i].size, law_table[i].trgt_id);
 299         }
 300
 301 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 302         /* check RCW to get which port is used for boot */
 303         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 304         u32 bootloc = in_be32(&gur->rcwsr[6]);
 305         /*
 306          * in SRIO or PCIE boot we need to set specail LAWs for
 307          * SRIO or PCIE interfaces.
 308          */
 309         switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
 310         case 0x0: /* boot from PCIE1 */
 311                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 312                                 LAW_SIZE_1M,
 313                                 LAW_TRGT_IF_PCIE_1);
 314                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 315                                 LAW_SIZE_1M,
 316                                 LAW_TRGT_IF_PCIE_1);
 317                 break;
 318         case 0x1: /* boot from PCIE2 */
 319                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 320                                 LAW_SIZE_1M,
 321                                 LAW_TRGT_IF_PCIE_2);
 322                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 323                                 LAW_SIZE_1M,
 324                                 LAW_TRGT_IF_PCIE_2);
 325                 break;
 326         case 0x2: /* boot from PCIE3 */
 327                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 328                                 LAW_SIZE_1M,
 329                                 LAW_TRGT_IF_PCIE_3);
 330                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 331                                 LAW_SIZE_1M,
 332                                 LAW_TRGT_IF_PCIE_3);
 333                 break;
 334         case 0x8: /* boot from SRIO1 */
 335                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 336                                 LAW_SIZE_1M,
 337                                 LAW_TRGT_IF_RIO_1);
 338                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 339                                 LAW_SIZE_1M,
 340                                 LAW_TRGT_IF_RIO_1);
 341                 break;
 342         case 0x9: /* boot from SRIO2 */
 343                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 344                                 LAW_SIZE_1M,
 345                                 LAW_TRGT_IF_RIO_2);
 346                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 347                                 LAW_SIZE_1M,
 348                                 LAW_TRGT_IF_RIO_2);
 349                 break;
 350         default:
 351                 break;
 352         }
 353 #endif
 354
 355         return ;
 356 }