1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/global_data.h>
13 #include <mach/pic32.h>
15 #include <dt-bindings/clock/microchip,clock.h>
24 #define CLK_MHZ(x) ((x) / 1000000)
26 DECLARE_GLOBAL_DATA_PTR;
28 static ulong rate(int id)
35 ret = uclass_get_device(UCLASS_CLK, 0, &dev);
37 printf("clk-uclass not found\n");
42 ret = clk_request(dev, &clk);
46 rate = clk_get_rate(&clk);
53 static ulong clk_get_cpu_rate(void)
58 /* initialize prefetch module related to cpu_clk */
59 static void prefetch_init(void)
61 struct pic32_reg_atomic *regs;
62 const void __iomem *base;
66 /* cpu frequency in MHZ */
67 rate = clk_get_cpu_rate() / 1000000;
69 /* get flash ECC type */
70 base = pic32_get_syscfg_base();
71 v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
89 regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs));
90 writel(nr_waits, ®s->raw);
92 /* Enable prefetch for all */
93 writel(0x30, ®s->set);
97 /* arch specific CPU init after DM */
98 int arch_cpu_init_dm(void)
105 /* Un-gate DDR2 modules (gated by default) */
106 static void ddr2_pmd_ungate(void)
110 regs = pic32_get_syscfg_base();
111 writel(0, regs + PMD7);
114 /* initialize the DDR2 Controller and DDR2 PHY */
120 gd->ram_size = ddr2_calculate_size();
125 int misc_init_r(void)
131 #ifdef CONFIG_DISPLAY_BOARDINFO
132 const char *get_core_name(void)
137 proc_id = read_c0_prid();
149 #ifdef CONFIG_CMD_CLK
151 int soc_clk_dump(void)
155 printf("PLL Speed: %lu MHz\n",
156 CLK_MHZ(rate(PLLCLK)));
158 printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
160 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
162 for (i = PB1CLK; i <= PB7CLK; i++)
163 printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
166 for (i = REF1CLK; i <= REF5CLK; i++)
167 printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,