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common: Drop asm/global_data.h from common header
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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015
4  * Purna Chandra Mandal <[email protected]>
5  *
6  */
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <init.h>
11 #include <malloc.h>
12 #include <asm/global_data.h>
13 #include <mach/pic32.h>
14 #include <mach/ddr.h>
15 #include <dt-bindings/clock/microchip,clock.h>
16
17 /* Flash prefetch */
18 #define PRECON          0x00
19
20 /* Flash ECCCON */
21 #define ECC_MASK        0x03
22 #define ECC_SHIFT       4
23
24 #define CLK_MHZ(x)      ((x) / 1000000)
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 static ulong rate(int id)
29 {
30         int ret;
31         struct udevice *dev;
32         struct clk clk;
33         ulong rate;
34
35         ret = uclass_get_device(UCLASS_CLK, 0, &dev);
36         if (ret) {
37                 printf("clk-uclass not found\n");
38                 return 0;
39         }
40
41         clk.id = id;
42         ret = clk_request(dev, &clk);
43         if (ret < 0)
44                 return ret;
45
46         rate = clk_get_rate(&clk);
47
48         clk_free(&clk);
49
50         return rate;
51 }
52
53 static ulong clk_get_cpu_rate(void)
54 {
55         return rate(PB7CLK);
56 }
57
58 /* initialize prefetch module related to cpu_clk */
59 static void prefetch_init(void)
60 {
61         struct pic32_reg_atomic *regs;
62         const void __iomem *base;
63         int v, nr_waits;
64         ulong rate;
65
66         /* cpu frequency in MHZ */
67         rate = clk_get_cpu_rate() / 1000000;
68
69         /* get flash ECC type */
70         base = pic32_get_syscfg_base();
71         v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
72
73         if (v < 2) {
74                 if (rate < 66)
75                         nr_waits = 0;
76                 else if (rate < 133)
77                         nr_waits = 1;
78                 else
79                         nr_waits = 2;
80         } else {
81                 if (rate <= 83)
82                         nr_waits = 0;
83                 else if (rate <= 166)
84                         nr_waits = 1;
85                 else
86                         nr_waits = 2;
87         }
88
89         regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs));
90         writel(nr_waits, &regs->raw);
91
92         /* Enable prefetch for all */
93         writel(0x30, &regs->set);
94         iounmap(regs);
95 }
96
97 /* arch specific CPU init after DM */
98 int arch_cpu_init_dm(void)
99 {
100         /* flash prefetch */
101         prefetch_init();
102         return 0;
103 }
104
105 /* Un-gate DDR2 modules (gated by default) */
106 static void ddr2_pmd_ungate(void)
107 {
108         void __iomem *regs;
109
110         regs = pic32_get_syscfg_base();
111         writel(0, regs + PMD7);
112 }
113
114 /* initialize the DDR2 Controller and DDR2 PHY */
115 int dram_init(void)
116 {
117         ddr2_pmd_ungate();
118         ddr2_phy_init();
119         ddr2_ctrl_init();
120         gd->ram_size = ddr2_calculate_size();
121
122         return 0;
123 }
124
125 int misc_init_r(void)
126 {
127         set_io_port_base(0);
128         return 0;
129 }
130
131 #ifdef CONFIG_DISPLAY_BOARDINFO
132 const char *get_core_name(void)
133 {
134         u32 proc_id;
135         const char *str;
136
137         proc_id = read_c0_prid();
138         switch (proc_id) {
139         case 0x19e28:
140                 str = "PIC32MZ[DA]";
141                 break;
142         default:
143                 str = "UNKNOWN";
144         }
145
146         return str;
147 }
148 #endif
149 #ifdef CONFIG_CMD_CLK
150
151 int soc_clk_dump(void)
152 {
153         int i;
154
155         printf("PLL Speed: %lu MHz\n",
156                CLK_MHZ(rate(PLLCLK)));
157
158         printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
159
160         printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
161
162         for (i = PB1CLK; i <= PB7CLK; i++)
163                 printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
164                        CLK_MHZ(rate(i)));
165
166         for (i = REF1CLK; i <= REF5CLK; i++)
167                 printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
168                        CLK_MHZ(rate(i)));
169         return 0;
170 }
171 #endif
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