include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #endif
  18
  19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  20 /* Set 1M boot space */
  21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28
  29 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  30 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  31 #endif
  32
  33 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  34 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  35
  36 #define CONFIG_SYS_SRIO
  37 #define CONFIG_SRIO1                    /* SRIO port 1 */
  38 #define CONFIG_SRIO2                    /* SRIO port 2 */
  39 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  40 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  41
  42 #ifndef __ASSEMBLY__
  43 #include <linux/stringify.h>
  44 #endif
  45
  46 /*
  47  * These can be toggled for performance analysis, otherwise use default.
  48  */
  49 #define CONFIG_SYS_CACHE_STASHING
  50 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  51
  52 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  53
  54 /*
  55  *  Config the L3 Cache as L3 SRAM
  56  */
  57 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  58 #ifdef CONFIG_PHYS_64BIT
  59 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  60                 CONFIG_RAMBOOT_TEXT_BASE)
  61 #else
  62 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  63 #endif
  64 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  65 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  66
  67 #ifdef CONFIG_PHYS_64BIT
  68 #define CONFIG_SYS_DCSRBAR              0xf0000000
  69 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  70 #endif
  71
  72 /* EEPROM */
  73 #define CONFIG_SYS_I2C_EEPROM_NXID
  74 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  75
  76 /*
  77  * DDR Setup
  78  */
  79 #define CONFIG_VERY_BIG_RAM
  80 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  81 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  82
  83 #define SPD_EEPROM_ADDRESS      0x52
  84 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  85
  86 /*
  87  * Local Bus Definitions
  88  */
  89
  90 /* Set the local bus clock 1/8 of platform clock */
  91 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  92
  93 /*
  94  * This board doesn't have a promjet connector.
  95  * However, it uses commone corenet board LAW and TLB.
  96  * It is necessary to use the same start address with proper offset.
  97  */
  98 #define CONFIG_SYS_FLASH_BASE           0xe0000000
  99 #ifdef CONFIG_PHYS_64BIT
 100 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 101 #else
 102 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 103 #endif
 104
 105 #define CONFIG_SYS_FLASH_BR_PRELIM \
 106                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 107                 BR_PS_16 | BR_V)
 108 #define CONFIG_SYS_FLASH_OR_PRELIM \
 109                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 110                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 111
 112 #define CONFIG_FSL_CPLD
 113 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 114 #ifdef CONFIG_PHYS_64BIT
 115 #define CPLD_BASE_PHYS          0xfffdf0000ull
 116 #else
 117 #define CPLD_BASE_PHYS          CPLD_BASE
 118 #endif
 119
 120 #define PIXIS_LBMAP_SWITCH      7
 121 #define PIXIS_LBMAP_MASK        0xf0
 122 #define PIXIS_LBMAP_SHIFT       4
 123 #define PIXIS_LBMAP_ALTBANK     0x40
 124
 125 #define CONFIG_SYS_FLASH_QUIET_TEST
 126 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 127
 128 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 129 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 130 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 131
 132 #if defined(CONFIG_RAMBOOT_PBL)
 133 #define CONFIG_SYS_RAMBOOT
 134 #endif
 135
 136 /* Nand Flash */
 137 #ifdef CONFIG_NAND_FSL_ELBC
 138 #define CONFIG_SYS_NAND_BASE            0xffa00000
 139 #ifdef CONFIG_PHYS_64BIT
 140 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 141 #else
 142 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 143 #endif
 144
 145 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 146 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 147
 148 /* NAND flash config */
 149 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 150                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 151                                | BR_PS_8               /* Port Size = 8 bit */ \
 152                                | BR_MS_FCM             /* MSEL = FCM */ \
 153                                | BR_V)                 /* valid */
 154 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 155                                | OR_FCM_PGS            /* Large Page*/ \
 156                                | OR_FCM_CSCT \
 157                                | OR_FCM_CST \
 158                                | OR_FCM_CHT \
 159                                | OR_FCM_SCY_1 \
 160                                | OR_FCM_TRLX \
 161                                | OR_FCM_EHTR)
 162 #endif /* CONFIG_NAND_FSL_ELBC */
 163
 164 #define CONFIG_SYS_FLASH_EMPTY_INFO
 165 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 166
 167 #define CONFIG_HWCONFIG
 168
 169 /* define to use L1 as initial stack */
 170 #define CONFIG_L1_INIT_RAM
 171 #define CONFIG_SYS_INIT_RAM_LOCK
 172 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 173 #ifdef CONFIG_PHYS_64BIT
 174 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 175 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 176 /* The assembler doesn't like typecast */
 177 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 178         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 179           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 180 #else
 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 184 #endif
 185 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 186
 187 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 188
 189 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 190
 191 /* Serial Port - controlled on board with jumper J8
 192  * open - index 2
 193  * shorted - index 1
 194  */
 195 #define CONFIG_SYS_NS16550_SERIAL
 196 #define CONFIG_SYS_NS16550_REG_SIZE     1
 197 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 198
 199 #define CONFIG_SYS_BAUDRATE_TABLE       \
 200         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 201
 202 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 203 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 204 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 205 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 206
 207 /* I2C */
 208
 209
 210 /*
 211  * RapidIO
 212  */
 213 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 214 #ifdef CONFIG_PHYS_64BIT
 215 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 216 #else
 217 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 218 #endif
 219 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 220
 221 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 222 #ifdef CONFIG_PHYS_64BIT
 223 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 224 #else
 225 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 226 #endif
 227 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 228
 229 /*
 230  * for slave u-boot IMAGE instored in master memory space,
 231  * PHYS must be aligned based on the SIZE
 232  */
 233 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 234 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 235 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 236 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 237 /*
 238  * for slave UCODE and ENV instored in master memory space,
 239  * PHYS must be aligned based on the SIZE
 240  */
 241 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 242 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 243 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 244
 245 /* slave core release by master*/
 246 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 247 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 248
 249 /*
 250  * SRIO_PCIE_BOOT - SLAVE
 251  */
 252 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 253 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 254 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 255                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 256 #endif
 257
 258 /*
 259  * eSPI - Enhanced SPI
 260  */
 261
 262 /*
 263  * General PCI
 264  * Memory space is mapped 1-1, but I/O space must start from 0.
 265  */
 266
 267 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 268 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 269 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 270 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 271 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 272
 273 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 274 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 275 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 276 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 277 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 278
 279 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 280 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 281 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 282 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 283 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 284
 285 /* Qman/Bman */
 286 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 287 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 288 #ifdef CONFIG_PHYS_64BIT
 289 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 290 #else
 291 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 292 #endif
 293 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 294 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 295 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 296 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 297 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 298 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 299                                         CONFIG_SYS_BMAN_CENA_SIZE)
 300 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 301 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 302 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 303 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 304 #ifdef CONFIG_PHYS_64BIT
 305 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 306 #else
 307 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 308 #endif
 309 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 310 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 311 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 312 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 313 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 314 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 315                                         CONFIG_SYS_QMAN_CENA_SIZE)
 316 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 317 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 318
 319 #define CONFIG_SYS_DPAA_FMAN
 320 #define CONFIG_SYS_DPAA_PME
 321 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 322
 323 #ifdef CONFIG_FMAN_ENET
 324 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 325 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 326 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 327 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 328 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 329
 330 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 331 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 332 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 333 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 334
 335 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 336
 337 #define CONFIG_SYS_TBIPA_VALUE  8
 338 #endif
 339
 340 /*
 341  * Environment
 342  */
 343 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 344 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 345
 346 #ifdef CONFIG_MMC
 347 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 348 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 349 #endif
 350
 351 /*
 352  * Miscellaneous configurable options
 353  */
 354
 355 /*
 356  * For booting Linux, the board info and command line data
 357  * have to be in the first 64 MB of memory, since this is
 358  * the maximum mapped by the Linux kernel during initialization.
 359  */
 360 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 361 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 362
 363 /*
 364  * Environment Configuration
 365  */
 366 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 367 #define CONFIG_UBOOTPATH        u-boot.bin
 368
 369 #define __USB_PHY_TYPE  utmi
 370
 371 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 372         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 373         "bank_intlv=cs0_cs1\0"                                  \
 374         "netdev=eth0\0"                                         \
 375         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 376         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 377         "tftpflash=tftpboot $loadaddr $uboot && "               \
 378         "protect off $ubootaddr +$filesize && "                 \
 379         "erase $ubootaddr +$filesize && "                       \
 380         "cp.b $loadaddr $ubootaddr $filesize && "               \
 381         "protect on $ubootaddr +$filesize && "                  \
 382         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 383         "consoledev=ttyS0\0"                                    \
 384         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 385         "usb_dr_mode=host\0"                                    \
 386         "ramdiskaddr=2000000\0"                                 \
 387         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 388         "fdtaddr=1e00000\0"                                     \
 389         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 390         "bdev=sda3\0"
 391
 392 #include <asm/fsl_secure_boot.h>
 393
 394 #endif  /* __CONFIG_H */