include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #include "../board/freescale/common/ics307_clk.h"
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  19 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  20 #endif
  21
  22 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  23 /* Set 1M boot space */
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  25 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  26                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  28 #endif
  29
  30 /* High Level Configuration Options */
  31
  32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  34 #endif
  35
  36 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  37
  38 /*
  39  * These can be toggled for performance analysis, otherwise use default.
  40  */
  41 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  42 #ifdef CONFIG_DDR_ECC
  43 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  44 #endif
  45
  46 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  47
  48 /*
  49  *  Config the L3 Cache as L3 SRAM
  50  */
  51 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  52 #ifdef CONFIG_PHYS_64BIT
  53 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  54 #else
  55 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  56 #endif
  57 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  58 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  59
  60 #ifdef CONFIG_PHYS_64BIT
  61 #define CONFIG_SYS_DCSRBAR              0xf0000000
  62 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  63 #endif
  64
  65 /* EEPROM */
  66 #define CONFIG_SYS_I2C_EEPROM_NXID
  67 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  68
  69 /*
  70  * DDR Setup
  71  */
  72 #define CONFIG_VERY_BIG_RAM
  73 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  74 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  75
  76 #define SPD_EEPROM_ADDRESS1     0x51
  77 #define SPD_EEPROM_ADDRESS2     0x52
  78 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
  79 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  80
  81 /*
  82  * Local Bus Definitions
  83  */
  84
  85 /* Set the local bus clock 1/8 of platform clock */
  86 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  87
  88 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
  89 #ifdef CONFIG_PHYS_64BIT
  90 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
  91 #else
  92 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  93 #endif
  94
  95 #define CONFIG_SYS_FLASH_BR_PRELIM \
  96                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
  97                  | BR_PS_16 | BR_V)
  98 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
  99                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 100
 101 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 102 #ifdef CONFIG_PHYS_64BIT
 103 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 104 #else
 105 #define PIXIS_BASE_PHYS         PIXIS_BASE
 106 #endif
 107
 108 #define PIXIS_LBMAP_SWITCH      7
 109 #define PIXIS_LBMAP_MASK        0xf0
 110 #define PIXIS_LBMAP_SHIFT       4
 111 #define PIXIS_LBMAP_ALTBANK     0x40
 112
 113 #define CONFIG_SYS_FLASH_QUIET_TEST
 114 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 115
 116 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 117 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 118 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 119
 120 /* Nand Flash */
 121 #ifdef CONFIG_NAND_FSL_ELBC
 122 #define CONFIG_SYS_NAND_BASE            0xffa00000
 123 #ifdef CONFIG_PHYS_64BIT
 124 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 125 #else
 126 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 127 #endif
 128
 129 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 130 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 131
 132 /* NAND flash config */
 133 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 134                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 135                                | BR_PS_8               /* Port Size = 8 bit */ \
 136                                | BR_MS_FCM             /* MSEL = FCM */ \
 137                                | BR_V)                 /* valid */
 138 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 139                                | OR_FCM_PGS            /* Large Page*/ \
 140                                | OR_FCM_CSCT \
 141                                | OR_FCM_CST \
 142                                | OR_FCM_CHT \
 143                                | OR_FCM_SCY_1 \
 144                                | OR_FCM_TRLX \
 145                                | OR_FCM_EHTR)
 146 #endif /* CONFIG_NAND_FSL_ELBC */
 147
 148 #define CONFIG_SYS_FLASH_EMPTY_INFO
 149 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 150
 151 #define CONFIG_HWCONFIG
 152
 153 /* define to use L1 as initial stack */
 154 #define CONFIG_L1_INIT_RAM
 155 #define CONFIG_SYS_INIT_RAM_LOCK
 156 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 157 #ifdef CONFIG_PHYS_64BIT
 158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 160 /* The assembler doesn't like typecast */
 161 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 162         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 163           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 164 #else
 165 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 166 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 167 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 168 #endif
 169 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 170
 171 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 172
 173 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 174
 175 /* Serial Port - controlled on board with jumper J8
 176  * open - index 2
 177  * shorted - index 1
 178  */
 179 #define CONFIG_SYS_NS16550_SERIAL
 180 #define CONFIG_SYS_NS16550_REG_SIZE     1
 181 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 182
 183 #define CONFIG_SYS_BAUDRATE_TABLE       \
 184         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 185
 186 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 187 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 188 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 189 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 190
 191 /* I2C */
 192
 193 /*
 194  * RapidIO
 195  */
 196 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 197 #ifdef CONFIG_PHYS_64BIT
 198 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 199 #else
 200 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 201 #endif
 202 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 203
 204 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 205 #ifdef CONFIG_PHYS_64BIT
 206 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 207 #else
 208 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 209 #endif
 210 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 211
 212 /*
 213  * for slave u-boot IMAGE instored in master memory space,
 214  * PHYS must be aligned based on the SIZE
 215  */
 216 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 217 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 218 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 219 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 220 /*
 221  * for slave UCODE and ENV instored in master memory space,
 222  * PHYS must be aligned based on the SIZE
 223  */
 224 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 225 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 226 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 227
 228 /* slave core release by master*/
 229 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 230 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 231
 232 /*
 233  * SRIO_PCIE_BOOT - SLAVE
 234  */
 235 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 236 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 237 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 238                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 239 #endif
 240
 241 /*
 242  * eSPI - Enhanced SPI
 243  */
 244
 245 /*
 246  * General PCI
 247  * Memory space is mapped 1-1, but I/O space must start from 0.
 248  */
 249
 250 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 251 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 252 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 253 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 254 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 255
 256 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 257 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 258 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 259 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 260 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 261
 262 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 263 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 264 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 265 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 266 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 267
 268 /* controller 4, Base address 203000 */
 269 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 270 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 271
 272 /* Qman/Bman */
 273 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 274 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 275 #ifdef CONFIG_PHYS_64BIT
 276 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 277 #else
 278 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 279 #endif
 280 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 281 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 282 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 283 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 284 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 285 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 286                                         CONFIG_SYS_BMAN_CENA_SIZE)
 287 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 288 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 289 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 290 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 291 #ifdef CONFIG_PHYS_64BIT
 292 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 293 #else
 294 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 295 #endif
 296 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 297 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 298 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 299 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 300 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 301 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 302                                         CONFIG_SYS_QMAN_CENA_SIZE)
 303 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 304 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 305
 306 #define CONFIG_SYS_DPAA_FMAN
 307 #define CONFIG_SYS_DPAA_PME
 308 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 309
 310 #ifdef CONFIG_FMAN_ENET
 311 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 312 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 313 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 314 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 315 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 316
 317 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 318 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 319 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 320 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 321 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 322
 323 #define CONFIG_SYS_TBIPA_VALUE  8
 324 #endif
 325
 326 /*
 327  * Environment
 328  */
 329 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 330 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 331
 332 #ifdef CONFIG_MMC
 333 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 334 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 335 #endif
 336
 337 /*
 338  * Miscellaneous configurable options
 339  */
 340
 341 /*
 342  * For booting Linux, the board info and command line data
 343  * have to be in the first 64 MB of memory, since this is
 344  * the maximum mapped by the Linux kernel during initialization.
 345  */
 346 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 347
 348 /*
 349  * Environment Configuration
 350  */
 351 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 352 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 353
 354 #ifdef CONFIG_TARGET_P4080DS
 355 #define __USB_PHY_TYPE  ulpi
 356 #else
 357 #define __USB_PHY_TYPE  utmi
 358 #endif
 359
 360 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 361         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 362         "bank_intlv=cs0_cs1;"                                   \
 363         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 364         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 365         "netdev=eth0\0"                                         \
 366         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 367         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 368         "tftpflash=tftpboot $loadaddr $uboot && "               \
 369         "protect off $ubootaddr +$filesize && "                 \
 370         "erase $ubootaddr +$filesize && "                       \
 371         "cp.b $loadaddr $ubootaddr $filesize && "               \
 372         "protect on $ubootaddr +$filesize && "                  \
 373         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 374         "consoledev=ttyS0\0"                                    \
 375         "ramdiskaddr=2000000\0"                                 \
 376         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 377         "fdtaddr=1e00000\0"                                     \
 378         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 379         "bdev=sda3\0"
 380
 381 #include <asm/fsl_secure_boot.h>
 382
 383 #endif  /* __CONFIG_H */